JP2001144189A - Semiconductor integrated circuit device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device and its manufacturing method that suppress function of Vt and have an MOSFET, for preventing degree of integration from being reduced. SOLUTION: In a MOSFET provided in an element region being divided by a trench element separation region 2 formed on a P-type silicon substrate 1, the center part of a channel region 10 is set to a P--channel region 11 of low Vt, and each of both end parts near the boundary to the trench element separation region 2 is set to a P+-channel region 12 of high Vt.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly to an insulated gate field effect transistor (hereinafter, referred to as a MOSFET) constituted by a pair in an amplifier circuit and its manufacture. About the method.

[0002]

2. Description of the Related Art Conventionally, an element isolation technique called a LOCOS technique, in which a channel stopper is provided at the bottom and a thick thermal oxide film partially buried in a substrate is formed by a selective thermal oxidation method, is generally used. Was.

[0003] However, this technique has disadvantages such as requiring high-temperature, long-time thermal oxidation, generating thermal distortion, forming an undesirable bird's beak at the boundary, and making it impossible to narrow the element isolation width. are doing.

For this reason, trench element isolation technology has recently been widely used. This trench element isolation technology is based on trench etching-oxide film growth-CMP
The element isolation region is formed by a process of (chemical mechanical polishing).

Hereinafter, a conventional trench element isolation will be described. FIG. 7 is a plan view, and FIG. 8 is a cross-sectional view showing each step in the AA section of FIG.

A silicon nitride film pattern 15 is formed on the main surface of the P-type silicon substrate 1 (FIG. 8A), and a trench (groove) 16 is formed using the silicon nitride film pattern 15 as a mask (FIG. 8B). )), Silicon oxide film 17 by CVD
Is deposited over the entire surface to fill the trench 16 with the silicon oxide film 17 (FIG. 8C).

The silicon oxide film 1 is formed by CMP using the silicon nitride film pattern 15 as an etching stopper.
7 is flattened (FIG. 8D), and after removing the silicon nitride film pattern 15, a gate oxide film 4 and a gate electrode 5 are formed on the channel region 10 (FIG. 8E). On the other hand, N ⁺ source and drain regions 7 and 8 are formed in a self-aligned manner (FIG. 1). Thus, trench isolation region 2 composed of trench 16 and buried oxide film 17 is formed.
MOSFETs are formed in the element regions partitioned by.

[0008] However, in the above-mentioned prior art, CM
In the P step, a crystal defect due to strain occurs in a portion A of the element region adjacent to the trench element isolation region 2, and thus has a gate voltage-drain current characteristic as shown in FIG. Voltage (hereinafter, Vt,
), Which causes a plurality of MOSFs
The variation between Vt of ET becomes large.

For example, in an amplifier circuit using two MOSFETs as a pair, Vt may greatly change from several tens mV to several hundred mV due to the influence of the portion A. In this case, the circuit can operate normally. Disappears.

Although the above description has been made with reference to an N-channel MOSFET, the same applies to a P-channel MOSFET.

On the other hand, in a MOSFET having a ring gate shape as shown in FIG.
As shown in (B), normal gate voltage-drain current characteristics are obtained, and fluctuations in Vt of the MOSFET are reduced to such an extent that no problem occurs.

That is, in FIG. 10, a ring-shaped channel region 20 and a gate electrode 25 thereon are provided in an element region partitioned by the trench element isolation region 2, and an N ⁺ source region (or drain region) 27 is provided inside the ring-shaped channel region 20. And an N ⁺ drain region (or source region) 2 outside
8, the location A where a crystal defect occurs adjacent to the trench isolation region 2 is located on the outer periphery of the N ⁺ drain region 28 and does not affect the characteristics including Vt.

However, the occupied area of the MOSFET having the ring gate shape as shown in FIG. 10 is twice as large as that of the normal MOSFET having the linear gate shape as shown in FIGS. This increases the chip size.

[0014]

As described above,
The prior art shown in FIGS. 7 and 8 has a problem that fluctuations in characteristics including Vt become large, and this causes a problem in normal operation particularly in an amplifier circuit requiring a pair of MOSFETs. .

On the other hand, in the prior art shown in FIG.
There is a problem that the area required for the SFET is increased and the degree of integration is reduced.

Accordingly, an object of the present invention is to provide a MOSFET which suppresses fluctuations in Vt and does not reduce the degree of integration.
An object of the present invention is to provide a semiconductor integrated circuit device provided with T.

Another object of the present invention is to provide a method for manufacturing the semiconductor integrated circuit device.

[0018]

A feature of the present invention is a semiconductor integrated circuit device having an N-channel or P-channel MOSFET provided in an element region defined by a trench element isolation region formed in a semiconductor substrate. In the above, Vt of the channel region of the transistor is
An end portion located near the boundary with the trench isolation region is higher than a central portion separated from the trench isolation region. That is, in the case of an N-channel type, Vt of the end portion is Vt of the central portion. And in the case of the P-channel type, the Vt of the end portion is increased.
Is a semiconductor integrated circuit device in which the voltage Vt increases in the negative direction from Vt in the central portion.

Here, the Vt of the end portion and the central portion is
Can be controlled by the configuration of impurities in the portion. In this case, it is preferable that an element having the same conductivity type as that of the semiconductor substrate be ion-implanted into the end portion, and an element having a conductivity type opposite to that of the semiconductor substrate be ion-implanted into the center portion.

Further, an amplifier circuit can be constituted by the above-mentioned MOSFET.

Another feature of the present invention is that the P-type (or N-type)
Forming a mask pattern on the surface of the semiconductor substrate of the (type), forming a trench for element isolation in the semiconductor substrate using at least the mask pattern as a mask, and depositing an insulating layer over the entire surface to form the trench for element isolation. Filling the insulating layer, flattening the insulating layer by a chemical mechanical polishing method using the mask pattern as an etching stopper, and removing the mask pattern. At least a N-type (or P-type) The step of ion-implanting the element with low energy and the step of ion-implanting a P-type (or N-type) element with low energy into the end of the channel region while at least masking the center of the channel region. And a method of manufacturing a semiconductor integrated circuit having a MOSFET. Here, after the step of removing the mask pattern, a step of implanting ions of the first conductivity type with high energy may be provided to form the channel stopper region inside the semiconductor substrate.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIGS. 1 and 2 show an MO according to an embodiment of the present invention.
FIG. 1A is a diagram showing an SFET, and FIG.
FIG. 2B is a cross-sectional view taken along the line AA in FIG. Also,
2A is a cross-sectional view taken along a line BB in FIG. 1A, and FIG. 2B is a cross-sectional view taken along a line CC in FIG. 1A.

A trench (groove) 1 is formed in a P-type silicon substrate 1.
The trench element isolation region 2 is formed by the silicon oxide film 17 filling the trench 6 and the trench 16, and a peak is formed at a depth of 300 nm from the main surface (surface) of the substrate in the element region in contact with the bottom of the trench element isolation region 2. A certain P ⁺ channel stopper region 3 is formed.

The MOSFET formed in the element region partitioned and surrounded by the trench element isolation region 2 is provided on the channel region 10, the N ⁺ source and drain regions 7, 8 and the channel region via the gate oxide film 4. And a side oxide film 6 on the side surface of the gate electrode.

In the present invention, of the width W of the channel region 10, both end portions (boundary portions) (width W2) in contact with the trench element isolation region 2 have a depth of 20n from the main surface of the substrate.
m ⁺ P channel region 12 and its width W2
Is 0.4 μm. And the P ⁺ channel region 12
And the central portion of the channel region (width W
1) is a P ^- channel region 11 having a depth of 20 nm from the main surface of the substrate.

As a result, the Vt of the central portion (P ^- channel region 11) serving as the main operation region of the MOSFET increases by +
0.5 V, and Vt at the end portion (P ⁺ channel region 12) is +0.7 V.

That is, since the P ^- channel region 11 is formed by introducing a pentavalent element such as phosphorus or arsenic into the P-type substrate, when a positive voltage is applied to the gate electrode, electrons are sufficiently generated. The current between the source and the drain easily flows.

On the other hand, since the P ⁺ channel region 12 is formed by introducing a trivalent element such as boron into a P-type substrate, when a positive voltage is applied to the gate electrode, electrons are sufficiently collected. Therefore, current between the source and the drain hardly flows.

For this reason, the characteristics of the MOSFET are determined by the P ^- channel region 11 in the central portion having the channel width W1, and even if a crystal defect occurs at the interface portion A with the trench isolation region 2, it does not matter. And the variation in Vt among the plurality of MOSFETs can be suppressed to such an extent that the circuit is not hindered.

According to various experimental studies by the inventor of the present invention, in an actual MOSFET, the width W2 of the P ⁺ channel region 12 at the end portion is set to 0.3 μm to 0.6 μm.
V in central P ^- channel region (W1) 11
V of the P ⁺ channel region (W2) 12 at the end portion than t
By increasing t by +0.1 V to +0.4 V, that is, by increasing Vt by 0.1 V to 0.4 V in absolute value, the influence of the interface portion A without affecting the characteristics of the original MOSFET is obtained. It has been found that the effect of suppressing the above can be obtained.

Next, a manufacturing method of the embodiment will be described with reference to FIGS.

First, in FIG. 3A, a silicon nitride film pattern 15 is formed on the P-type main surface of the P-type silicon substrate 1. In this case, it can be formed via a thin silicon oxide film called a pad oxide film.

Next, in FIG. 3B, a trench (groove) 16 is formed by dry etching or wet etching using the silicon nitride film pattern 15 as a mask. In this case, the photoresist pattern used when forming the silicon nitride film pattern 15 from the silicon nitride film can be left as it is, and this photoresist pattern can also be used as a mask when forming the trench.

Next, in FIG. 3C, if a photoresist pattern remains, after removing it, a silicon oxide film 17 is deposited on the entire surface by CVD or the like so as to fill the trench 16. This silicon oxide film 17 is not only a silicon dioxide oxide film but also a PSG film and a BSG film.
A film containing impurities such as a film and a BPSG film can also be used.

Next, in FIG. 3D, CMP (CMP) is performed using the silicon nitride film pattern 15 as an etching stopper.
chemical Mechanical Polish
ing) to flatten the silicon oxide film 17. That is, the silicon substrate 1 is fixed to a carrier which is rotated by a spindle with the back side (the lower side in the figure) facing upward, and the silicon substrate 1 is brought into contact with the polishing pad into which the abrasive has been applied with the front side (the upper side in the figure) facing downward. The silicon oxide film 17 is polished and flattened by rotation and pressurization by a spindle.

Next, in FIG. 3E, the silicon nitride film pattern 15 is removed with hot phosphoric acid. When a thin silicon oxide film is formed under the silicon nitride film pattern 15, after the series of ion implantation steps described later, the thin silicon oxide film is removed before forming the gate oxide film. Is preferred from the viewpoint of preventing substrate surface damage.

Then, boron is applied to the entire surface at an energy of 200 k.
eV, ion implantation at a dose of 2 × 10 ¹³ cm ⁻² and subsequent activation heat treatment make contact with the bottom of the trench isolation region 2 to 300 nm from the main surface (front surface) of the substrate in the element region.
A P ⁺ channel stopper region 3 having a peak at the depth of is formed.

Next, in FIG. 4, channel doping is performed at the center of the channel region. 4A is a plan view, and FIG. 4B is a cross-sectional view taken along the line AA in FIG. 4A.

A photoresist pattern 18 having an opening 18A is formed, and arsenic as an N-type impurity is passed through the opening 18A at a low energy of 20 keV and a low dose of 1 × 10 ¹¹ cm.
Ion implantation at ^-2 . This amount is the P-type silicon substrate 1
Since it is smaller than the amount of the type impurity, it is canceled by the subsequent activation heat treatment to form a P ^- channel region 11 having a depth of 20 nm from the main surface (surface). The portion protruding beyond the channel formation boundary indicated by the two-dot chain line in the channel length direction becomes the N ⁺ source and drain regions because the amount of N-type impurities in the source and drain is larger.

Next, in FIG. 5, channel doping is performed at the end of the channel region. FIG. 5A is a plan view, and FIG. 5B is a cross-sectional view taken along the line AA of FIG. 5A.

A photoresist pattern 19 having an opening 19A is formed, boron of a P-type impurity is ion-implanted at a low energy and a low dose through the opening 19A, and a depth from the main surface (surface) is obtained by an activation heat treatment. A 20 nm P ⁺ channel region 12 is formed. The portion protruding beyond the channel formation boundary indicated by the two-dot chain line in the channel length direction becomes the N ⁺ source and drain regions because the amount of N-type impurities in the source and drain is larger. Also, the opening 19A is overlapped with the trench isolation region 2 so that the P ⁺
Care must be taken so that No. 2 is formed.

Further, the steps of FIG. 4 and FIG. 5 may be reversed. Further, since the implanted portions other than the channel region in the step of FIG. 4 become the N ⁺ source and drain regions and the P ⁺ channel region 12, ion implantation of the low energy, low dose N-type impurity in FIG. The process may be performed on the entire surface without using a mask. FIG.
The mask for ion implantation of the P-type impurity in the step of
Channel region center, ie, P ^- channel region 1
Any mask may be used as long as it masks only one or the same area.

What is necessary is that the effective impurity concentrations of the P ^- channel region 11 and the P ⁺ channel region 12 are set at the respective predetermined Vt at the time when the steps of FIGS.
Is to be obtained.

Next, if a thin silicon oxide film has been formed on the surface, the film is removed with hydrofluoric acid, and a gate silicon oxide film 4 is formed by thermal oxidation. An extended gate electrode 5 is formed from polycrystalline silicon, and a side surface oxide film 6 is formed on the side surface of the gate electrode. Using this gate electrode structure as a part of a mask, phosphorus is applied at an energy of 40 keV and a dose of 1 × 10 ¹⁵ cm ⁻ Ion implantation is performed in step ² , and N ⁺ source and drain regions 7 and 8 are formed at a depth of 30 nm from the main surface (front surface) of the substrate by activation heat treatment, thereby obtaining the MOSFET shown in FIGS.

Although only the N-channel MOSFET has been described in the embodiment, the present invention can be applied to a P-channel MOSFET. In the case of a P-channel MOSFET, the central portion of the channel region becomes the N ^- channel region, and is 0.3 μm to 0.2 μm.
N ⁺ channel region of 6μm width are formed on the respective end portions, for example, N ^- Vt of the channel region is -0.5V
, Vt in the N ⁺ channel region is −0.6 V to −0.6 V.
Set to 0.9V. That is, Vt is set to 0.1 V or more in absolute value.
Increase by 0.4V.

In a CMOS structure in which an N-channel MOSFET and a P-channel MOSFET are provided on the same substrate, for example, in the process of FIG.
An N-type impurity is ion-implanted by forming an opening also at the second position so that a predetermined Vt can be simultaneously obtained for W1 of the N-channel MOSFET and W2 of the P-channel MOSFET. An opening is also formed in the resist pattern 19 at the location of W1 of the P-channel MOSFET, and P-type impurities are ion-implanted, whereby a predetermined Vt can be simultaneously obtained for the W2 of the N-channel MOSFET and the W1 of the P-channel MOSFET. It is also possible to use a method to make it. According to this method, the V1 of both MOSFETs W1 and W2
Since the t control is performed, there is an advantage that the manufacturing process is simplified.

Next, a sense amplifier circuit using a MOSFET according to the present invention will be described with reference to FIG. Capacitors C1 and C2 are connected between data lines D and DB and ground, respectively. The gate of MOSFET Q1 and the drain of MOSFET Q2 are connected to data line DB, and the gate of MOSFET Q2 and MOSFET Q1
Is connected to the data line D, and both MOSFETs
By connecting the source of T to the source voltage line (precharge voltage line) VS in common, the MOS formed in the element region partitioned by the trench element isolation region
The FET Q1 and the MOSFET Q2 constitute a flip-flop.

In such an amplifier circuit, MOSF
When the ETQ1 and the MOSFET Q2 are formed by the conventional technique as shown in FIGS.
The difference ΔVt between Vt of OSFET Q2 becomes several hundred mV, which may cause a case where a normal sensing operation becomes impossible.

However, the MOSFETs Q1, Q in the circuit of FIG.
2 is a channel region 10 as shown in FIGS.
Of the MOSFET Q1 is not affected by crystal defects in the vicinity of the trench element isolation region since the central portion of the MOSFET is a low Vt P ⁻ channel region 11 which is a main portion and both end portions are a high Vt P ⁺ channel region 12. And MOSFE
The difference ΔVt between Vt of TQ2 can be several mV to 30 mV, and a normal sense operation is guaranteed.

[0051]

As described above, according to the present invention, Vt at both ends of the channel region is made higher than Vt at the main central portion so as not to be affected by crystal defects near the trench isolation region. Therefore, it is possible to suppress the variation of Vt of the entire MOSFET and reduce the Vt difference between the plurality of MOSFETs. This gives two M
Normal operation of the amplifier circuit using OSFETs as a pair is always possible.

Since the ring gate structure is not used, the degree of integration can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a MOSFET according to an embodiment of the present invention, FIG. 1 (A) is a plan view, and FIG. 1 (B) is a cross-sectional view taken along the line AA in FIG. 1 (A).

2A and 2B are diagrams showing a MOSFET according to an embodiment of the present invention, FIG. 2A is a cross-sectional view taken along a line BB in FIG. 1A, and FIG. ()) Is a sectional view of the C-C part.

FIG. 3 is a cross-sectional view showing a manufacturing method according to the embodiment of the present invention in the order of steps.

FIG. 4 is a view showing a step subsequent to that of FIG. 3, and FIG.
FIG. 4B is a plan view, and FIG. 4B is a cross-sectional view taken along a line AA in FIG.

FIG. 5 is a view showing a step that follows the step of FIG. 4, and FIG.
5A is a plan view, and FIG. 5B is a cross-sectional view taken along the line AA in FIG.

FIG. 6 is a circuit diagram illustrating an amplifier circuit according to an embodiment of the present invention.

FIG. 7 is a plan view showing a conventional MOSFET.

8 is a cross-sectional view of each step of manufacturing a conventional MOSFET, and shows an AA section in FIG. 7;

FIG. 9 is a diagram showing a gate voltage-drain current characteristic of a MOSFET.

FIG. 10 is a plan view showing another conventional MOSFET.

[Description of Signs] 1 P-type silicon substrate 2 Trench element isolation region 3 P ⁺ channel stopper region 4 Gate oxide film 6 Side oxide film 5 Gate electrode 7, 8 N ⁺ Source / drain region 10 Channel region 11 P ^- channel region 12 P ⁺ channel region 15 Silicon nitride film pattern 16 Trench (groove) 17 Silicon oxide film 18, 19 Photoresist pattern 18A, 19A Opening of photoresist pattern 20 Ring channel region 25 Ring gate electrode 27, 28 N ⁺ source , the width W1 P drain region a crystal defect locations W channel region ^- the width W2 P ⁺ channel region D of the channel region, DB data lines C1, C2 capacitor Q1, Q2 MOSFET VS source voltage line

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yoshihiro Takagi 1-403, Kosugi-cho, Nakahara-ku, Kawasaki-shi, Kanagawa 53 F-term in NEC Ic Microcomputer System Co., Ltd. 5F032 AA34 AA44 AA49 AC01 CA17 CA20 DA02 DA23 DA24 DA33 DA43 DA78 5F040 DA00 DA06 DB01 DB03 DC01 EC07 EE05 EK02 EK05 FA05 5F048 AA01 AA07 AA09 AB10 AC01 AC03 BA01 BB05 BB14 BG14 BH07 DA25

Claims (10)

[Claims] 1. A semiconductor integrated circuit device provided with an insulated gate field effect transistor provided in an element region of a semiconductor substrate partitioned by a trench element isolation region,
The threshold voltage of the channel region of the transistor is:
A semiconductor integrated circuit device, wherein an end portion located near a boundary with the trench element isolation region is higher than a central portion separated from the trench element isolation region. 2. The semiconductor integrated circuit device according to claim 1, wherein the threshold voltages at the end portions and the central portion are controlled by the configuration of impurities in the portions. 3. An element having the same conductivity type as that of the semiconductor substrate is ion-implanted into the end portion, and an element having a conductivity type opposite to that of the semiconductor substrate is ion-implanted into the central portion. 3. The semiconductor integrated circuit device according to claim 1, wherein: 4. The semiconductor integrated circuit device according to claim 1, wherein two insulated gate field effect transistors are paired to form an amplifier circuit. 5. The insulated gate field effect transistor is of an N-channel type, wherein a threshold voltage at the end portion is more positive than a threshold voltage at the central portion. The semiconductor integrated circuit device according to claim 1. 6. The insulated gate field effect transistor is of a P-channel type, and the threshold voltage at the end portion is more negatively increased than the threshold voltage at the central portion. The semiconductor integrated circuit device according to claim 1. 7. A step of forming a mask pattern on a surface of a semiconductor substrate of a first conductivity type, a step of forming an element isolation trench in the semiconductor substrate using at least the mask pattern as a mask, and depositing an insulating layer over the whole. Filling the device isolation trenches, flattening the insulating layer by a chemical mechanical polishing method using the mask pattern as an etching stopper, and removing the mask pattern; at least a central portion of the channel region. Ion-implanting a second conductivity type element at low energy, and ion-implanting a first conductivity type element at low energy into an end portion of the channel region while at least masking a central portion of the channel region. A method of manufacturing a semiconductor integrated circuit, comprising: forming an insulated gate field effect transistor. 8. The method according to claim 1, further comprising, after the step of removing the mask pattern, a step of ion-implanting a first conductivity type element with high energy to form a channel stopper region inside the semiconductor substrate. A method for manufacturing a semiconductor integrated circuit according to claim 7. 9. The method according to claim 1, wherein the first conductivity type is P-type, and the second conductivity type is P-type.
9. The method according to claim 7, wherein the conductivity type is N-type. 10. The method according to claim 7, wherein the first conductivity type is N-type, and the second conductivity type is P-type.