JP2601664B2 - Insulated gate field effect semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect semiconductor device, and more particularly to a P-channel MOSFET provided in an N-type well.

B. 2. Description of the Related Art Conventionally, as a CMOS device, a device 2 having a large channel width and a bent gate electrode 1 as shown in FIGS. 4 and 5 is known. This device 2
Has a P ⁺ -type source region 3 commonly formed inside a gate electrode 1 and a pair of P ⁺ -type drain regions 4 and 5 formed on both sides, respectively. Is obtained. In order to connect the two left and right P-channel MOSFETs 2a and 2b in parallel,
Each of the P ⁺ -type regions 3, 4, and 5 is formed by diffusion in an N-type well (tank) 7 formed by diffusion in a P-type semiconductor substrate 6. In the figure, reference numeral 8 denotes N which holds the well 7 at the voltage _VDD.
^{It is a +} type guard ring. Reference numeral 9 denotes a gate insulating film. The substrate 6 is provided with an N ⁺ -type source region 15, drain regions 16 and 17, which constitute the N-channel MOSFETs 2c and 2d, and a gate electrode 19 on the gate insulating film 18, respectively. 2b, the gate 19 may have a bent pattern, and the source region 15 may be common. An insulating film having a LOCOS structure for element isolation is provided on the substrate surface, but is not shown.

P-channel type with gate structure bent as described above
In the MOSFETs 2a and 2b, when the N-type well 7 becomes shallower due to miniaturization, increasing the power supply voltage may cause a large current a to flow to the P-type substrate 6 as shown in FIG. 6 ( Here, the current value is normalized by the unit width of the transistor.) This raises the substrate particularly in a CMOS device using a substrate bias, which is one cause of latch-up.

That is, as shown in FIG.
When the depletion layer 10 extending to the junction 35 between the P-type substrate 6 and the depletion layers 11 and 12 extending immediately below the drain regions 4 and 5 comes into contact with each other, the area immediately below the source region 3 is electrically floating, and the operation is performed. Hot electrons (e) generated by the strong electric field effect at the time lower the potential immediately below the source region, and as a result, a forward bias state is established between the source region 3 and the well 7. Therefore, the source region 3-well 7-
Parasitic vertical PNP bipolar transistor 1 between substrates 6
3 turns on and holes 14 are injected into the substrate 6. As a result, the substrate potential rises, which triggers N ⁺
Thyristor structure that exists laterally between the drain region 17-P type substrate 6-N well 7-P ⁺ type drain region 4
20 turns on, causing device malfunction.

As a countermeasure to prevent such a latch-up phenomenon, the guard ring 8 as described above is conceivable. However, even with this, the floating state of the N well 7 immediately below the source region 3 → floating of the substrate 6 cannot be prevented. It is impossible to eliminate latch-up.

C. An object of the present invention is to provide an insulated gate field effect semiconductor device in which latch-up is effectively prevented and reliability is improved.

D. In other words, the present invention provides a semiconductor substrate of a first conductivity type to which a substrate potential is applied, a semiconductor region of a second conductivity type formed on one main surface of the semiconductor substrate, A first conductivity type source region formed on a surface; first and second conductivity type first and second drain regions formed on one main surface of the semiconductor region; the source region and the first drain region A first gate electrode formed on the semiconductor region between the source region and the second drain region via an insulating film; and a first gate electrode formed on the semiconductor region between the source region and the second drain region via the insulating film. A second gate electrode electrically connected to the first gate electrode, and a second conductivity type island region formed in the source region from the surface thereof to the semiconductor region. The source region and the island region Refers to an insulated gate field effect semiconductor device connected to a power supply voltage potential or a ground potential.

E. Examples Hereinafter, examples of the present invention will be described. However, parts common to the examples of FIGS. 4 and 5 described above are denoted by the same reference numerals,
The description may be omitted.

In the example shown in FIGS. 1 and 2, a plurality of N ⁺ -type semiconductor regions 30 are formed in the common P ⁺ -type source region 3 of the P-channel MOSFETs 2a and 2b provided in the N-type well 7 in an island shape. In this example, four regions 30 are formed, and each of these regions 30 is in contact with the lower N-type well 7. The two regions 30 and 3 are joined to each other by a silicide layer 31 generated by silicidation of a metal (eg, Ti) deposited in a predetermined pattern, or fixed to a power supply voltage (V _DD ) by a contact not shown. Is done. In FIG. 1, the source electrode 32 and the drain electrode 33 are shown by imaginary lines, but the contacts are not shown. As shown in FIG. 2, a substrate potential VBB is applied to the substrate 6, and the drain regions 4, 5 are connected to the ground potential VSS.

As described above, in order to form the N ⁺ -type region 30 in the source region 3, an N-type impurity is diffused therein after the source region 3 is formed first (in this case, the impurity concentration is offset by the P-type impurity). In the case where the source region 3 is diffused,
Diffuse remove the portion of the N ⁺ -type region 30, and it is desirable to form the N ⁺ -type region 30 by diffusing N-type impurity in this pulled region. These diffusion steps can be performed simultaneously with other regions. The impurity concentration of the N ⁺ type region 30 may be 10 ¹⁹ to 10 ²⁰ / cm ³ . The width of the above N ⁺ type region 30 is
The length l ₁ and the length l ₂ may be about 1 μm, the pitch P may be about 10 μm, the length l ₃ of the source region 3 may be about 2.4 μm, and the gate length (channel length) l ₄ may be about 1 μm.

With the above configuration, since the N ⁺ type region 30 is in contact with the N type well 7 immediately below the source region 3, the P-channel MOSFET
Hot elktrons (e) generated when 2a and 2b operate can be absorbed into the N ⁺ -type region 30 as shown by arrows. That is, the barrier to electrons is eliminated by the N ⁺ type region 30, and electrons easily enter here and are absorbed by the power supply. As a result, it is possible to prevent the local potential drop directly below the source region as described above (FIG. 5), and it is possible to prevent the vertical PNP parasitic bipolar transistor 13 from being turned on by forward biasing.

Therefore, holes are not injected into the P-type substrate 6, and the above-described CM having a high latch-up resistance, in which latch-up is unlikely to occur.
OS device can be realized. Specifically, when a 1 Mbit DRAM was operated with an internal cycle of 210 nsec, the power supply voltage was only up to 8.0 V due to a rise in the substrate potential in a normal device without the N ⁺ type region 30. When the N ⁺ type region 30 is provided as shown in FIG.
It works up to 9.0V.

The above effect according to the present embodiment is particularly remarkable when the impurity concentration of the N-type well 7 is as thin as 10 ¹⁷ / cm ³ or less and the thickness is as small as 2 μm or less (that is, when the depletion layer is easily extended). is there.

FIG. 3 illustrates a CMOS device 22 according to another example of the present invention.

This example is the same as the example of FIG. 1 except that the N ⁺ type region 30 in the source region 3 is formed in a longitudinal pattern.
Even in this case, there is an effect of absorbing hot electrons by the N ⁺ type region 30, and latch-up can be effectively prevented. Moreover, since the region 30 is longitudinal, the hot electron absorption area is increased.

Although the present invention has been described above, the above-described example can be further modified based on the technical idea of the present invention.

For example, the pattern, size, depth, and the like of the above-described N ⁺ -type region 30 may be variously changed, and the respective diffusion regions and gate electrode shapes are not limited to those described above. Further, the conductivity type of each of the above-described semiconductor regions may be changed to an opposite type (that is, a structure in which an N-channel MOSFET is provided in a P-well). Further, the present invention can be widely applied to devices other than the above-mentioned CMOS.

F. Advantageous Effects of the Invention As described above, in the present invention, the semiconductor region of the opposite conductivity type is provided in the common source region in an island shape so as to be in contact with the lower layer (well layer). Absorption can be prevented, thereby preventing a potential change immediately below the source region, preventing carrier injection into the substrate that causes latch-up, and improving reliability.

[Brief description of the drawings]

1 to 3 show an embodiment of the present invention. FIG. 1 is a plan view of a main part of a CMOS device, and FIG. 2 is a CMOS FIG. 1-II including an N-channel MOSFET.
FIG. 3 is an enlarged sectional view corresponding to a line, and FIG. 3 is a plan view of a principal part of another CMOS device. 4 to 6 show a conventional example, FIG. 4 is a plan view of a main part of a CMOS device, and FIG. 5 is an enlarged view corresponding to a line VV in FIG. 4 including an N-channel MOSFET. FIG. 6 is a voltage-current characteristic curve diagram. In the reference numerals shown in the drawings, 1, 19 ... gate electrodes 2a, 2b ... P-channel MOSFETs 2c, 2d ... N-channel MOSFETs 3, 15 ... source regions 4, 5, 16, 17 ... drain regions 6 ... Substrate 7 N-well 8 Guard ring 10, 11, 12 Depletion layer 22 CMOS device 30 N ⁺ type semiconductor region.

Claims (1)

(57) [Claims] A first conductive type semiconductor substrate to which a substrate potential is applied; a second conductive type semiconductor region formed on one main surface of the semiconductor substrate; and a first conductive type semiconductor region formed on one main surface of the semiconductor region. A first conductivity type source region, and a first conductivity type first region formed on one main surface of the semiconductor region.
And a second drain region; a first gate electrode formed on the semiconductor region between the source region and the first drain region with an insulating film interposed therebetween; A second gate electrode formed between the drain region and the semiconductor region via an insulating film, and electrically connected to the first gate electrode; An insulated gate field effect semiconductor device having a second conductivity type island region formed so as to reach a region, wherein the source region and the island region are connected to a power supply voltage potential or a ground potential.