JPS62211945A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the generation of a trigger current which is the cause of a latch-up phenomenon by a method wherein, in a complementary metal oxide semiconductor (CMOS) type erasable and programmable ROM, a capacitor is constituted between source electrodes. CONSTITUTION:When a memory transistor, consisting of a source and drain region, a channel region 10, a gate 8a and the like, is going to be formed on a P-well 2, a capacitor is formed between source electrodes simultaneously with the formation of the floating gate 8a and a control gate. To be more precise, polysilicon layers 8b and 9b, to be used for a capacitor electrode, are formed between the VDD electrode 11, which will be turned to a source terminal, and a VSS electrode 3 and they are connected to the electrodes 3 and 11. When external noise voltage is applied to a power source terminal, it can be absorbed with the above-mentioned capacitor by providing a capacitor between two power source terminals 3 and 11. As a result, the generation of a trigger current which is the cause of occurrence of a latch-up phenomenon can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to improving the latch-up resistance of semiconductor devices, particularly CMOS type semiconductor devices.

[Conventional technology]

Figure 2a shows, for example, a reprint of the journal of the Institute of Electronics and Communication Engineers
es, ICES' 78/2 Vol 61-CN
n2) “Analysis of launch-up phenomenon of 0MO8IC”
FIG. 2 is a cross-sectional view showing the CMOS type semiconductor device shown in FIG.

In FIG. 2a, reference numeral 1 denotes a substrate of a CMOS type semiconductor device, which is N conductivity type silicon with a low impurity concentration (hereinafter referred to as N−
8i board), and 2 is this N”-
A P conductivity type well (hereinafter referred to as P-well) with a low impurity concentration was formed in a region of the 8t substrate 1, the N diffusion layer 14 was used as the source, the N diffusion layer 15 was used as the drain, and the polysilico layer 16 was used as the gate. An N-type MO3 transistor is formed, and the LP diffusion layer 17 is used as a source on the surface of the N-8i substrate 1.
A P-type MO8 transistor is formed with the P diffusion layer 18 as the drain and the polysilicon 19 as the gate. And gates 16 and 19 of each MOS transistor
are connected by metal wiring, and 20 is its input terminal. In addition, each drain is an N diffusion layer 15, P″
- The diffusion layer 18 is also connected in the same way and becomes the output terminal 21, and the two transistors form a CMOS inverter.

Here, the P diffusion layer 22 has the function of stabilizing the potential of the P-well 2, and similarly, the N diffusion layer 23 has the function of stabilizing the potential of the N-8t substrate 1. Note that 3.11 is a Vss metal electrode wiring and a VDD metal electrode wiring, respectively, and will hereinafter be referred to as a VSS electrode t and a VDD electrode. The CMOS inverter is, as shown in numerals 24 and 26 in FIG. 2a,
Horizontal PN with the source 17 and drain 18 diffusion layers of the P-type MO8 transistor as the emitter, the N''-8i substrate 1 as the base, and the P-well 2 diffusion layer as the collector.
In addition, as indicated by reference numerals 25 and 27 in the figure, the diffusion layers of the source 14 and drain 15 of the N-type MO8 transistor are connected to the emitter and P- transistor, respectively.
A vertical NPN transistor is formed with the well layer 2 as the base and the N-8i substrate 1 as the collector. The base resistors that bias the bases of these parasitic transistors 24,25 are shown at 28,29.

The resistances between the diffusion layer 23 connected to the VDD electrode 11 and the base N-8i substrate 1, and the resistance between the diffusion layer 22 connected to the VBs electrode 3 and the P-well layer 2 serving as the base are extremely large. It is considered to have low resistance.

In addition, the emitter resistance 30 of the parasitic transistor 24°25
．． 31 are the sources 17.14 of the P and N type MO8 transistors, the vDD electrode 11, and the Vss electrode 3, respectively.
It is thought that the low resistance created during 32 is the above horizontal type P
This is the effective pace length of the NP transistor. In addition, the second
Figure b is a basic equivalent circuit of Figure 2a, focusing on parasitic transistors.

Next, the operation will be explained. In Figure 2a, vDD
When a sufficiently large positive external noise voltage is applied to the electrode 11, a current flows from the vno electrode 11 through the base resistor 28 of the PNP transistor 24, and the PNp transistor 24 becomes conductive. And this transistor 2
Q NPN transistor 25 with collector current of 4
The base of the PNP transistor 24 is biased, the NPN transistor 25 is not conductive, and current flows to the base of the PNP transistor 24, so that positive feedback is applied between the transistors 24 and 25, and even if the trigger current due to external noise disappears, the power supply terminal remains VD electrode 11 and VSS electrode 3 as
A current flows steadily between them, causing a latch-up phenomenon. The conditions for launch-up to occur in this way include (1) the point at which external noise enters the parasitic transistor, (II) the point at which the parasitic thyristor turns on, and (iii) the point at which the turned-on state is maintained. 9. If the effective base length 32 of the lateral PNP transistor is increased, 9. A method was used to make it difficult to turn on the parasitic thyristor by reducing the current amplification factor hFE of the PNP transistor.

[Problem that the invention seeks to solve]

However, since the conventional CMOS type semiconductor device is configured as described above, the parasitic PNP transistor's HP
It has been difficult to create a fine pattern layout because the attempt has been made to reduce E-P and Nm by increasing the distance between the MOS transistors, thereby preventing the thyristor from turning on and preventing double-up.

This invention was made to solve the above-mentioned problems, and allows for a fine pattern layout, a high degree of integration, and a CMOS with high latch-up resistance.
The purpose is to obtain a type semiconductor device.

[Means for solving problems]

In the CMOS type semiconductor device according to the present invention, a capacitive element is provided by sandwiching an insulating layer between one polysilicon or metal silicide and another polysilicon or metal silicide connected between the vDD electrode and the V8S electrode as power supply terminals. The capacitive element is arranged in an active region of the semiconductor device, a portion where polysilicon or metal silicide serving as an electrode of the capacitive element and a diffusion layer are not present.

[Effect]

In the semiconductor device of the present invention, even when an external noise voltage is applied, the capacitive element between the Vnl) electrode and the VssN electrode absorbs the external noise voltage, thereby generating a trigger current that is a cause of latch-up. This makes it possible to prevent

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
& Figure 1b is a layout diagram of an icMO8 type EPROM, and Figure 1b is a cross-sectional view taken along line AB in Figure 1a. In this embodiment, a P-well 2 region is provided on an N-8i substrate 1, an N diffusion layer 5 connected to a metal wiring, which is a VSS electrode 3, through a contact hole 4a is on the source side, and a metal wiring, which is a bit line 6, is on the source side. The N diffusion layer 7, which is reversely connected to the wiring through the contact hole 4b, is on the drain side, and the first polysilicon 8I
Form a 70-ting gate with L. Furthermore, a control gate is formed using the second polysilicon 9a, and when configuring a memory transistor having a channel forming region 10 serving as a source and a drain on the P-well 2 where both gates overlap, the floating gate 8a, the control gate In each step of forming 9a, a pair of polysilicon layers 8b and 9 are formed as electrodes on which a capacitive element is to be formed.
The contact holes 4c and 4a of these polysilicon layers 8b and 9b are electrically connected to the VDD electrode 11 and the metal wiring that is the Vss electrode 3, respectively. Note that 12 is a metal wiring for an in-circuit signal line, and 13 is an interlayer insulating layer, and in FIG. 5, the same reference numerals indicate the same or corresponding parts.

Next, the operation of the configuration of the above embodiment will be explained.

The EPROM has a memory transistor structure with a floating gate 8a and a control gate 9ae, stores information using an avalanche breakdown phenomenon, and usually uses polysilicon as the material for these two gates. However, FIGS. 1a and 1b
In the figure, by using the two types of gate manufacturing processes for the memory transistor described above to form polysilicon layers 8b and 9b't, which become the electrodes of the capacitive element between the vDD electrode 11 and the vss electrode 3, the conventional manufacturing process A capacitive element can be formed without increasing the capacity. Therefore, by configuring this capacitive element between the VDD electrode 11, which is the power supply terminal, and the VSS electrode 3, even if an external noise voltage is applied to the power supply terminal, it can be absorbed by the capacitive element, and the latch amplifier It is possible to prevent the generation of trigger direct current, which is the cause of generation, and to obtain a CMOS type semiconductor device in which latch-up is less likely to occur.

In the above embodiment, the two types of gate materials of the CMOS type EPROM are polysilicon, but other gate materials such as doped polysilicon and metal silicide may be used. Furthermore, the above capacitive element can be formed not only in EPROMs but also in semiconductor devices using multilayer polysilicon or metal silicide as gate materials and peripheral circuit wiring materials, and the substrate and well structure can be changed to P-substrate, N-well, N-well, etc., respectively. Alternatively, even when an N-substrate and a P-well are used, the same effects as in the above embodiment can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to form a capacitive element with a laminated structure in a location where a conventional active region, capacitive electrode material, or diffusion layer does not exist, and special process sound lessons can be added to the conventional manufacturing process. The launch-up resistance of a CMOS type semiconductor device can be improved without any change, and a fine pattern layout can be performed. This has excellent effects such as higher integration and lower cost of the device.

[Brief explanation of drawings]

FIG. 1a is a schematic top view showing the layout of a CMOS type semiconductor device according to an embodiment of the present invention, FIG. 1b is a cross-sectional view taken along the line A-B, and FIG. FIG. 2b, which is a schematic cross-sectional view of the CMOS inverter, is a basic equivalent circuit diagram of the parasitic transistor in the same figure. 1...7y-si substrate, 2...P-well, 3
...vss gold end gold type electrode wiring VSS electrode), 4a. 4b, 4c, 4d... contact hole, 5.
...N+ diffusion layer, 6...Bit line (metal wiring), 7...N diffusion layer, 8&... Floating gate of memory transistor, 8b...Polysilicon for capacitive element electrode Layer 9a...Control gate of memory transistor, 9b...Polysilicon layer for capacitive element electrode, 10...Channel formation region, 1
1...Fist/VDD metal electrode wiring (VDD electrode), 12.
...Metal wiring for signal lines in the circuit, 13...Interlayer insulating layer.

Claims (1)

[Claims] In a CMOS type semiconductor device, a diffusion layer of an opposite conductivity type is formed in a semiconductor substrate of one conductivity type, and MOS transistors with different conduction channels are formed in substrate regions of both conductivity types. A first conductor made of polysilicon or metal silicide and a second conductor made of polysilicon or metal silicide are connected to the metal wiring, and an element with a laminated structure having an insulating layer between these conductors is used in the semiconductor device described above. 1. A semiconductor device characterized in that an active region, both conductors, and a diffusion layer are arranged at a possible location where no diffusion layer is present.