JPS627160A - Semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate wirings by forming a bipolar switching element outside a semiconductor substrate, and an FET at the portion inside surrounded by the element, and adjacently disposing the second layer of a switching element of the same conductive type and the drain of the FET. CONSTITUTION:A source electrode 5 on a semiconductor substrate 1 secured onto a metal substrate 20 is connected through a conductor 71 formed with an S terminal secured through an insulating plate 26 on the substrate 10 and aluminum wirings 28. Similarly, a base electrode 8 is connected with a conductor 72 formed with a B terminal, and a gate electrode 7 is connected with a conductor 73 formed with a G terminal by leads 28. A Zener diode 23 connected between the base of a bipolar transistor 21 and the source of an FET 22 is secured on an S terminal conductor 71 as an external chip, and connected by the conductor 72 and the leads 28. Thus, the region 3 and the drain 4 of the FET are adjacently connected while omitting wirings, and an inductance which becomes a cause of generating a high voltage is not generated at switching time.

Description

[Detailed description of the invention] [Technical field to which the invention pertains]

The present invention relates to a semiconductor device in which a bipolar switching element such as a bipolar transistor or a gate turn-off thyristor and a field effect transistor connected in series thereto are integrated in the same semiconductor substrate.

[Prior art and its problems]

When configuring a circuit in which the emitter of a bipolar transistor 21 and the drain of a field effect transistor (FET) 22 are connected in series as shown in FIG. 2, each individual semiconductor element is placed on a metal substrate 20 as shown in FIG. semiconductor chips are mounted directly or via an insulating plate 26, and the electrodes of each semiconductor chip and the conductor 27 on the m-edge plate are connected by a conducting wire 28 such as an aluminum wire. In Figure 3,
Semiconductor chips corresponding to the elements in FIG. 2 are given the same reference numerals as the elements in FIG. Such a structure had two drawbacks. One is that the number of parts is large and the assembly structure is complicated, and the other is that the switching speed of FET 22 is fast, so the connection wire 28, especially the connecting wire between the emitter of transistor 21 and the drain of FET 22, causes Because of the inductance, the withstand voltage of the FET cannot be lowered, and the operating resistance of the FET increases, resulting in an increase in on-loss. In order to lower the breakdown voltage of the FET, use a Zener diode 24 as shown in the figure. An overvoltage absorbing device such as a CR circuit 25 is required. Therefore, bipolar transistor 21 and F
It is desirable to integrate E722'' into the same semiconductor substrate to eliminate the need for connection using conductive wires.The same applies when using a gate turn-off circuit as a switching element.

[Purpose of the invention]

In response to this demand, the present invention integrates FETs and bipolar switching elements on the same substrate, making it possible to reduce the number of parts in assembly, eliminate the need for connections by bonding conductive wires, and omit overvoltage absorbing devices for FETs. Alternatively, the purpose is to make it possible to downsize the FET and lower the withstand voltage of the FET.

[Key points of the invention]

A semiconductor device according to the present invention includes a surface region of a second conductivity type provided on a semiconductor substrate of a first conductivity type, a region provided within the region of the second conductivity type, the region being a second layer, and an original region of the substrate being a second layer. An annular first conductivity type surface region forming the first layer of the three-layer bipolar switching element; an annular first conductivity type surface region adjacent to the inside of the annular region and shallower than that region; An annular first conductivity type surface region that is provided inside the conductivity type region and forms the source of the PET with that region as the drain, and two annular first conductivity type surface regions that form the source and the drain. The above object is achieved by providing a gate electrode provided on the surface between the regions via an oxide film.

[Embodiments of the invention]

FIG. 1(a) and (bl are modeled representations of an example of the semiconductor device according to the present invention, and t) is (X-X of al
FIG. A P-type region 2 is formed in an N-type semiconductor substrate 1 by impurity diffusion. This P type region 2 may be an epitaxially grown layer on an N type semiconductor substrate.
An annular N-type region 3 is formed within the P-required region 2 . N-type substrate 1. P-type region 2. The N-type region 3 forms an NPN transistor 21. A FET 22 is formed in a region surrounded by this NPN transistor 21. That is, two concentric annular N-type regions 4.5 having a depth W which is significantly shallower than the depth Wm of the N-type emitter region 3 are provided with an interval between them, and the outer annular region 4 is N! E! ! [Adjacent to the inside of area 3. An annular gate electrode 7 made of polycrystalline silicon or the like is placed through an oxide film 6 on the surface of this shallow annular N-type region 4.5, which is formed by ion implantation or the like. There is. A gate terminal G is connected to this gate electrode 7, a base terminal B is connected to an aluminum electrode 8 that contacts the P-type region 2 outside the N-type region 3, and a source terminal S is connected to the aluminum electrode 9 that contacts the N-type region 5. A collector terminal is connected to the N4 layer 10 formed on the lower surface side of the substrate 1 via an electrode (not shown). FIG. 4 shows a concrete embodiment of the present invention in a plan view, and parts common to those in FIGS. 1 to 3 are given the same reference numerals. A source electrode 5 on a semiconductor substrate 1 having a structure similar to that shown in FIG. Connected by aluminum 1j128. Similarly, the base electrode 8 is the conductor 7 forming the B terminal.
2 and the gate electrode 7 are connected to a conductor 73 forming a C terminal by a conducting wire 28, respectively. The Zener diode 23 connected between the base of the bipolar transistor 21 and the source of the FET 22 is externally fixed as a chip on the S terminal conductor 71, and connected to the S terminal conductor 72 and the conductor &I 28.
connected by. The C terminal is connected to the board 20. As a result, the circuit included within the chain line in Figure 2 is connected to the board 2.
It is constructed integrally on G. In this case, the N-type region 3, which becomes the emitter of the bipolar transistor, and the drain 4 of the FET are adjacent to each other, as shown in Figure 1), and wiring for connection is omitted, and high voltage is generated when the switch is turned off. Since no inductance is generated, the overvoltage absorbers 24 and 25 are unnecessary. Although the above embodiment describes a semiconductor device consisting of an NPN transistor and an N-channel FET using an N-type semiconductor substrate, the present invention can be similarly implemented with a combination of a PNP transistor and a P-channel FET. The present invention can also be implemented by adding a P layer to the lower surface of the substrate shown in FIG. 1 and forming a gate turn-off thyristor using the base electrode 8 as the gate electrode.

【Effect of the invention】

In the present invention, a bipolar switching element is formed on the outside of a semiconductor substrate, an FET is formed on the inside surrounded by the bipolar switching element, the second layer of the switching element of the same conductivity type and the drain of the FET are made adjacent to each other, and the wiring between them is formed. Since this eliminates the need for overvoltage during switching, it is possible to reduce operating resistance by lowering the withstand voltage of the FET or
It is possible to omit or downsize the overvoltage absorption gjtt for T protection. Moreover, the integration of bipolar switching elements and FETs can of course reduce the number of man-hours required for assembling one assembly, which is extremely effective.

[Brief explanation of drawings]

FIG. 1 shows a modeled example of a semiconductor device according to the present invention, +al is a plan view, (b) is a sectional view taken along the line X-X@, and FIG. 2 is a circuit showing an example of a circuit integrated according to the present invention. 3 shows a conventional device configuring the circuit in FIG. 2, (1) is a plan view, (6) is a side view, and FIG. 4 is a book configuring the circuit within the chain line in FIG. 2. FIG. 1 is a plan view of a device using a semiconductor device according to an embodiment of the invention. 1; Semiconductor substrate, 2: P required region, 3 = Engineering ivy, 4 Nidrain, 5: Source, 6: Oxide film, 7: Gate electrode,
8: base electrode, 9: source electrode, 21: NPN) transistor, 22: FET.

Claims (1)

[Claims] 1) A surface region of a second conductivity type provided on a semiconductor substrate of a first conductivity type, and a bipolar switching element provided within the region, with the region as a second layer and the original region of the semiconductor substrate as a third layer. an annular first conductivity type surface region forming a first layer; an annular first conductivity type surface region adjacent to the inside of the annular region and shallower than the region; a gate electrode provided via an oxide film on an annular first conductivity type surface region forming a source of a field effect transistor to be used as a drain, and on a surface between the two first conductivity type regions forming a source and a drain; A semiconductor device characterized by comprising: