JP2901275B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a structure of a bonding pad of a semiconductor integrated circuit device having a terminal voltage higher than a power supply voltage.

[Conventional technology]

Conventionally, this type of semiconductor integrated circuit device is characterized in that a P-type substrate is set at the lowest voltage and is insulated and separated by a PN junction. Normally, the terminal voltage is used within the range of the power supply voltage. However, depending on the environmental conditions of the device using the present semiconductor integrated circuit device, a voltage higher than the power supply voltage may be applied to each terminal. In such a case, in order to prevent the semiconductor integrated circuit device from malfunctioning due to destruction and parasitic effects, a protection diode is inserted between the terminal and the terminal having the highest potential (power supply voltage) to protect elements connected to the terminal. I was

FIG. 3 shows a cross-sectional structure of a semiconductor chip including the protection diode. Reference numeral 1 denotes an aluminum electrode for a bonding pad, 2 denotes an insulating film, and an N-type epitaxial layer 4 formed on a P-type substrate 6. Is insulated and separated by the P ⁺ -type isolation region 3, and the N-type epitaxial layer 4 is biased by the power supply voltage via the power supply voltage aluminum electrode 8 and the N ⁺ high-concentration diffusion region 7. A P-type diffusion region 9 is formed in the N-type epitaxial layer 4, and one end thereof is connected to the bonding pad aluminum electrode 1 to form a diode having the P-type diffusion region 9 as an anode and the N-type epitaxial layer 4 as a cathode. When the terminal voltage input to the aluminum electrode for the bonding pad is higher than the power supply voltage, the current flowing into the terminal is supplied to the power supply terminal side to protect the elements connected to the terminal from malfunctions such as destruction and parasitics. I was

[Problems to be solved by the invention]

In the above-described conventional semiconductor integrated circuit device, when the terminal voltage exceeds the power supply voltage, the protection diode formed by the P-type diffusion region 9 and the N-type epitaxial layer 4 conducts. The potential becomes 0.7V higher. At this time, if the anode side of the protection diode, that is, the terminal side and the P-type diffusion region in the other N-type epitaxial layer are electrically connected by the aluminum wiring, the P-type diffusion region also has the same potential as the terminal. Become. In particular, as shown in FIG. 3, in the same N-type epitaxial layer 4, a P-type diffusion region 9, an N ⁺ -type diffusion region 7, a P-type diffusion region 13, and an N ⁺ -type diffusion region 14 electrically connected to terminals. When the NPN type transistor composed of the NPN type transistors is included at the same time, the P type diffusion region is higher than the potential of the N type epitaxial layer. A parasitic PNP having the collector as a collector is generated, and this parasitic PNP is connected to the NPN transistor as shown in FIG. 4 to form a thyristor structure, which may cause an inconvenient operation in circuit operation.

Therefore, in order to prevent an undesired operation due to the occurrence of the parasitic transistor described above, the P terminal electrically connected to the terminal is
There is a method of isolating and isolating the type diffusion region 9 independently and biasing the N type epitaxial region with a power supply voltage. However, this measure has a disadvantage that when there are a plurality of P-type diffusion regions connected to the terminals, only those elements need to be insulated and separated, and the chip area of the semiconductor integrated circuit increases. In order to prevent malfunctions such as destruction and parasitic effects, there is a method in which a P-type diffusion region is provided outside the semiconductor integrated circuit device and an external resistor is used. However, this method increases the number of external components and the number of terminals. However, there is a disadvantage that the chip area is increased due to an increase in the cost and the cost is increased.

An object of the present invention is to provide a semiconductor integrated circuit device that can prevent malfunctions such as destruction and parasitic effects and can reduce the chip size.

[Means for solving the problem]

The semiconductor integrated circuit device of the present invention is an element region partitioned by one conductivity type isolation region selectively provided from the surface of the opposite conductivity type epitaxial layer on the one conductivity type semiconductor substrate to the one conductivity type semiconductor substrate; A diffusion region of one conductivity type serving as a base of a bipolar transistor selectively provided on the surface of the opposite conductivity type epitaxial layer; and an input electrode connected to the one conductivity type diffusion region and formed on the opposite conductivity type epitaxial layer. And a power supply voltage electrode for supplying a power supply voltage to the reverse conductivity type epitaxial layer, the reverse conductivity type epitaxial layer and the input electrode constitute a Schottky barrier diode, and the Schottky barrier diode is It conducts when a voltage higher than the power supply voltage is applied to the input electrode, and clamps the voltage of the input electrode. The features.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a longitudinal sectional view of a chip of a semiconductor integrated circuit device showing one embodiment of the present invention. In this embodiment, each of the P ⁺ -type isolation regions 3 selectively provided from the surface of the epitaxial layer 4 of the chip including the P-type semiconductor substrate 6 made of silicon and the N-type epitaxial layer 4 to the P-type substrate 7. Are formed in the element formation region. The N-type epitaxial layer 4 and the bonding pad electrode 1 are electrically connected. Although not shown in the drawing, a plurality of P-type diffusion regions are formed on the N-type epitaxial layer 4 to form an element. And is connected to the electrode 1. Further, a Schottky barrier diode is formed as a protection diode using the bonding pad electrode 1 as an anode and the N-type epitaxial layer 4 as a cathode, and the N-type epitaxial layer 4 is connected via an N ⁺ -type high concentration diffusion region 7. It has a structure in which a power supply aluminum electrode is biased by the power supply voltage. FIG. 2 is an equivalent circuit diagram.

In the above configuration, when the potential of the bonding pad aluminum electrode becomes higher than the power supply voltage, the Schottky barrier diode conducts, and the current flowing into the terminal becomes N ⁺ high concentration through the Schottky barrier diode serving as a protection diode. It flows into the power supply terminal via the diffusion region and the power supply voltage aluminum electrode. At this time, the forward voltage of the Schottky barrier diode is less than half the forward voltage of the diode formed by the P-type diffusion region and the N-type epitaxial layer.

Therefore, even when the plurality of P-type diffusion regions provided in the N-type epitaxial layer are electrically connected to the bonding pad aluminum electrode, if the bonding pad aluminum electrode 1 rises above the power supply voltage, According to the above description, since the diode formed by the P-type diffusion region and the N-type epitaxial layer does not have a forward potential, the diode is in a cut-off state, and malfunctions due to destruction, parasitic, and the like do not occur.

In the figure, reference numeral 5 denotes an N ⁺ -type high-concentration buried layer selectively provided at and near the interface between the P-type substrate 6 and the N-type epitaxial layer 4, which reduces the operating resistance of the N-type epitaxial layer 4. And not particularly essential according to the invention.

〔The invention's effect〕

As described above, according to the present invention, a protection diode is formed by a Schottky barrier diode with a bonding pad aluminum electrode and an N-type epitaxial layer biased by a power supply voltage. However, even if a plurality of P-type diffusion regions are connected to the bonding pad aluminum electrode for clamping by the forward voltage of the Schottky barrier diode, malfunctions such as destruction and parasitic effects occur. Therefore, there is no need to insulate and separate only these P-type diffusion regions, so that the chip size can be reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor chip showing one embodiment of the present invention, FIG. 2 is an equivalent circuit diagram thereof, FIG. 3 is a sectional view of a semiconductor chip showing an embodiment of the prior art, and FIG. FIG. 3 is an equivalent circuit diagram of a parasitic transistor generated when the bonding pad aluminum electrode rises above a power supply voltage. 1 ... Aluminum electrode for bonding pad, 2 ... Insulating film, 3 ... P ⁺ type isolation region, 4 ... N type epitaxial layer region, 5 ... N ⁺ type high concentration buried layer region, 6 ... P Type semiconductor substrate, 7 N ⁺ type high concentration diffusion region, 8 Aluminum electrode for power supply voltage (collector), 9 P type diffusion region, 10
Other electrodes of the P-type diffusion region, 11: Base electrode, 12: Emitter electrode.

Claims (1)

(57) [Claims] An element region defined by an isolation region selectively provided from the surface of the opposite conductivity type epitaxial layer on the semiconductor substrate to the one conductivity type semiconductor substrate; A first conductivity type diffusion region serving as a base of a bipolar transistor selectively provided on a layer surface; an input electrode connected to the one conductivity type diffusion region and formed on the opposite conductivity type epitaxial layer; A power supply voltage electrode for supplying a power supply voltage to the conductive type epitaxial layer, the reverse conductive type epitaxial layer and the input electrode constitute a Schottky barrier diode, and the Schottky barrier diode is connected to the input electrode. A semiconductive device that conducts when a voltage higher than a power supply voltage is applied and clamps the voltage of the input electrode. Integrated circuit device.