JPS61296770A - Insulated gate field effect type semiconductor device - Google Patents
Insulated gate field effect type semiconductor deviceInfo
- Publication number
- JPS61296770A JPS61296770A JP60138714A JP13871485A JPS61296770A JP S61296770 A JPS61296770 A JP S61296770A JP 60138714 A JP60138714 A JP 60138714A JP 13871485 A JP13871485 A JP 13871485A JP S61296770 A JPS61296770 A JP S61296770A
- Authority
- JP
- Japan
- Prior art keywords
- type
- biased
- semiconductor device
- gate
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 8
- 230000005669 field effect Effects 0.000 title claims description 10
- 230000005611 electricity Effects 0.000 abstract description 2
- 230000003068 static effect Effects 0.000 abstract description 2
- 230000001681 protective effect Effects 0.000 abstract 3
- 239000000758 substrate Substances 0.000 description 10
- 230000015556 catabolic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7808—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Protection Of Static Devices (AREA)
- Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は絶縁ゲート電界効果型半導体装置、特に高出力
電界効果トランジスタのゲート入力静電耐量を向上する
ゲート入力保護の構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an insulated gate field effect semiconductor device, particularly to a gate input protection structure for improving gate input electrostatic withstand capability of a high output field effect transistor.
従来の高出力絶縁ゲート電界効果トランジスタはＮ型基
板にＰ型ベース領域とＮ型ソース領域とを重複して形成
し、Ｎ型基板をソース領域とし、このＮ型基板とＮ型ソ
ース領域間のＰ型ベース領域表面に絶縁膜を介してゲー
ト電極を形成していた。ゲート電極下の絶縁膜を異常高
電圧の入力信号から保護するゲート入力保護回路は第３
図に示すように、Ｎ型基板３にＰ型ベース領域と同時に
形成したＰ型領域】２と、Ｎ型ソース領域と同時に形成
した２つのＮ型領域１３．１３’を形成し、Ｎ型領域１
３を配線１１でゲート電極と入力端子１０とに接続し、
Ｎ型領域１３′をソース電極に接続していた。A conventional high-output insulated gate field effect transistor has a P-type base region and an N-type source region overlappingly formed on an N-type substrate, the N-type substrate serving as a source region, and a region between the N-type substrate and the N-type source region. A gate electrode was formed on the surface of the P-type base region with an insulating film interposed therebetween. The third gate input protection circuit protects the insulating film under the gate electrode from abnormally high voltage input signals.
As shown in the figure, two N-type regions 13 and 13' are formed on an N-type substrate 3, a P-type region 2 formed at the same time as the P-type base region, and two N-type regions 13 and 13' formed at the same time as the N-type source region. 1
3 is connected to the gate electrode and the input terminal 10 by the wiring 11,
The N-type region 13' was connected to the source electrode.
かかる従来のツェナーダイオードを使ったゲート入力保
護回路は、等制約に、通常のゲート入力電圧に対し逆バ
イアスするツェナーダイオードと順バイアスするツェナ
ーダイオードとがＰ型領域１２とＮ型領域１３．１３’
との間に形成され、これら２つのツェナーダイオードが
直列に接続された形になっている。このためこの直列接
続の降伏電圧はツェナーダイオード１つの降伏１圧であ
り、たかだかＩＯＶ程度であった。このため、高電圧高
出力用のゲート入力保護回路としては不十分であった。In such a conventional gate input protection circuit using a Zener diode, a Zener diode that is reverse-biased and a Zener diode that is forward-biased are divided into a P-type region 12 and an N-type region 13.13' under equal constraints.
These two Zener diodes are connected in series. Therefore, the breakdown voltage of this series connection was the breakdown voltage of one Zener diode, which was about IOV at most. For this reason, it was insufficient as a gate input protection circuit for high voltage and high output.
Ｃ問題点を解決するための手段〕
本発明によれば、絶縁ゲート電界効果型半導体装置のゲ
ート入力保護回路として、通常のゲート入力電圧に対し
て逆バイアスされる２つのツェナーダイオードと顆バイ
アスされる１つのツェナーダイオードとの直列接続を用
いている。この逆バイアスされるツェナーダイオードの
１つと順バイアスされるツェナーダイオードとは絶縁ゲ
ート電界効果型半導体装置の電界効果トランジスタとは
別個に形成される基体とは逆導電型の領域とこの逆４１
Ｆ型の領域内に離間して形成される基体と同導電型の２
つの領域とで形成され、残シの逆バイアスされるツェナ
ーダイオードは電界効果トランジスタのソース電極に接
続された基体と逆導電型の領域に形成される。Means for Solving Problem C] According to the present invention, as a gate input protection circuit for an insulated gate field effect semiconductor device, two Zener diodes that are reverse biased with respect to the normal gate input voltage and two Zener diodes that are condyle biased are used. A series connection with one Zener diode is used. One of the reverse biased Zener diodes and the forward biased Zener diode are formed separately from the field effect transistor of the insulated gate field effect semiconductor device.
2 of the same conductivity type as the base formed spaced apart within the F-type region.
The remaining reverse biased Zener diode is formed in a region of opposite conductivity type to the substrate connected to the source electrode of the field effect transistor.
次に、図面を参照して本発明をよシ詳細に説明する。 Next, the present invention will be explained in detail with reference to the drawings.
第１図は本発明の一実施例を説明したもので。FIG. 1 illustrates one embodiment of the present invention.
第２図はその等価回路図である。Ｎ型シリコン基板３の
下面にはドレイン端子１５に接続されたドレイン電極１
６が設けられている。基板３の上面にはＰ型ベース領域
４とゲート入力保護用のＰ領域６が設けられておシ、Ｐ
型ベース領域４内にはＮ型ソース領域２が、ま九Ｐ領域
６にはツェナーダイオードを形成するＮ型領域８．９が
設けられている。Ｎ型ソース領域の１つにはツェナーダ
イオードを形成するＮ型領域７が形成されている。FIG. 2 is its equivalent circuit diagram. A drain electrode 1 connected to a drain terminal 15 is provided on the lower surface of the N-type silicon substrate 3.
6 is provided. A P type base region 4 and a P region 6 for gate input protection are provided on the upper surface of the substrate 3.
An N-type source region 2 is provided in the type base region 4, and an N-type region 8.9 forming a Zener diode is provided in the P region 6. An N-type region 7 forming a Zener diode is formed in one of the N-type source regions.
Ｎ型領域２と基板３間のＰ型ベース領域４の表面にチャ
ンネルが形成され、その上に絶縁膜を介してポリシリコ
ンのゲート１極５が形成されている。A channel is formed on the surface of a P-type base region 4 between the N-type region 2 and the substrate 3, and a polysilicon gate 1 pole 5 is formed thereon with an insulating film interposed therebetween.
ゲート入力保護回路はＮ型領域７，８．９で形成され、
第２図の婢価回路に示すように、ツェナーダイオード１
７，１８．１９が入力端子１０とソース端子１４間に直
列に接続されるよう形成されている。The gate input protection circuit is formed by N-type regions 7, 8.9,
As shown in the low-cost circuit in Figure 2, the Zener diode 1
7, 18, and 19 are connected in series between the input terminal 10 and the source terminal 14.
これらツェナーダイオード１７，１８．１９はそれぞれ
Ｎ型領域７，８．９とベース領域４又はＰ領域６とで形
成され、通常のゲート入力信号に対してはツェナーダイ
オード１９と１７は逆バイアスされ、ツェナーダイオー
ド１８は屓バイアスされている。このため、ツェナーダ
イオード１７゜１８．１９の直列接続のもっている降伏
電圧は約２０Ｖであり、高１圧・高出力動作に対しても
十分高いゲート入力電圧を正常に加えることができる。These Zener diodes 17, 18, 19 are formed by N type regions 7, 8, 9 and base region 4 or P region 6, respectively, and for normal gate input signals, Zener diodes 19 and 17 are reverse biased. Zener diode 18 is biased. Therefore, the breakdown voltage of the series connection of the Zener diodes 17.degree.18.19 is about 20V, and a sufficiently high gate input voltage can be normally applied even for high single voltage, high output operation.
また、Ｐ領域６には横方向に分離してツェナーダイオー
ドとして動作するＮ領域８，９が形成されており、これ
らＮ領域８，９間上で入力電極１０に接続されるポンデ
ィングパッドを形成するよう十分広く分離されるので、
保護回路が動作した時、Ｎ領域８−Ｐ領域６−Ｎ領域９
一基板３で形成されるサイリスタは動作することはない
。従、って、保護回路が動作した時、いわゆるラッチア
ップ現象が生じることはない。Further, N regions 8 and 9 are formed in the P region 6 to be separated laterally and operate as Zener diodes, and a bonding pad connected to the input electrode 10 is formed between these N regions 8 and 9. separated widely enough so that
When the protection circuit operates, N area 8 - P area 6 - N area 9
A thyristor formed of one substrate 3 never operates. Therefore, when the protection circuit operates, a so-called latch-up phenomenon does not occur.
このように、本発明によれば、従来の製造プロセスを変
更することな〈実施できるため誤動作のない、静電気等
のサージ耐量の大きい絶縁ゲート型半導体装置を容易に
製造できる効果がある。As described above, according to the present invention, it is possible to easily manufacture an insulated gate type semiconductor device that does not malfunction and has a high resistance to surges such as static electricity because it can be carried out without changing the conventional manufacturing process.
第１図は本発明の一実施例を示す断面図、第２図は第１
図の等価回路図、第３図は従来のゲート保護回路の構造
を示す断面図である。
２・・・・・・ソース領域、３・・・・・・基板、４・
・・・・・ベース領域、５・・・・・・ゲート１極％６
−１２・・・・・・Ｐ領域、７、 ８． ９． １３．
１３’・・・・・・Ｎ領域、１０・・・・・・入力電
極、１１・・・・・・配線、１４・・・・・・ソース端
子、１５・・・・・・ドレイン端子、１７，１８．１９
・旧・・ツェナーダイオード。FIG. 1 is a sectional view showing one embodiment of the present invention, and FIG.
The equivalent circuit diagram shown in the figure and FIG. 3 are cross-sectional views showing the structure of a conventional gate protection circuit. 2... Source region, 3... Substrate, 4...
...Base region, 5...Gate 1 pole%6
-12...P area, 7, 8. 9. 13.
13'...N region, 10...Input electrode, 11...Wiring, 14...Source terminal, 15...Drain terminal, 17, 18.19
- Old... Zener diode.
Claims (1)
準電位間に挿入したゲート入力保護回路に通常のゲート
入力電圧に対して逆バイアスされる２つのツェナーダイ
オードと通常のゲート入力電圧に対して順バイアスされ
る１つのツェナーダイオードとの直列接続回路を用いた
ことを特徴とする絶縁ゲート電界効果型半導体装置。In an insulated gate field effect semiconductor device, the gate input protection circuit inserted between the gate and the reference potential includes two Zener diodes that are reverse biased with respect to the normal gate input voltage and one that is forward biased with respect to the normal gate input voltage. An insulated gate field effect semiconductor device characterized in that it uses a series connection circuit with one Zener diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60138714A JPS61296770A (en) | 1985-06-25 | 1985-06-25 | Insulated gate field effect type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60138714A JPS61296770A (en) | 1985-06-25 | 1985-06-25 | Insulated gate field effect type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61296770A true JPS61296770A (en) | 1986-12-27 |
Family
ID=15228410
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60138714A Pending JPS61296770A (en) | 1985-06-25 | 1985-06-25 | Insulated gate field effect type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61296770A (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0218968A (en) * | 1988-07-06 | 1990-01-23 | Nec Corp | Vertical mos field effect transistor |
| EP0372820A2 (en) * | 1988-12-02 | 1990-06-13 | Motorola Inc. | Semiconducteur device having high energy sustaining capability and a temperature compensated sustaining voltage |
| US4962411A (en) * | 1986-03-21 | 1990-10-09 | Nippondenso Co., Ltd. | Semiconductor device with current detecting function |
| JPH03203380A (en) * | 1989-12-29 | 1991-09-05 | Nec Corp | Protecting device for vertical type mos field effect transistor |
| FR2676870A1 (en) * | 1991-05-24 | 1992-11-27 | Sgs Thomson Microelectronics | PROTECTIVE STRUCTURE IN A CMOS CIRCUIT AGAINST LATCHING. |
| JPH0567742A (en) * | 1991-09-05 | 1993-03-19 | Mitsubishi Electric Corp | Input protective circuit |
| US5204988A (en) * | 1990-07-16 | 1993-04-20 | Fuji Electic Co., Ltd. | Mos semiconductor device having a surge protecting element |
| US5324971A (en) * | 1992-04-09 | 1994-06-28 | U.S. Philips Corporation | Power semiconductor device having over voltage protection |
| US5365085A (en) * | 1990-07-30 | 1994-11-15 | Nippondenso Co., Ltd. | Power semiconductor device with a current detecting function |
| US5426320A (en) * | 1993-04-21 | 1995-06-20 | Consorzio Per La Ricera Sulla Mmicroelectronica Nel Mezzogiorno | Integrated structure protection device for protecting logic-level power MOS devices against electro-static discharges |
| US5543645A (en) * | 1992-11-24 | 1996-08-06 | Sgs-Thomson Microelectronics S.A. | Forward overvoltage protection circuit for a vertical semiconductor component |
| EP3979331A1 (en) * | 2020-09-30 | 2022-04-06 | Infineon Technologies AG | Silicon carbide device with transistor cell and clamp region |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5821374A (en) * | 1981-07-29 | 1983-02-08 | Toshiba Corp | Semiconductor device |
-
1985
- 1985-06-25 JP JP60138714A patent/JPS61296770A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5821374A (en) * | 1981-07-29 | 1983-02-08 | Toshiba Corp | Semiconductor device |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4962411A (en) * | 1986-03-21 | 1990-10-09 | Nippondenso Co., Ltd. | Semiconductor device with current detecting function |
| JPH0218968A (en) * | 1988-07-06 | 1990-01-23 | Nec Corp | Vertical mos field effect transistor |
| US5365099A (en) * | 1988-12-02 | 1994-11-15 | Motorola, Inc. | Semiconductor device having high energy sustaining capability and a temperature compensated sustaining voltage |
| EP0372820A2 (en) * | 1988-12-02 | 1990-06-13 | Motorola Inc. | Semiconducteur device having high energy sustaining capability and a temperature compensated sustaining voltage |
| US5631187A (en) * | 1988-12-02 | 1997-05-20 | Motorola, Inc. | Method for making semiconductor device having high energy sustaining capability and a temperature compensated sustaining voltage |
| JPH03203380A (en) * | 1989-12-29 | 1991-09-05 | Nec Corp | Protecting device for vertical type mos field effect transistor |
| US5204988A (en) * | 1990-07-16 | 1993-04-20 | Fuji Electic Co., Ltd. | Mos semiconductor device having a surge protecting element |
| US5365085A (en) * | 1990-07-30 | 1994-11-15 | Nippondenso Co., Ltd. | Power semiconductor device with a current detecting function |
| FR2676870A1 (en) * | 1991-05-24 | 1992-11-27 | Sgs Thomson Microelectronics | PROTECTIVE STRUCTURE IN A CMOS CIRCUIT AGAINST LATCHING. |
| JPH0567742A (en) * | 1991-09-05 | 1993-03-19 | Mitsubishi Electric Corp | Input protective circuit |
| US5324971A (en) * | 1992-04-09 | 1994-06-28 | U.S. Philips Corporation | Power semiconductor device having over voltage protection |
| US5780895A (en) * | 1992-10-24 | 1998-07-14 | Sgs-Thomson Microelectronics S.A. | Forward overvoltage protection circuit for a vertical semiconductor component |
| US5543645A (en) * | 1992-11-24 | 1996-08-06 | Sgs-Thomson Microelectronics S.A. | Forward overvoltage protection circuit for a vertical semiconductor component |
| US5563436A (en) * | 1992-11-24 | 1996-10-08 | Sgs-Thomson Microelectronics S.A. | Forward overvoltage protection circuit for a vertical semiconductor component |
| US5426320A (en) * | 1993-04-21 | 1995-06-20 | Consorzio Per La Ricera Sulla Mmicroelectronica Nel Mezzogiorno | Integrated structure protection device for protecting logic-level power MOS devices against electro-static discharges |
| EP3979331A1 (en) * | 2020-09-30 | 2022-04-06 | Infineon Technologies AG | Silicon carbide device with transistor cell and clamp region |
| US11876133B2 (en) | 2020-09-30 | 2024-01-16 | Infineon Technologies Ag | Silicon carbide device with transistor cell and clamp region |
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