JP3522532B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMOS (Do
uble diffused Metal Oxide
(Semiconductor) structure lateral MOSFET
The present invention relates to a semiconductor device such as a power IC in which T is integrated. 2. Description of the Related Art A lateral high voltage MOSFE having a DMOS structure is used.
In a semiconductor device such as a power IC in which T is integrated, a planar pattern of a source region, a base region, and a drain region may be formed in a stripe shape. FIG.
FIG. 1 (a) is a plan view, FIG. 2 (b) is a cross-sectional view of an essential part taken along line XX of FIG. 1 (a), and FIG. FIG. 5 is a cross-sectional view of a main part taken along line YY in FIG. In FIG. 3, an n drain region 2 is formed in a surface layer of a p substrate 1, a p base region 3 is formed in a surface layer of the n drain region 2, and an n source region 4 is formed in a surface layer of the p base region 3. Is formed, and ap base pickup region 5 is formed in contact with n source region 4. A gate electrode 8 is formed via a gate oxide film 6 on the surface of p base region 3 sandwiched between n source region 4 and n drain region 2. LOCOS oxide film 7 is formed on the surface of n drain region 2 and the surface of p substrate 1 apart from p base region 3. Further, an n ⁺ drain region 21 for forming an ohmic contact with the n drain region 2 is formed on the surface layer of the n drain region 2 at a distance from the p base region. n
Source region 4 is connected to source electrode 11 via source contact region 9, p base pickup region 5 is connected to base electrode 12 via pickup contact region 10, and n ⁺ drain region 21 is via drain contact region 22. To the drain electrode 23. 2a is an end of an n drain region, 3a is an end of a p base region, 4a is an end of an n source region, 5a is an end of a p base pickup region, 7a is an end of a LOCOS oxide film, 8a,
8b is a gate electrode end, and 13 is a junction between the n source region and the p base pickup region. This horizontal MOSFET
T is a DMOS structure, and each of the n ⁺ drain regions 2a for making ohmic contact between the n source region 4, the p base region 3, and the n drain region 2 has a stripe pattern. A source contact region 9 is disposed at an end A of the striped n source region 4.
At the end A, a parasitic npn transistor (FIG. 3) is formed by the n source region 4, the p base region 3, and the n drain region.
((C) shows a transistor symbol). A parasitic resistance (indicated by a resistance symbol in FIG. 3C) is also formed in the p base region 3. Next, the operation of the lateral MOSFET will be described. In FIG. 3B, when a positive voltage is applied to the drain electrode 23 and a positive voltage is applied to the gate electrode 8 with respect to the source electrode 11, a channel is formed on the surface of the p base region 3, and a drain electrode is formed. A current flows from 23 to the source electrode 11. When the voltage of the gate electrode 8 is made lower than the gate threshold voltage, the channel closes and the horizontal M
The OSFET is turned off. The source electrode 11 and the pickup electrode 12 are usually connected. When a surge voltage is applied between the source electrode 11 and the drain electrode 23 in the off state of the lateral MOSFET, a depletion layer is formed in the n drain region 2 and the p base region 3, and the surge voltage is reduced. When the avalanche voltage exceeds the avalanche voltage of the MOSFET, an avalanche current flows through the path of the n-drain region 2-p base region 3-p base pickup region 5. A voltage drop occurs due to the product of the avalanche current and the parasitic resistance, and the parasitic npn transistor operates due to the voltage drop. However, in the conventional lateral MOSFET, the hFE of the parasitic npn transistor is as small as 50 or less, so that the collector current, which is the product of the avalanche current and the hFE, is small.
T did not break. However, since the lateral MOSFET integrated in the power IC is manufactured in the same process as the low-voltage bipolar element integrated simultaneously, the thickness of the p base region 3 is reduced. Becomes thinner, and therefore the horizontal M
HFE of parasitic npn transistor formed in OSFET
Is as large as 50 or more. In the conventional lateral MOSFET, a source contact region 9 is arranged at an end A in a longitudinal direction of an n source region, and a p base region 3 is formed so as to surround the n source region 4. DM with such a plane pattern
In MOSFET of OS structure, if h _FE of the parasitic npn transistor 50 or more and high lateral parasitic resistance of the p base region 3 becomes high. When a surge voltage or the like is applied to this lateral MOSFET, a parasitic npn
In particular, the conventional lateral MOSFET has a low surge withstand voltage of 1000 V or less in an ESD test, which is a surge voltage test, and several hours even in a high-temperature voltage application test, which is a reliability test. There was something to destroy. In the ESD test, a closed loop is formed by a capacitor C, a series resistor Rs, a switch, and a device under test.
In this test, the charge charged in C is closed by a switch and discharged by the device under test to check whether the device under test is broken. Usually, as an example of the condition, C = 100 pF, Rs = 1.5 kΩ
To charge C to a predetermined voltage. The higher the charging voltage at this time, the higher the surge withstand capability. An object of the present invention is to solve the above problems,
It is an object of the present invention to provide a semiconductor device such as a lateral MOSFET having a high withstand voltage and a high withstand voltage capable of securing reliability against application of a high temperature voltage. [0012] In order to achieve the above object, a second conductivity type drain region is selectively formed on a first conductivity type semiconductor substrate, and a drain region is formed on a surface layer of the drain region. First
A conductive type base region is selectively formed, a second conductive type source region is selectively formed in a surface layer of the base region, and a first conductive type base pickup region in contact with the base region is formed in the source region. A semiconductor device in which a gate electrode is formed on the base region sandwiched between the source region and the drain region via a gate oxide film, and a planar pattern of the source region is formed in a stripe shape; Forming the first conductivity type base pickup region at an end portion in the longitudinal direction of the source region;
Parasitic bipolar formed by rain region and base region
It is assumed that the hFE of the transistor is 50 or more. With this configuration, no parasitic bipolar transistor is formed at the end of the stripe, and the surge withstand voltage and the reliability when a high-temperature voltage is applied can be improved. The operation of the parasitic bipolar transistor can be reduced by forming the base pickup region in a region other than the longitudinal end of the source region and forming a metal wiring on the base pickup region. . As a result, it is possible to improve the surge resistance and the reliability when a high-temperature voltage is applied . DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description of the embodiments, the first conductivity type is p-type and the second conductivity type is n-type. FIG. 1 shows a lateral MOSFET according to a first embodiment of the present invention.
(A) is a plan view, and (b) is a line Y- in FIG.
It is principal part sectional drawing cut | disconnected by the Y line. The same reference numerals in the drawing denote the same parts as in FIG. Also, X in FIG.
The cross-sectional view of the main part taken along line -X is the same as that of FIG. 3B. Here, the cross-sectional view of the main part taken along line XX of FIG. 1A and the description thereof are omitted. In FIG. 1, a surface concentration of about 3 × 10 ¹⁶ cm ⁻³ is applied to a surface layer of a p-substrate 1 having a specific resistance of about 150 Ωcm.
An n-drain region 2 having a diffusion depth of about 4 μm (the n-drain region of an n-channel DMOS structure MOSFET) is formed, and the surface concentration of the n-drain region 2 is 2 × 10 ¹⁷ cm ⁻ A p base region 3 of about ³ and Xj of about 1 μm is formed, and an n source region 4 of a surface concentration of about 1 × 10 ²¹ cm ⁻³ and Xj of about 0.2 μm is formed on the surface layer of the p base region 3. Then, p base pickup region 5 is formed in contact with n source region 4. The p base pickup region 5 may be formed apart from the n source region 4. Next, a gate electrode 8 is formed on the surface of the p base region 3 sandwiched between the n source region 4 and the n drain region 2 with a 200.degree. Thick gate oxide film 6 therebetween (FIG. 3).
(See (b)). LOCOS oxide film 7 is formed on the surface of n drain region 2 and the surface of p substrate 1 apart from p base region 3. Also, p is added to the surface layer of the n drain region 2.
An n ⁺ drain region 21 for forming an ohmic contact with the n drain region 2 is formed apart from the base region 3. The n source region 4 is a source contact region 9
, P base pickup region 5 is connected to base electrode 12 via pickup contact region 10, and n ⁺ drain region 21 is connected to drain electrode 23 via drain contact region 22. The source electrode 11, the drain electrode 24 and the base electrode 12 are connected to the metal wiring 50. The gate electrode 8 is formed so as to surround the stripe-shaped n source region 4 and n ⁺ drain region 21. 2a is an end of an n drain region, 3a is an end of a p base region, 4a is an end of an n source region, 5a is an end of a p base pickup region, 7a is an end of a LOCOS oxide film, 8a,
8b is a gate electrode end, and 13 is a junction between the n source region 4 and the p base pickup region 5. MOSF of FIG.
In ET, the hFE of the parasitic npn transistor (parasitic bipolar transistor) formed by the n source region 4-p base region 3-n drain region 2 is 50, and its BVce
o (Gate-open collector-emitter withstand voltage) is 2
0V. The breakdown voltage between the source and the drain of the n-channel DMOS is 100V. The hFE of the parasitic npn transistor is set to 5
In the following, the value n is set to 0 as described above.
The function of the pn transistor is weak, and the surge resistance is not reduced. However, in the case of 50 or more, the parasitic npn
The function of the transistor is strong, and therefore, the structure of the lateral MOSFET shown in this embodiment has an effect of improving the surge resistance. In the lateral MOSFET shown in FIG. 1, the end B in the longitudinal direction of the n source region 4 does not terminate at the source contact region 9 but terminates at the pickup contact region 10. According to this structure, in the lateral MOSFET having the conventional structure shown in FIG.
Then, the formed parasitic npn transistor disappears in the lateral MOSFET of FIG. 1, and due to a surge voltage or the like,
Even when an avalanche current flows into p base region 3, the avalanche current flows out to pickup contact region 10 via base pickup region 5. Therefore, in the lateral MOSFET shown in FIG.
Since the n source region 4 is not formed at the longitudinal end B of the source region 4, the operation of the parasitic npn transistor does not occur. Therefore, the surge voltage test E
In the SD test, the charging voltage is twice or more the value of the lateral MOSFET of FIG. 3, and the surge withstand capability can be greatly improved. Further, in a reliability test such as application of a high-temperature voltage, the standard for 1000 hours can be sufficiently satisfied. Also, as shown in FIG. 1A, by providing the p base pickup region 5 at a position other than the end B of the n source region 4, the function of the parasitic npn transistor can be reduced and the surge withstand capability can be increased. . FIG. 2 shows a second embodiment of the present invention.
1A is a plan view, FIG. 2B is a cross-sectional view of an essential part taken along line XX of FIG. 1A, and FIG. 1C is a horizontal MOSFET of the embodiment. FIG. 5 is a sectional view of a main part taken along line YY of FIG. Note that the reference numerals in the figure are the same for the same parts as those in FIG. In FIG. 2, the specific resistance of the p substrate 1 is 15Ω.
An n-channel DMOS is formed on the surface by about cm, and an n-drain buried region 31 is formed below the n-channel DMOS. The n-drain region 2d has an impurity concentration of 5 × 10 ¹⁵ by epitaxial growth on the surface layer.
cm ^-3 or so, it is formed with a thickness of 4μm about. The p base region 3 has a surface concentration of 2 × 1 in the surface layer of the n drain region 2d.
Xj is formed at about 0 ¹⁷ cm ^-3 and Xj is about 1 μm. An n source region 4 is formed on the surface layer at a surface concentration of about 1 × 10 ²¹ cm ⁻³ and Xj is about 0.2 μm. The p base region 3 sandwiched between the n source region 4 and the n drain region 2d
A gate electrode 8 is formed on the surface of the substrate with a 200-nm thick gate oxide film 6 interposed therebetween. Further, an n drain wall region 32 is formed and becomes a part of the drain region. The n ⁺ drain region 21 is formed on the surface layer of the n drain wall 32. Above n source region 4, p base pickup region 5
Above, the source electrode 11, the pickup electrode 12, and the drain electrode 22 are formed on the n ⁺ drain region 21, and the metal wiring 50 is formed on these electrodes. A gate electrode 8 is formed on the surface of p base region 3 via a gate oxide film 6 having a thickness of 200 °. Here, n source region 4-p base region 3
The hFE of the parasitic npn transistor formed by the -n drain region 2d is 50, and its Vceo is 20V. And n
The breakdown voltage between the source and drain of the channel DMOS is 100
V. As shown in FIG. 3A, the planar pattern has an n source region 3 and an n ⁺ drain region 21 formed in a stripe shape. The gate electrode 8 is connected to the n source region 4, n ⁺
It is formed so as to surround the drain region 21. Also, in the lateral MOSFET of FIG. 2, similarly to the lateral MOSFET of FIG. 1, the end B of the n source region 4 does not terminate at the source contact region 9 but terminates at the pickup contact region 10. With this structure, in the lateral MOSFET of the conventional structure shown in FIG. 3, the parasitic npn transistor formed at the longitudinal end A of the n source region 4 disappears at the lateral end B of the lateral MOSFET of FIG. Even when an avalanche current flows into the p base region 3 due to a surge voltage or the like, the avalanche current flows out to the pickup contact region 10 via the base pickup region 5. Therefore, in the lateral MOSFET shown in FIG.
Since the n source region 4 is not formed at the longitudinal end B of the source region 4, the operation of the parasitic npn transistor does not occur. Therefore, the surge voltage test ES
In the D test, the charging voltage was twice or more the value of the lateral MOSFET of FIG. 3, and it was found that the surge withstand capability was greatly improved. Further, in a reliability test such as application of a high-temperature voltage, the standard for 1000 hours was sufficiently satisfied. In the lateral MOSFET of FIG. 2, since the drain current flows through the n-drain buried layer 31 and the n-drain wall 32, the on-resistance of the MOSFET is smaller than that of the lateral MOSFET of FIG. Further, although the lateral MOSFET has been described as an example of the semiconductor device, this embodiment can be applied to other lateral MOS devices. According to the present invention, the end of the stripe-shaped n source region in the longitudinal direction is set as the p base pickup region, so that the surge withstand capability at this end is more than doubled compared with the conventional case. Can be done. In addition, the reliability of high-temperature voltage application can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a lateral MOSFET according to a first embodiment of the present invention;
2A is a plan view, and FIG. 2B is a cross-sectional view of a main part taken along line YY in FIG. 2A. FIG. 2 is a lateral MOSFET according to a second embodiment of the present invention.
(A) is a plan view, (b) is a cross-sectional view of a main part taken along line XX of (a), (c) is a cross-sectional view of a main part cut along line YY of (a). A conventional striped lateral MOSFET
(A) is a plan view, (b) is a cross-sectional view of a main part taken along line XX of (a), (c) is a cross-sectional view of a main part cut along line YY of (a). 1 p substrate 2 n drain region 2 a n drain region end 2 d n drain 3 p base region 3 a p base region end 4 n source region 4 a n source region end 5 p base pickup region 5 a p base pickup region end 6 gate oxide film 7 LOCOS oxide film 7a LOCOS oxide film 8 Gate electrode 8a Gate electrode end 8b Gate electrode end 9 Source contact region 10 Pickup contact region 11 Source electrode 12 Pickup electrode 13 Junction point 21 n ⁺ Drain region 21a n ⁺ Drain region end 22 Drain contact region 23 drain electrode 31 n drain buried layer 32 n drain wall 50 metal wiring A end B end

Claims (1)

(57) Claims 1. A second conductivity type drain region is selectively formed on a first conductivity type semiconductor substrate, and a first conductivity type base region is formed on a surface layer of the drain region. Selectively forming a second conductivity type source region on a surface layer of the base region;
Forming a first conductivity type base pickup region in contact with the base region in the source region; forming a gate electrode on the base region sandwiched between the source region and the drain region via a gate oxide film; In the semiconductor device in which the planar pattern of the above is formed in a stripe shape, the first portion is formed at the longitudinal end of the stripe source region.
A conductive type base pickup area is formed, and the source area is formed.
Parasitic region formed in the region, drain region and base region.
A semiconductor device, wherein h FE of the bipolar transistor is 50 or more .