JP2008244236A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To effectively reduce resistance between a source region and a substrate without increasing an element size in a transistor having substrate connection parts. <P>SOLUTION: A substrate connection part 13A is formed on a portion where a contact 15 selected at a rate of one to N (N is two in the figure) out of a plurality of contacts 15 each of which connects a high density diffusion layer 12 in a source region 10A to a source wire 14 by diffusing an impurity which is conductive similarly to the substrate and has a high concentration so as to reach a substrate body. The substrate connection part 13A is formed like a square pole whose side face has an angle of 45° with respect to a boundary with a gate region 20. Thereby, as compared with the case that the square pole-like substrate connection part is formed in parallel with the boundary, the resistance of the source region held between the substrate connection part 13A and a gate electrode can be reduced. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a structure of a substrate connection portion for preventing a parasitic bipolar operation due to an increase in substrate potential in a semiconductor device, particularly, a power MOS transistor that flows a large current.

  For example, an N-channel MOS transistor (hereinafter referred to as “NMOS”) forms an n-type drain region and a source region facing each other across a channel region on the surface of a p-type semiconductor substrate, and a gate insulating film on the channel region. The gate electrode is formed through the gate electrode, and the drain-source current is controlled by the voltage applied to the gate electrode. In this configuration, when the bipolar transistor is used, the n-type drain corresponds to the collector, the p-type substrate corresponds to the base, and the n-type source corresponds to the emitter.

  When a voltage is applied to such an NMOS gate electrode and a large current flows between the drain and source, the potential of the substrate rises due to the resistance between the source region and the substrate. An increase in the potential of the substrate means an increase in the base potential of the NPN transistor. For this reason, when the increase in the base potential exceeds the threshold voltage between the base and the emitter (for example, 0.7 V), the voltage between the collector and the emitter of the parasitic NPN transistor (that is, the NMOS voltage) is independent of the voltage of the NMOS gate electrode. A latch-up state in which current continues to flow between the drain and the source occurs. In addition, even when a surge such as static electricity enters the drain, a current flows from the drain to the substrate. This current increases the potential of the substrate and turns on the parasitic NPN transistor, causing an overcurrent to flow between the drain and source. The NMOS may be destroyed.

  As a countermeasure against such latch-up and electrostatic breakdown, especially in a power MOS transistor that conducts a large current, a substrate connection for suppressing the occurrence of a potential difference between the source and the substrate by bringing a part of the source region into close contact with the substrate There are many parts.

  2A and 2B are configuration diagrams of a conventional NMOS having a substrate connection portion, where FIG. 2A is a plan view, and FIGS. 2B and 2C are respectively XX and XX in FIG. It is sectional drawing which shows the cross section in YY.

  The NMOS is formed in an element formation region isolated by an element isolation portion 2 provided on a p-type substrate 1, and a source region 10 is formed in the center, and gate regions are formed on both sides of the source region 10. A drain region 30 is formed via 20.

  The source region 10 includes an electric field relaxation layer 11 in which low concentration n-impurities are diffused throughout the region, and a high concentration diffusion layer 12 in which high concentration n + impurities are diffused inside the electric field relaxation layer 11. Yes. Further, as shown in FIG. 2B, the source region 10 has a high concentration so as to reach a p-type substrate body from the surface of the substrate 1 to a part of the high concentration diffusion layer 12 and the electric field relaxation layer 11. A substrate connecting portion 13 in which p + impurities are diffused is formed. The substrate connecting portion 13 is a regular quadrangular prism having a square shape with a side length of about 2 μm. The side of the square is arranged in parallel to the boundary line with the gate region 20 as shown in FIG. Has been.

  The drain region 30 is formed by an electric field relaxation layer 31 in which low concentration n-impurities are diffused throughout the region, and a high concentration diffusion layer 32 in which high concentration n + impurities are diffused inside the electric field relaxation layer 31. Yes.

  A gate insulating film 3 is formed on the surface of the substrate in the element formation region isolated by the element isolation portion 2, and part of the gate insulating film 3 in the gate region 20 is an electric field relaxation layer of the source region and the drain region. A gate electrode 21 is formed so as to overlap with 11 and 31.

  The entire surface of the substrate 1 on which the gate electrode 21 is formed is covered with the insulating layer 4, and the source wiring 14, the drain wiring 33, and a gate wiring (not shown) are provided on the insulating layer 4. The source wiring 14 and the high-concentration diffusion layer 12 and the substrate connecting portion 13 are electrically connected by a contact 15 formed through the insulating layer 4. Further, the drain wiring 33 and the high concentration diffusion layer 32 are also electrically connected by a contact 34 formed so as to penetrate the insulating layer 4.

  Although not shown, the wiring for the gate electrode 21 is similarly formed. Further, in the active region outside the element isolation portion 2, a substrate potential extraction portion 5 in which high-concentration p + impurities are diffused is formed, and the surface of the substrate 1 on which the NMOS is formed is protected by a protective film 6. .

  For example, in the case of an NMOS in which a large current flows with a power supply voltage of 20 V class, such a substrate connecting portion 13 is provided at intervals of 10 μm in the gate width direction (direction parallel to the gate region 20). And the parasitic bipolar operation due to the increase in the substrate potential can be prevented.

JP-A-5-206470 Japanese Unexamined Patent Publication No. 7-161984 Japanese Patent Laid-Open No. 10-4192

  However, since the source-side resistance of the substrate connecting portion 13 is more than twice that of the high-concentration diffusion layer 12, current hardly flows through the source region 10 facing the substrate connecting portion 13. For example, when the gate width is 50 μm, it is necessary to form 4 to 5 substrate connecting portions 13. Due to the formation of the substrate connecting portion 13, the length occupied by the substrate connecting portion 13 becomes 10 μm in the gate width direction, and the effective width of the gate is reduced by 10 to 20%. For this reason, it is necessary to increase the gate width by the reduced amount, and there is a problem that the element size increases.

  An object of the present invention is to provide a semiconductor device having a substrate connection portion that can reduce the resistance between a source region and a substrate without increasing the element size.

  The present invention relates to a semiconductor substrate of a first conductivity type, a first electrode region formed by diffusing a second conductivity type impurity on the semiconductor substrate, and a semiconductor substrate with a gate region separated from the first electrode region. A second electrode region formed by diffusing impurities of a second conductivity type thereon; an insulating layer formed on the semiconductor substrate; and an electrode formed on the first electrode region with the insulating layer interposed therebetween A second conductive layer in the first electrode region is arranged in a row at a constant interval parallel to a boundary line between the wiring and the first electrode region and the gate region, and penetrates the insulating layer from the electrode wiring. A plurality of contacts connected to the type impurity diffusion region, and a contact selected at a ratio of N (N is an integer of 2 or more) among the plurality of contacts to the first electrode region of the semiconductor substrate High-concentration first-conductivity-type impurities at locations connected to In a semiconductor device having a plurality of substrate connection portions formed to diffuse so as to reach the semiconductor substrate body, the side surfaces of the plurality of substrate connection portions are border lines between the first electrode region and the gate region. It is characterized in that it is formed in a regular quadrangular prism shape having an oblique angle.

  In the present invention, the substrate connecting portion for connecting the first electrode region to the substrate is formed in a regular quadrangular prism shape whose side surface has an oblique angle with respect to the boundary line between the first electrode region and the gate region. As a result, compared to a regular quadrangular columnar substrate connection portion formed in parallel to the boundary line, the current flowing range is widened, and the resistance between the source region and the substrate is reduced without increasing the element size. There is an effect that can be.

  The above and other objects and novel features of the present invention will become more fully apparent when the following description of the preferred embodiment is read in conjunction with the accompanying drawings. However, the drawings are for explanation only, and do not limit the scope of the present invention.

  FIG. 1 is a configuration diagram of an NMOS showing Embodiment 1 of the present invention, where FIG. 1A is a plan view, and FIGS. 1B and 1C are AA in FIG. 1A, respectively. , BB is a cross-sectional view showing a cross section. In FIG. 1, elements common to the elements in FIG.

  The NMOS is formed in an element formation region isolated by an element isolation portion 2 provided on a p-type semiconductor substrate 1, and a source region 10 A is formed in the center, and gates are formed on both sides of the source region 10. A drain region 30 is formed through the region 20.

  The source region 10A has an electric field relaxation layer 11 in which low concentration n-impurities are diffused to a depth of about 0.34 μm in the entire region, and a high concentration n + impurity has a depth of about 0.1 μm inside the electric field relaxation layer 11. A diffused high concentration diffusion layer 12 is provided. Further, in the source region 10A, as shown in FIG. 1B, a high concentration diffusion layer 12 and a portion of the electric field relaxation layer 11 are formed so as to reach the p-type substrate body from the surface of the substrate 1. Substrate connecting portions 13A in which p + impurities are diffused are formed at regular intervals in parallel with the boundary line with the gate region 20.

  The substrate connecting portion 13A is a regular quadrangular prism having a square cross section with a side length of about 2 μm, and the square side of the board connecting portion 13A is in relation to the boundary line with the gate region 20 as shown in FIG. It arrange | positions so that it may have an angle (45 degrees in this figure).

  The drain region 30 is formed by an electric field relaxation layer 31 in which low concentration n-impurities are diffused throughout the region, and a high concentration diffusion layer 32 in which high concentration n + impurities are diffused inside the electric field relaxation layer 31. Yes.

  A gate insulating film 3 is formed on the surface of the substrate in the element formation region isolated by the element isolation portion 2, and part of the gate insulating film 3 in the gate region 20 is an electric field relaxation layer of the source region and the drain region. A gate electrode 21 is formed so as to overlap with 11 and 31.

  The entire surface of the substrate 1 on which the gate electrode 21 is formed is covered with the insulating layer 4, and the source wiring 14, the drain wiring 33, and a gate wiring (not shown) are provided on the insulating layer 4. The source wiring 14 and the high-concentration diffusion layer 12 and the source wiring 14 and the substrate connecting portion 13A are electrically connected by contacts 15 formed through the insulating layer 4, respectively. In FIG. 1, contacts 15 for the high-concentration diffusion layer 12 and contacts 15 for the substrate connection portion 13A are alternately provided.

  Further, the drain wiring 33 and the high concentration diffusion layer 32 are also electrically connected by a contact 34 formed so as to penetrate the insulating layer 4. Although not shown, the wiring for the gate electrode 21 is similarly formed. Further, in the active region outside the element isolation portion 2, a substrate potential extraction portion 5 in which high-concentration p + impurities are diffused is formed, and the surface of the substrate 1 on which the NMOS is formed is protected by a protective film 6. .

  For example, when such an NMOS is used for the purpose of flowing a large current at a power supply voltage of 20 V, the source region 10 is provided by providing the substrate connecting portions 13A every 10 μm in the gate width direction (direction parallel to the gate region 20). The resistance between the substrate 1 and the substrate 1 can be kept low, and a parasitic bipolar operation due to an increase in substrate potential can be prevented.

  FIG. 3 is an operation comparison diagram of the NMOS of FIGS. 1 and 2 and schematically shows a path of a current flowing through the source region. In FIG. 3, a solid line indicates the NMOS substrate connection 13A and current of FIG. 1, and a broken line indicates the NMOS substrate connection 13 and current of FIG.

  As shown in FIG. 3, in the NMOS shown in FIG. 2, the side of the square substrate connecting portion 13 is arranged in parallel with the gate electrode. For this reason, the current flowing from the drain region to the contact 15 in the source region through the gate region concentrates on a narrow portion between the gate electrode and the substrate connecting portion 13.

  On the other hand, in the NMOS of FIG. 1, the side of the square substrate connecting portion 13A has an inclination of 45 ° with respect to the gate electrode, and therefore flows from the drain region to the source region contact 15 via the gate region. The current can flow diagonally.

  As described above, the NMOS according to the first embodiment is formed so that the side surface of the substrate connecting portion 13A is inclined at 45 ° with respect to the gate electrode, so that it is sandwiched between the substrate connecting portion 13A and the gate electrode. The resistance of the source region can be reduced compared to the NMOS of FIG. Accordingly, there is an advantage that the resistance between the source region and the substrate can be effectively reduced without forming a wide gate width (without increasing the element size).

  FIG. 4 is a configuration diagram of an NMOS showing Embodiment 2 of the present invention, where FIG. 4A is a plan view, and FIGS. 4B and C are CC lines in FIG. It is sectional drawing which shows the cross section in DD. In FIG. 4, elements common to the elements in FIG.

  This NMOS is provided with a source region 10B having a different structure in place of the source region 10A in the NMOS of FIG.

  That is, as shown in FIGS. 4B and 4C, the source region 10B is formed in a region below the bottom surface of the high concentration diffusion layer 12 in which high concentration n + impurities are diffused to a depth of about 0.1 μm. It has an embedded substrate connection portion 16 in which a high-concentration p + impurity is embedded at a depth of about 0.43 μm using an energy ion implantation technique.

  Further, as shown in FIGS. 4A and 4B, the substrate connection portion 13B for connecting the embedded substrate connection portion 16 to the source wiring 14 is provided only at one position in the center portion of the source region 10. Yes. The substrate connection portion 13B is a square having a side length of about 2 μm, similar to the substrate connection portion 13A in FIG. 1, and the side of the square is connected to the gate region 20 as shown in FIG. It is arranged so as to form an angle of 45 ° with respect to the boundary line. The substrate connection portion 13B is formed by diffusing a high concentration p + impurity in the high concentration diffusion layer 12 so as to reach the embedded substrate connection portion 16 from the surface of the substrate 1 to a depth of about 0.15 μm. Other configurations are the same as those in FIG.

  In this NMOS, the buried substrate connecting portion 16 formed in the entire bottom region of the bottom surface of the high concentration diffusion layer 12 in the source region 10B is connected to the substrate 1, and the high concentration p + diffused in the center of the buried substrate connecting portion 16 is used. It is connected to the source wiring 14 through the substrate connecting portion 13B made of impurities. Thereby, the source electrode and the substrate 1 are held at substantially the same potential.

  As described above, in the NMOS according to the second embodiment, the embedded substrate connecting portion 16 and the source wiring 14 formed on the entire bottom portion of the bottom of the source region 10B are connected by one substrate connecting portion 13B. As a result, the source electrode and the substrate 1 are held at substantially the same potential, so that latch-up and electrostatic breakdown due to an increase in substrate potential can be effectively suppressed, and the substrate connecting portion 13B is only at one location. The source region is hardly affected by the substrate connecting portion 13B, and there is an advantage that it is not necessary to increase the source width and the device can be miniaturized.

In addition, this invention is not limited to the said Example, A various deformation | transformation is possible. Examples of this modification include the following.
(1) Although the NMOS has been described, the present invention can be similarly applied to a P-channel MOS transistor.
(2) Depending on the application, it is possible to provide the substrate connection portion in the drain region instead of the source region.
(3) In Example 1, although the example which provided the board | substrate connection part 13A in the ratio of one piece with respect to two contacts of 10 A of source regions was demonstrated, the dimension of the board | substrate connection part, the number of arrangement | positioning, and a position are arbitrary. It can be set appropriately according to the capacity of the transistor.
(4) Although the substrate connection part 13B of Example 2 is one place, you may provide two or more places. Further, the shape of the board connecting portion 13B is not limited to a regular quadrangular prism, and may be a cylindrical shape or the like.
(5) Although the NMOS in which the drain region 30 is formed on both sides of the source regions 10A and 10B with the gate region 20 interposed therebetween is illustrated, the number of source regions, gate regions, and drain regions is not limited to this.

It is a block diagram of NMOS which shows Example 1 of this invention. It is a block diagram of a conventional NMOS. FIG. 3 is an operation comparison diagram of the NMOS of FIGS. 1 and 2. It is a block diagram of NMOS which shows Example 2 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 Element isolation part 3 Gate insulating film 4 Insulating layer 5 Substrate potential extraction part 6 Protective film 10A, 10B Source region 11, 31 Electric field relaxation layer 12, 32 High concentration diffusion layer 13A, 13B Substrate connecting part 14 Source wiring 15, 34 Contact 16 Embedded Substrate Connection Portion 20 Gate Region 21 Gate Electrode 30 Drain Region 33 Drain Wiring

Claims (4)

A first conductive type semiconductor substrate; a first electrode region formed by diffusing a second conductive type impurity on the semiconductor substrate; and a second region on the semiconductor substrate with a gate region separated from the first electrode region. A second electrode region formed by diffusing conductive impurities, an insulating layer formed on the semiconductor substrate, an electrode wiring formed on the first electrode region with the insulating layer interposed therebetween, A second conductivity type impurity diffusion region of the first electrode region, which is arranged in a row at a constant interval in parallel with a boundary line between the first electrode region and the gate region and penetrates the insulating layer from the electrode wiring. A plurality of contacts that are connected to the first electrode region of the semiconductor substrate, and contacts that are selected at a ratio of N (N is an integer of 2 or more) among the plurality of contacts to the first electrode region of the semiconductor substrate In addition, a high-concentration first conductivity type impurity is added to the semiconductor In a semiconductor device having a plurality of board connecting portion which is formed by diffusing to reach the plate body,
The semiconductor device according to claim 1, wherein the plurality of substrate connection portions are formed in a regular quadrangular prism shape whose side surfaces have an oblique angle with respect to a boundary line between the first electrode region and the gate region. A first conductivity type semiconductor substrate;
A first electrode region formed by diffusing a second conductivity type impurity on the semiconductor substrate;
A buried substrate connecting portion formed by implanting a high-concentration first conductivity type impurity into the semiconductor substrate below the first electrode region;
A second electrode region formed by diffusing a second conductivity type impurity on the semiconductor substrate across the gate region from the first electrode region;
An insulating layer formed on the semiconductor substrate;
An electrode wiring formed on the first electrode region with the insulating layer interposed therebetween;
A plurality of contacts connecting from the electrode wiring to the second conductivity type impurity diffusion region of the first electrode region through the insulating layer;
At least one contact of the plurality of contacts is formed by diffusing high-concentration first conductivity type impurities so as to reach the buried substrate connecting portion at a position where the contact is connected to the first electrode region of the semiconductor substrate. Board connection part
A semiconductor device comprising the semiconductor device.   3. The semiconductor according to claim 1, wherein the substrate connecting portion is formed in a regular quadrangular prism shape having a side surface having an angle of 45 degrees with respect to a boundary line between the first electrode region and the gate region. apparatus. The first electrode region and the second electrode region are formed by diffusing a low concentration second conductivity type impurity in the peripheral portion and a high concentration in the central portion, respectively.
4. The device according to claim 1, wherein the contact is disposed so as to be connected to a region where the high-concentration second conductivity type impurity in the first electrode region is diffused. 5. Semiconductor device.

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