JP2002176347A - Overcurrent limiting semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a two-terminal overcurrent limiting semiconductor device which is monolithic on the same substrate and prevents overcurrent flowing to an electric load connected to the semiconductor device. SOLUTION: This overcurrent limiting semiconductor device of a two-terminal monolithic structure comprises a static induction transistor 10 and a junction field-effect transistor 20, the static induction transistor 10 and the field-effect transistor 20 are serially connected, the drain 12 of the transistor 10 and the gate 23 of the transistor 20 are used as an anode electrode 1, the gate 13 of the transistor 10 and the drain 22 of the transistor 20 are used as a cathode electrode 2, interrupts overcurrent with a high breakdown voltage to protect the electric load without using a depression MOS field-effect transistor. Furthermore, a two-terminal bidirectional overcurrent limiting device formed on both the front and rear faces of a semiconductor substrate is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a two-terminal type overcurrent limiting semiconductor device for protecting an electric load connected in series from being destroyed by an overcurrent flowing through the electric load. .

[0002]

2. Description of the Related Art Conventionally, there is a method in which a circuit breaker is connected in series to cut off an overcurrent when an overcurrent flows to an electric load and is destroyed. The breaker must be operated in a short time, and the shape is too large to be mounted on an integrated circuit.

[0003] An overcurrent limiting type semiconductor device combining semiconductor devices has been devised for application to an integrated circuit.
In such an overcurrent limiting type semiconductor device, means for detecting a voltage drop due to an overcurrent and shutting off with a gate voltage when the overcurrent flows is used. As an example of this, FIG. 11 shows an equivalent circuit of the overcurrent limiting semiconductor element.
Since the depletion type MOS field effect transistor is used, the gate electrode needs to be protected from overvoltage, and there is a problem that it is difficult to increase the breakdown voltage between the source and the drain.

The overcurrent limiting circuit has three field effect transistors and a Zener diode as shown in an equivalent circuit of an overcurrent limiting semiconductor device in FIG. 11, and the number of circuit components is small. It is large, the circuit is complicated, the burden is high economically, and it is difficult to reduce the size of the device.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and has as its object to be able to be monolithically formed on the same semiconductor substrate and to use a depletion type MOS type with two terminals. The circuit configuration does not use a transistor, and a high breakdown voltage can be achieved. When a predetermined current flows through the current-limiting semiconductor device of the present invention, the impedance of the device increases, and Overcurrent limiting type semiconductor element for protecting any electrical load connected in series with the type semiconductor element.

Further, an overcurrent limiting type semiconductor which can be formed on the same substrate so as to protect a certain electric load by restricting a predetermined current from flowing even in a bidirectional overcurrent. An element can be provided.

[0007]

SUMMARY OF THE INVENTION In order to achieve the above-mentioned object, the invention according to the present invention is directed to an electrostatic induction transistor of a first conductivity type and a junction field-effect transistor of a second conductivity type which are arranged and connected in series. I have.

The source electrode of the second conductivity type junction field effect transistor is connected to the source electrode of the first conductivity type static induction transistor, and the anode electrode is connected to the gate electrode of the second conductivity type junction field effect transistor. The cathode electrode is connected to the drain electrode of the conduction type static induction transistor, the cathode electrode is connected to the gate electrode of the first conduction type electrostatic induction transistor and the drain electrode of the second conduction type junction field effect transistor, and the anode electrode and the cathode electrode are connected to each other. A semiconductor element as a terminal is formed.

The two transistors are formed on the surface of one silicon substrate, and the back surface is used as the drain electrode of the first conductivity type static induction transistor and the gate electrode of the second conductivity type junction field effect transistor.

A floating region is provided between the source electrode and the drain electrode of the junction field effect transistor of the second conductivity type, and the current flowing through the junction field effect transistor of the second conductivity type is suppressed and cut off by the gate voltage. The gate voltage of the first-conduction-type static induction transistor can be raised to a threshold value or higher, and the current flowing through the first-conduction-type static induction transistor can be cut off.

The current to be cut off can be controlled by controlling the depth of the floating region. When the current exceeds a certain level, the overcurrent is rapidly suppressed and cut off. The effect of preventing increases.

Since the first conductivity type static induction transistor has a vertical structure, it can be a high-voltage field-effect transistor that can withstand high voltages and can cut off current.

Since a depletion type MOS field effect transistor is not used in the manufacturing process of the overcurrent control type semiconductor device of the present invention, a high breakdown voltage can be obtained.

In the embodiment of the present invention, the silicon semiconductor substrate has an n-type conductivity type. However, the same effect can be obtained even when the first conductivity type n-type and the second conductivity type p-type are all replaced with the opposite conductivity types. Is apparently obtained.

In order to further reduce the on-resistance, a region of the opposite conductivity type to the bulk is provided on the anode electrode side of the static induction transistor, or a junction type field effect is formed on the epitaxial layer having a low impurity concentration by using a substrate having a high impurity concentration. Obviously, it is effective to provide a transistor and a static induction transistor, and both can be used in combination.

Since the two transistors are formed on the same substrate and share an anode electrode and a gate electrode and a cathode electrode and a gate electrode, respectively, there are effects such as downsizing and no increase in size of the device. Further, since the diffusion can be performed in the same step, there is an effect that the manufacturing cost can be reduced.

Further, by connecting the overcurrent limiting element in anti-series, it is possible to limit overcurrent with respect to bidirectional current. In this case, the drain electrode of the static induction transistor and the junction field effect transistor By forming an element on the front and back surfaces of the substrate by using a common gate electrode in the substrate, diffusion can be performed in the same step, so that the production cost can be reduced.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an overcurrent limiting type semiconductor device according to the present invention will be described below with reference to the accompanying drawings. In the description of the drawings, the same members are given the same reference numerals,
Duplicate description will be omitted.

FIG. 1 shows an example of an embodiment of the present invention, and FIG. 1 is a monolithic sectional structure diagram thereof. In this sectional structure, the portion A indicates the n-channel electrostatic induction transistor 10, and the portion B indicates the p-channel junction field effect transistor 20.

As shown in FIG. 1, wiring is connected to each of the electrodes. Reference numeral 1 denotes an anode, reference numeral 2 denotes a cathode, and the overall configuration is a two-terminal overcurrent blocking semiconductor device. .

FIG. 2 shows an equivalent circuit of the embodiment shown in FIG.
The channel junction field-effect transistor 20 is connected in series, the source electrode 11 of the n-channel electrostatic induction transistor 10 and the source electrode 21 of the p-channel junction field-effect transistor 20 are connected, and the anode electrode 1 is connected to the n-channel electrostatic induction transistor 10. Is connected to the gate electrode 23 of the p-channel junction field effect transistor. The cathode electrode 2 is connected to the gate electrode 13 of the n-channel electrostatic induction transistor 10 and the drain electrode 22 of the p-channel junction field effect transistor 20.

P-channel junction field effect transistor 20
The n-channel electrostatic induction transistor 10 is on when the gate-source voltage is zero, and the current flows until the gate-source voltage exceeds the threshold. The n-channel electrostatic induction transistor 10 has a gate threshold in a negative region.
A non-conductive off state is established between the 2-source 11 and a high breakdown voltage can be maintained due to the vertical structure.

P-channel junction field effect transistor 20
Has a floating region 25, and reduces the width of the channel 24 with an increase in the potential of the anode 1, that is, an increase in the voltage of the gate 23 of the p-channel junction field effect transistor.
Since the current stops flowing, the potential at the node 3 between the two transistors rises to a value approaching the potential of the anode 1. At the same time, the potential of the node 3 is applied as a negative voltage between the gate 13 and the source 11 of the n-channel static induction transistor 10.

When the potential of the node 3 rises and the voltage between the gate 13 and the source 11 of the n-channel electrostatic induction transistor 10 exceeds a threshold value, the n-channel electrostatic induction transistor 1
0 enters an off operation, and a voltage is applied to the voltage between the gate 13 and the source 11 of the n-channel electrostatic induction transistor 10 so that the voltage of the node 3 is maintained. And the current is cut off.

Since the potential of the node 3 is saturated by the operation of the n-channel static induction transistor 10, the drain 22-source 21 of the p-channel junction field effect transistor 20
A constant voltage is applied between them.

The operation of the n-channel static induction transistor 10 suppresses the node 3 to a constant potential. However, even when the potential further rises, the potential between the gate and source of the p-channel junction field effect transistor is lower than that of the MOS field effect transistor. Has a sufficient withstand voltage, and the voltage applied to the overcurrent limiting semiconductor device is n-channel electrostatic induction transistor 1.
0 mainly shares the breakdown voltage.

P-channel junction field effect transistor 20
Region 2 between source 21 and drain 22
By adjusting the depth of 5 and reducing the width of the channel
The two-terminal overcurrent limiting type semiconductor device is sensitive to the anode voltage 1. When a current flows through the overcurrent limiting semiconductor device, the voltage drop by the p-channel junction field-effect transistor 20 becomes a negative bias and is applied between the gate 13 and the source 11 of the n-channel electrostatic induction transistor 10,
When the voltage between the gate 13 and the source 11 reaches the threshold, n
The drain current of the channel static induction transistor 10 is limited, and the current flowing through the device is cut off.

FIG. 3 shows a schematic diagram of the voltage-current characteristics of the overcurrent cutoff semiconductor device. In order to cut off the current and turn off the overcurrent limiting type semiconductor element, it is effective to make the floating region 25 deep.

FIGS. 4, 5 and 6 show an embodiment for reducing the on-resistance. FIG. 4 shows a case where a conductive type region opposite to the bulk is provided on the anode side of the electrostatic induction transistor. FIG. 5 shows a case in which a region having a high impurity concentration is provided on the substrate, and FIG. 6 shows a combination of FIG. 4 and FIG.

Further, the overcurrent limiting element limits the current in one direction. By connecting this element in anti-series, it is possible to limit the overcurrent in both directions. FIG. 7 is a cross-sectional structural view, and FIG. 8 is an equivalent circuit diagram thereof. By forming the element on the front and back surfaces of the same semiconductor substrate as shown in FIG. 7, a small-sized element capable of limiting bidirectional overcurrent can be provided, and the diffusion step can be performed at the same time, so that the cost can be reduced. As shown in FIG. 9, using a semiconductor with a high impurity concentration for the substrate reduces on-resistance.

FIG. 10 is a schematic diagram of the voltage-current characteristics of the overcurrent cutoff semiconductor device, which has the effect of blocking current for bidirectional overcurrent.

This embodiment is merely an example, and it is apparent that a structure in which the n-type and p-type conductivity types are reversed has a similar effect.

[0033]

According to the present invention, an n-channel electrostatic induction transistor 10 and a p-channel junction field effect transistor 20 are connected in series in a monolithic configuration on one substrate, and when an overcurrent flows, a p-channel junction field effect transistor is formed. 2
A two-terminal overcurrent limiting semiconductor that cuts off overcurrent by applying a voltage rise generated by the control of the gate 23 of 0 to the source 11 of the n-channel electrostatic induction transistor 10 and making the gate 13 substantially a negative voltage. An element can be provided. Moreover, it is possible to form a reverse bi-directional semiconductor device using the front and back surfaces of the same semiconductor substrate, thereby providing a bidirectional overcurrent limiting semiconductor device.

[0034]

[Brief description of the drawings]

FIG. 1 is a structural sectional view of an example showing an embodiment of the present invention.

FIG. 2 is a diagram showing an equivalent circuit of the embodiment of the present invention.

FIG. 3 is a schematic diagram of voltage-current characteristics of an overcurrent limiting semiconductor device of the present invention.

FIG. 4 is an embodiment in which the ON resistance of the overcurrent limiting type semiconductor device of the present invention is reduced.

FIG. 5 is an embodiment in which the ON resistance of the overcurrent limiting type semiconductor device of the present invention is reduced.

FIG. 6 is an embodiment in which the ON resistance of the overcurrent limiting type semiconductor device of the present invention is reduced.

FIG. 7 is a structural sectional view of an embodiment showing a bidirectional overcurrent limiting semiconductor device of the present invention.

FIG. 8 is a diagram showing an equivalent circuit of the bidirectional overcurrent limiting type semiconductor device of the present invention.

FIG. 9 is an embodiment in which the on-resistance of the bidirectional overcurrent limiting semiconductor device of the present invention is reduced.

FIG. 10 is a schematic diagram of a voltage-current characteristic of a bidirectional overcurrent limiting semiconductor device of the present invention.

FIG. 11 is a diagram showing an equivalent circuit of a conventional overcurrent limiting semiconductor device.

[Explanation of symbols]

Anode cathode node 10, first conductivity type static induction transistor 11, source of first conductivity type static induction transistor 12, drain of first conductivity type static induction transistor 13, gate of first conductivity type static induction transistor 20 A junction field effect transistor 21 of the second conductivity type; a source 22 of the junction field effect transistor of the second conductivity type; a drain 23 of the junction field effect transistor of the second conductivity type; a gate 24 of the junction field effect transistor of the second conductivity type; Layer 25 of type junction field effect transistor, floating region of junction field effect transistor of second conductivity type

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/812 H03K 17/56 Z H02H 9/02 H03K 17/56 (72) Inventor Masaya Shirota Hanno, Saitama F-term (reference) 10-13 Shindengen Kogyo Co., Ltd., Shindengen Kogyo Co., Ltd.F5 term (reference)

Claims (8)

[Claims] 1. A semiconductor device having a first conductivity type static induction transistor and a second conductivity type junction field effect transistor, wherein the two transistors are arranged in series, and a drain of the static induction transistor is connected to the junction field effect transistor. The anode electrode of the overcurrent limiting semiconductor element is formed in common with the gate electrode, and the source electrode of the junction field effect transistor and the source electrode of the static induction transistor are connected to each other. An overcurrent limiting semiconductor device comprising a semiconductor device having two terminals as a whole, the cathode being connected to a drain electrode of a transistor and forming a cathode electrode of the overcurrent limiting semiconductor device. 2. The overcurrent limiting type semiconductor according to claim 1, wherein the first conductive type static induction transistor and the second conductive type junction field effect transistor are formed on the first conductive type semiconductor substrate. Overcurrent limiting type semiconductor device. 3. The overcurrent limiting semiconductor device according to claim 1, wherein the first conductivity type static induction transistor and the second conductivity type junction field effect transistor are formed on one surface of the substrate and the other surface is an anode electrode. An overcurrent limiting semiconductor device, characterized in that: 4. The overcurrent limiting semiconductor device according to claim 1, wherein the second conductivity type junction field effect transistor is a first conductive type junction field effect transistor.
An overcurrent limiting semiconductor device comprising a conductive floating region. 5. The overcurrent limiting semiconductor device according to claim 1, wherein the current is limited by both the static induction transistor and the junction field effect transistor. 6. An overcurrent limiting semiconductor device according to claim 1, wherein said overcurrent limiting semiconductor device comprises an inverted conductive semiconductor. 7. An overcurrent limiting semiconductor device according to claim 1, wherein the overcurrent limiting semiconductor device according to claim 1 is arranged in anti-series to limit a bidirectional overcurrent. An overcurrent limiting type semiconductor device characterized by the above-mentioned. 8. The overcurrent limiting type semiconductor device according to claim 7, wherein the anode electrode is common inside the semiconductor substrate, and
An overcurrent limiting semiconductor device comprising: two overcurrent limiting semiconductor devices arranged on both front and back surfaces of a semiconductor substrate of the same conductivity type to limit bidirectional overcurrent.