JP2022084984A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device including an electrostatic protection circuit where a parasitic PNP transistor structure is not formed.SOLUTION: A semiconductor device includes an electrostatic protection circuit. The electrostatic protection circuit includes an Nch enhancement type MOS transistor. The Nch enhancement type MOS transistor is an off transistor in which a gate, an N-type high concentration source region, and a P-type high concentration base region are grounded to a ground potential. An N-type high concentration drain region of the Nch enhancement type MOS transistor is connected to an N-type region of a polysilicon diode formed on a field oxide film and a P-type region of the polysilicon is connected to a signal input terminal.SELECTED DRAWING: Figure 2

Description

The present invention relates to a semiconductor device having an electrostatic protection circuit.

As an electrostatic protection element that can protect the signal input side terminal when reversely connected, a P-type diode on the signal input terminal side formed in the Nwell in the P-type substrate and a P on the ground terminal side formed in the same Nwell. A PNP bidirectional diode composed of a type diode is used. In this electrostatic protection element, when the voltage becomes equal to or lower than the ground potential due to the signal input terminal being reversely connected, the P-type diode on the signal input terminal side is applied in the opposite direction, so that no current flows. (See Patent Document 1)

JP-A-2014-143378

There is a semiconductor vertical parasitic PNP transistor composed of a P-type high concentration region of a P-type diode on the signal input terminal side, Nwell, and a P-type substrate, and Nwell has an OPEN potential (floating). In this configuration, when a positive voltage is applied to the signal input terminal, a forward current flows between the P-type high-concentration region connected to the signal input terminal and Nwell, and the Nwell voltage is lower than the P-type high-concentration region, and the parasitic PNP. Transistors cause bipolar operation and significantly increase the current consumption of semiconductor devices.

This parasitic PNP transistor can fix the voltage to the same voltage as the P-type high concentration region by connecting the potential of Nwell to the signal input terminal, for example, so that bipolar operation does not occur, but this structure has the signal input terminal connected in reverse. When this is done, a forward current is passed between Nwell and the P-type substrate, which is directly connected to the signal input terminal, without passing through the P-type region (anode) of the P-type diode on the signal input terminal side to which the voltage in the opposite direction is applied. It does not meet the original purpose of protection at the time of reverse connection.
When the PNP bidirectional diode is used as described above, it is necessary to set the Nwell to an open potential, but the current consumption may be significantly increased due to the bipolar operation.

Off-transistor that is used in the off state by grounding the well, source and gate of the Nch enhanced MOS transistor to the ground potential, and for protection at the time of reverse connection, the N-type part is on the off-transistor drain side and the P-type part is the input terminal. The circuit configuration was such that a polysilicon diode formed on a thick oxide film was inserted so as to be on the side.

By using this structure, when a positive voltage is applied to the signal input terminal, a voltage is applied to the Nch type off-transistor via the forward direction of the polysilicon diode, and normal off-tarranger operation is performed to function as a protection element. When a negative voltage is applied to the signal input terminal during reverse connection, the voltage applied to the polysilicon diode is in the opposite direction, so that the current can be limited. In addition, since the parasitic PNP transistor structure consisting of the P-type high-concentration region, Nwell, and P-type substrate, which has been a problem, is not formed, it is possible to avoid an increase in current consumption when a positive voltage is applied to the signal input terminal, and the off-transistor can be used. It is possible to have a considerable leakage current.

Regarding the voltage-current characteristics after breakdown, the PNP bidirectional diode keeps rising until it breaks, but in the case of an off-transistor, it snaps back at the voltage before the break and shifts to low voltage operation. .. For this reason, there is a risk that the PNP bidirectional diode will not be able to protect against the breakdown voltage of the protected element when an overcurrent is applied from the outside, but in the case of an off-transistor, the snapback voltage is set low by design. Therefore, the protection of the protected element can be enhanced.

Further, since the off-transistor after snapback operates with low resistance, it is possible to escape the same surge in a smaller area than the conventional PNP transistor structure.

Equivalent circuit diagram of a semiconductor device having an electrostatic protection circuit according to an embodiment of the present invention. Schematic cross-sectional view of a semiconductor device having an electrostatic protection circuit according to an embodiment of the present invention. Equivalent circuit diagram of a semiconductor device having an electrostatic protection circuit having a conventional structure Schematic cross-sectional view of a semiconductor device having an electrostatic protection circuit having a conventional structure

A semiconductor device having an electrostatic protection circuit according to an embodiment of the present invention will be described.
FIG. 1 is an equivalent circuit diagram of a semiconductor device having an electrostatic protection circuit according to an embodiment of the present invention. As an example, an off-transistor 1 that is used in an off state by grounding the well, source, and gate of an Nch-enhanced MOS transistor (hereinafter referred to as NchMOS transistor) to the ground potential, and an N-type portion on the off-transistor drain side and a P-type portion. The part of the electrostatic protection circuit having the diode 2 inserted so as to be on the input terminal side is shown as an equivalent circuit diagram.

FIG. 2 shows a schematic cross-sectional view of the electrostatic protection circuit of FIG. 1 as an example of the electrostatic protection circuit according to the embodiment of the present invention. A P-type low-concentration well region 4, which is a well region of an NchMOS transistor, is formed on a silicon substrate 3 having a P-type conductive type.
A field oxide film 5 for element separation is provided on the silicon substrate. A gate oxide film 6 is provided in a region where the field oxide film 5 is not formed, and an NchMOS transistor channel region 7 is formed below the gate oxide film 6.

A gate electrode 8 made of polysilicon is provided on the gate oxide film 6, and a source region 9 and an N-type high concentration, which are N-type high-concentration impurity diffusion regions, are provided on the surface of the semiconductor substrate adjacent to the gate electrode 8. The drain region 10 which is the impurity diffusion region of the above is provided so as to sandwich the NchMOS transistor channel region 7. Further, a base region 11 which is a P-type high-concentration impurity diffusion region for taking the voltage of the P-type low-concentration well region 4 is provided on the surface of the semiconductor substrate at a location not adjacent to the gate electrode 8 but at a distance.
The N-type high-concentration source region 9, the gate electrode 8, and the P-type high-concentration base region 11 are grounded by metal wiring so as to have a ground potential.

The field oxide film 5 is composed of a polysilicon diode N-type high-concentration region 12, a polysilicon diode N-type low-concentration region 13, a polysilicon diode P-type low-concentration region 14, and a polysilicon diode P-type high-concentration region 15. A polysilicon diode is provided, and the polysilicon diode N-type low concentration region 13 is in the polysilicon diode N-type high-concentration region 12, and the polysilicon diode P-type low-concentration region 14 is in the polysilicon diode N-type low-concentration region 13. The polysilicon diode P-type high concentration region 15 is provided adjacent to the polysilicon diode P-type low concentration region 14.

The N-type high-concentration region 12 which is the cathode of the polysilicon diode is connected to the N-type high-concentration drain region 10 by metal wiring, and the P-type high-concentration region 15 which is the anode of the polysilicon diode is connected to the signal input terminal. ing.
As described above, the circuit shown in FIG. 1 can be realized by configuring the NchMOS transistor 1 and the polysilicon diode 2. Although the method of configuring the diode 2 is not shown in FIG. 1, as described with reference to FIG. 2, the diode 2 is a diode made of polysilicon provided on the field oxide film 5, and thus silicon. Since the parasitic PNP transistor structure is not formed inside the substrate 3, it is possible to avoid an increase in current consumption when a positive voltage is applied to the signal input terminal, and it is possible to make the current equivalent to the leakage current of the off-transistor. Is.

Further, when a negative voltage is applied to the signal input terminal at the time of reverse connection, the voltage applied to the polysilicon diode is in the opposite direction, so that the current can be limited.

Regarding the voltage-current characteristics after breakdown, the PNP bidirectional diode keeps increasing the current when the voltage rises, but the off-transistor causes snapback and operates at a constant voltage. Therefore, the protection of the protected element can be enhanced by setting the voltage that causes snapback lower than the breakdown voltage of the PNP bidirectional diode with respect to the breakdown voltage of the protected element.

Further, since the off-transistor after snapback operates with low resistance, it is possible to escape the same surge in a smaller area than the conventional PNP transistor structure.

1 Nch enhanced MOS transistor 2 Polysilicon diode 3 P type conductive semiconductor substrate 4 P type low concentration well region 5 Field oxide film 6 Gate oxide film 7 Channel region 8 Polysilicon gate 9 N type high concentration source region 10 N type high Concentration drain region 11 P-type high-concentration base region 12 Polysilicon diode N-type high-concentration region 13 Polysilicon diode N-type low-concentration region 14 Polysilicon diode P-type low-concentration region 15 Polysilicon diode P-type high-concentration region 16 Ground terminal side P-type diode 17 Signal input terminal side P-type diode 18 N-type low-concentration well region 19 Ground terminal side P-type diode P-type high-concentration region 20 Signal input terminal-side P-type diode P-type high-concentration region 21 P-type high-concentration region

Claims (2)

In a semiconductor device in which an electrostatic protection circuit is connected to a signal input terminal
The electrostatic protection circuit is
Nch enhanced MOS transistors with wells, sources and gates grounded to ground potential,
The polysilicon diode formed on the oxide film and
Have,
A semiconductor device characterized in that the drain of the Nch enhanced MOS transistor is connected to the N-type region of the polysilicon diode, and the P-type region of the polysilicon diode is connected to the signal input terminal. The PN junction region of the polysilicon diode is
From the P-type polysilicon having a concentration lower than the P-type high-concentration region of the polysilicon diode connected to the signal input terminal and from the N-type high-concentration region of the polysilicon diode connected to the drain of the Nch enhanced transistor. A semiconductor device characterized by being composed of low-concentration N-type polysilicon.

Images