CN114678853B - CDM ESD protection circuit - Google Patents

CDM ESD protection circuit Download PDF

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Publication number
CN114678853B
CN114678853B CN202210597525.2A CN202210597525A CN114678853B CN 114678853 B CN114678853 B CN 114678853B CN 202210597525 A CN202210597525 A CN 202210597525A CN 114678853 B CN114678853 B CN 114678853B
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circuit
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protection
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unit
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CN114678853A (en
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杨耕
戴佼容
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Xinyaohui Technology Co ltd
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Xinyaohui Technology Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
    • H02H9/025—Current limitation using field effect transistors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The application provides a CDM ESD protection circuit, which comprises a first sub-circuit, a second sub-circuit, a first protection sub-circuit and a second protection sub-circuit, wherein the first sub-circuit is respectively and electrically connected with an output circuit and the second sub-circuit, the second sub-circuit comprises at least one input stage unit, the input stage unit is electrically connected with the output circuit and a first voltage line, the first protection sub-circuit is connected with the input stage unit in series, the second protection sub-circuit is arranged in parallel with the input stage unit, the second sub-circuit is electrically connected with the first voltage line, and when positive ESD is generated between the output circuit and the first voltage line, the first protection sub-circuit is used for protecting the input stage unit; when negative ESD is generated between the output circuit and the first voltage line, the second protection sub-circuit is used for protecting the input stage unit. The first protection sub-circuit enables the breakdown voltage of the input stage unit to be obviously improved compared with a single-pole input structure; the second protection sub-circuit causes the gate oxide differential voltage of the input stage cell to clamp to a lower level.

Description

CDM ESD protection circuit
Technical Field
The application relates to the technical field of electrostatic discharge protection circuits, in particular to a CDM ESD protection circuit.
Background
With the development of integrated circuits, the performance of chips is getting better and better by adopting an advanced Fin-Field-Effect Transistor (FinFET) nano-scale process. However, as the process advances, the gate of the transistor becomes thinner and thinner, and therefore, the chip has a weaker and weaker ability to withstand electrostatic discharge (ESD), especially ESD protection for Charged Device Model (CDM).
In the prior art, a CDM ESD protection circuit is only limited to positive ESD or negative ESD and cannot be realized simultaneously.
Disclosure of Invention
The application discloses a CDM ESD protection circuit, which can solve the technical problem that the CDM ESD protection circuit cannot be simultaneously realized when positive or negative electrostatic discharge occurs.
The application provides a CDM ESD protection circuit, CDM ESD protection circuit includes first sub-circuit, second sub-circuit, first protection sub-circuit and second protection sub-circuit, output circuit and the second sub-circuit are connected to first sub-circuit electricity respectively, the second sub-circuit includes at least one input stage unit, the input stage unit respectively with output circuit and the first voltage line electricity is connected, first protection sub-circuit with the input stage unit sets up in series, the second protection sub-circuit with the input stage unit sets up in parallel, the first voltage line is connected to the second sub-circuit electricity, when producing forward ESD between output circuit and the first voltage line, first protection sub-circuit is used for protecting the input stage unit; when negative ESD is generated between the output circuit and the first voltage line, the second protection sub-circuit is used for protecting the input stage unit.
When positive ESD is generated between the output circuit and the first voltage line, the first protection sub-circuit is arranged in series with the input stage unit, so that the breakdown voltage of the input stage unit is obviously improved compared with a single-pole input structure, and the ESD voltage is prevented from breaking down the input stage unit; when negative ESD is generated between the output circuit and the first voltage line, the second protection sub-circuit is connected with the input stage unit in parallel, so that the grid oxide layer voltage difference of the input stage unit is clamped to a lower level, and the ESD voltage is prevented from breaking down the input stage unit.
Optionally, the gate of the first protection sub-circuit is configured to receive a scan signal, the scan signal is configured to control on/off of the first protection sub-circuit, the drain of the first protection sub-circuit is electrically connected to the input stage unit, the source of the first protection sub-circuit is electrically connected to the first voltage line, and the substrate of the first protection sub-circuit is electrically connected to the first voltage line.
Optionally, when a forward ESD is generated between the output circuit and the first voltage line, a drain junction breakdown voltage of the second protection sub-circuit is smaller than a sum of a gate oxide layer breakdown voltage of the input stage unit and a source-drain channel breakdown voltage of the first protection sub-circuit.
Optionally, a gate of the second protection sub-circuit is electrically connected to the first voltage line, a drain of the second protection sub-circuit is electrically connected to the output circuit, a source of the second protection sub-circuit is electrically connected to the first voltage line, and a substrate of the second protection sub-circuit is electrically connected to the first voltage line.
Optionally, a parasitic diode and a parasitic resistor are formed between the source and the drain of the second protection sub-circuit and the substrate.
Optionally, when negative ESD is generated between the output circuit and the first voltage line, a sum of a parasitic diode voltage of the second protection sub-circuit and a parasitic resistance voltage of the second protection sub-circuit is smaller than a gate oxide breakdown voltage of the input stage unit.
Optionally, the CDM ESD protection circuit further comprises a clamp sub-circuit, the first sub-circuit is further electrically connected to a second voltage line, and the first voltage line and the second voltage line are electrically connected through the clamp sub-circuit.
Optionally, the CDM ESD protection circuit further comprises a resistive sub-circuit, and the second sub-circuit is electrically connected to the output circuit through the resistive sub-circuit.
Optionally, the first sub-circuit includes at least one first pull-up unit and at least one pull-down unit, a source of the first pull-up unit is electrically connected to the third voltage line, a drain of the first pull-up unit is electrically connected to the output circuit, a source of the pull-down unit is electrically connected to the second voltage line, and a drain of the pull-down unit is electrically connected to the output circuit; the second sub-circuit further comprises at least one second pull-up unit, wherein a source electrode of the second pull-up unit is electrically connected with a fourth voltage line, a drain electrode of the second pull-up unit is electrically connected with a drain electrode of the input stage unit, and a grid electrode of the second pull-up unit is electrically connected with a grid electrode of the input stage unit.
Optionally, the first pull-up unit and the second pull-up unit are PMOS, and the pull-down unit, the input stage unit, the first protection sub-circuit and the second protection sub-circuit are NMOS.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for a person skilled in the art to obtain other drawings based on the drawings without any inventive exercise.
Fig. 1 is a block diagram of a CDM ESD protection circuit according to an embodiment of the present application.
Fig. 2 is a schematic diagram of a CDM ESD protection circuit according to an embodiment of the present application.
Fig. 3 is a schematic diagram of a voltage-current relationship of a second protection sub-circuit according to an embodiment of the present disclosure.
Fig. 4 is a schematic cross-sectional view of a second protection sub-circuit according to an embodiment of the present disclosure.
Fig. 5 is a schematic cross-sectional view of a PMOS device according to an embodiment of the present disclosure.
Fig. 6 is a schematic cross-sectional view of an NMOS provided in an embodiment of the present application.
The reference numbers illustrate: CDM ESD protection circuit-1, first sub-circuit-11, first pull-up unit-111, pull-down unit-112, second sub-circuit-12, input stage unit-121, second pull-up unit-122, first protection sub-circuit-13, second protection sub-circuit-14, parasitic diode-141, parasitic resistor-142, clamp sub-circuit-15, resistor sub-circuit-16, output circuit-PAD, first voltage line-AVSS, second voltage line-VSS, third voltage line-VDD, fourth voltage line-AVDD, scan signal-G, gate-G, drain-d, source-s, substrate-b.
Detailed Description
The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments obtained by a person of ordinary skill in the art without any inventive work based on the embodiments in the present application are within the scope of protection of the present application.
Please refer to fig. 1, wherein fig. 1 is a schematic diagram of a CDM ESD protection circuit 1 according to an embodiment of the present disclosure. The CDM ESD protection circuit 1 includes a first sub-circuit 11, a second sub-circuit 12, a first protection sub-circuit 13, and a second protection sub-circuit 14, wherein the first sub-circuit 11 is electrically connected to an output circuit PAD and the second sub-circuit 12, the second sub-circuit 12 includes at least one input stage unit 121, the input stage unit 121 is electrically connected to the output circuit PAD and the first voltage line AVSS, the first protection sub-circuit 13 is connected in series to the input stage unit 121, the second protection sub-circuit 14 is connected in parallel to the input stage unit 121, the second sub-circuit 12 is electrically connected to the first voltage line AVSS, and when a forward ESD is generated between the output circuit PAD and the first voltage line AVSS, the first protection sub-circuit 13 is configured to protect the input stage unit 121; when negative ESD is generated between the output circuit PAD and the first voltage line AVSS, the second protection sub-circuit 14 is used for protecting the input stage unit 121.
The CDM means a model in which the first sub-circuit 11 and the second sub-circuit 12 may be integrated circuit chips, and when the housings of the first sub-circuit 11 and the second sub-circuit 12 are frictionally charged with the outside or the first sub-circuit 11 and the second sub-circuit 12 are charged, the first sub-circuit 11 or the second sub-circuit 12 itself is charged. At this time, the first sub-circuit 11 or the second sub-circuit 12 may discharge static electricity to a lower potential, or a higher potential may discharge static electricity to the first sub-circuit 11 or the second sub-circuit 12, that is, positive ESD and negative ESD.
In this embodiment, the output circuit PAD may be an input/output pin of a chip, and the discharge of the static electricity from the output circuit PAD to the first voltage line AVSS is referred to as positive ESD, and the discharge of the static electricity from the first voltage line AVSS to the output circuit PAD is referred to as negative ESD.
Specifically, when the output circuit PAD discharges static electricity to the first voltage line AVSS, since the first protection sub-circuit 13 is connected in series with the input stage unit 121, a current is transmitted to the first voltage line AVSS through the input stage unit 121 and the first protection sub-circuit 13, that is, the first protection sub-circuit 13 and the input stage unit 121 divide the voltage, thereby reducing the risk of breakdown of the input stage unit 121 by the discharged static electricity current; when the output circuit PAD discharges static electricity to the first voltage line AVSS, since the first protection sub-circuit 13 is connected in series with the input stage unit 121, a current is discharged to the first voltage line AVSS through the input stage unit 121 and the first protection sub-circuit 13, that is, the first protection sub-circuit 13 and the input stage unit 121 divide the voltage, thereby reducing the risk of breakdown of the input stage unit 121 by the discharged static electricity current, and at the same time, the static electricity current is also discharged to the first voltage line AVSS through the second protection sub-circuit 14;
when the first voltage line AVSS discharges static electricity to the output circuit PAD, because the second protection sub-circuit 14 is connected in parallel to the input stage unit 121, the second protection sub-circuit 14 and the input stage unit 121 shunt electricity, so as to reduce the static current discharged from the input stage unit 121, and further clamp the gate g oxide voltage difference of the input stage unit 121 to a lower level, thereby reducing the risk of breakdown of the input stage unit 121 by the discharged static current.
It is understood that, in the present embodiment, when the ESD in the forward direction is generated between the output circuit PAD and the first voltage line AVSS, the first protection sub-circuit 13 is disposed in series with the input stage unit 121, so that the breakdown voltage of the input stage unit 121 is significantly increased compared to the unipolar input structure, thereby preventing the ESD voltage from breaking down the input stage unit 121; when negative ESD is generated between the output circuit PAD and the first voltage line AVSS, the second protection sub-circuit 14 is connected in parallel to the input stage unit 121, so that the gate g-oxide voltage difference of the input stage unit 121 is clamped to a lower level, thereby preventing ESD voltage from breaking down the input stage unit 121.
In one possible implementation, please refer to fig. 2, wherein fig. 2 is a schematic diagram of a CDM ESD protection circuit according to an embodiment of the present disclosure. The gate G of the first protection sub-circuit 13 is configured to receive a scan signal G, the scan signal G is configured to control on/off of the first protection sub-circuit 13, the drain d of the first protection sub-circuit 13 is electrically connected to the input stage unit 121, the source s of the first protection sub-circuit 13 is electrically connected to the first voltage line AVSS, and the substrate b of the first protection sub-circuit 13 is electrically connected to the first voltage line AVSS.
It should be noted that, when the first protection sub-circuit 13 is turned on under the loading of the scan signal G, the source s and the drain d of the first protection sub-circuit 13 form a source-drain channel under the loading of the scan signal G. Normally, the substrate b of the transistor is grounded in a circuit or used to receive a power supply voltage to normally operate.
In this embodiment, when the electrostatic current is released from the output circuit PAD to the first voltage line AVSS, the electrostatic current needs to pass through the gate g oxide layer of the input stage unit 121 and the source-drain channel formed by the source s and the drain d of the first protection sub-circuit 13, and it can be understood that the breakdown voltage of the input stage series structure is significantly improved compared to the unipolar input structure.
In this embodiment, the first protection sub-circuit 13 is a transistor, and it is understood that in other possible embodiments, the first protection sub-circuit 13 may also be other types of electronic components, which is not limited in this application.
In one possible implementation, when the forward ESD is generated between the output circuit PAD and the first voltage line AVSS, the drain-body junction breakdown voltage of the second protection sub-circuit 14 is smaller than the sum of the gate g-oxide breakdown voltage of the input stage unit 121 and the source-drain channel breakdown voltage of the first protection sub-circuit 13.
It should be noted that, when a transistor is manufactured by a more advanced technology process, such as a FinFET nano-scale process, the gate g oxide breakdown voltage of the input stage unit 121 is usually 3V. The drain junction of the second protection sub-circuit 14 refers to a semiconductor junction formed between the drain d terminal of the second protection sub-circuit 14 and the substrate b, and when a voltage difference between the drain junctions of the second protection sub-circuits 14 is greater than a certain threshold, the drain junction of the second protection sub-circuit 14 is turned on, that is, the drain d terminal of the second protection sub-circuit 14 is turned on with the substrate b. In this embodiment, the drain-to-body junction breakdown voltage of the second protection sub-circuit 14 is 3.5V.
Specifically, referring to fig. 3, fig. 3 is a schematic diagram of a voltage-current relationship of a second protection sub-circuit according to an embodiment of the present application. The first protection sub-circuit 13 is connected in series with the input stage unit 121, and then the voltage of the source s of the input stage unit 121 is clamped to 2-3V, since the drain d of the first protection sub-circuit 13 is electrically connected to the source s of the input stage unit 121, and the source s of the first protection sub-circuit 13 is electrically connected to the first voltage line AVSS, that is, the voltage difference between the source and drain channels of the first protection sub-circuit 13 is equal to the voltage of the source s of the input stage unit 121. As shown in fig. 3, Vt is a drain-body junction breakdown voltage of the second protection sub-circuit 14, Vb is a gate g-oxide breakdown voltage of the input stage unit 121, and Vbx is a sum of the gate g-oxide breakdown voltage of the input stage unit 121 and a source-drain channel breakdown voltage of the first protection sub-circuit 13.
The minimum value of the source s voltage of the input stage unit 121 is taken, that is, 2V, and the sum of the gate g oxide layer breakdown voltage of the input stage unit 121 and the source drain channel breakdown voltage of the first protection sub-circuit 13 is 5V. As the drain junction breakdown voltage of the second protection sub-circuit 14 is 3.5V, that is, the electrostatic current first breaks down the drain junction of the second protection sub-circuit 14, and the drain junction of the second protection sub-circuit 14 releases the electrostatic current, thereby achieving the purpose of protecting the input stage unit 121.
In one possible implementation, referring to fig. 2 again, the gate g of the second protection sub-circuit 14 is electrically connected to the first voltage line AVSS, the drain d of the second protection sub-circuit 14 is electrically connected to the output circuit PAD, the source s of the second protection sub-circuit 14 is electrically connected to the first voltage line AVSS, and the substrate b of the second protection sub-circuit 14 is electrically connected to the first voltage line AVSS.
In this embodiment, the first voltage line AVSS is used for transmitting a ground signal, that is, the Gate g and the substrate b of the second protection sub-circuit 14 are Grounded at the same time, and a Gate-G Grounded N Metal Oxide Semiconductor (GGNMOS) is formed. It is understood that, in other possible embodiments, the second protection sub-circuit 14 may also be other types of electronic components, which is not limited in this application.
In this embodiment, please refer to fig. 4, wherein fig. 4 is a schematic cross-sectional view of a second protection sub-circuit according to an embodiment of the present application. A parasitic diode 141 and a parasitic resistor 142 are formed between the source s and the drain d of the second protection sub-circuit 14 and the substrate b.
The parasitic diode 141 and the parasitic resistor 142 of the second protection sub-circuit 14 are generated internally in the manufacturing process flow of the transistor, and the present application is schematically illustrated in the circuit form of fig. 4.
Specifically, as shown in fig. 4, since the second protection sub-circuit 14 is a GGNMOS, a parasitic npn bipolar diode is formed between the source s and the drain d of the second protection sub-circuit 14 and the substrate b, where n represents an n-type semiconductor injection region, p represents a p-type semiconductor injection region, and npn is a semiconductor junction. The drain junction of the second protection sub-circuit 14 is a semiconductor junction formed by an n-type semiconductor injection region at the d end of the drain of the second protection sub-circuit 14 and a p-type semiconductor injection region at the b end of the substrate.
When the drain-body junction of the second protection sub-circuit 14 is broken down, the electrostatic current discharged from the first voltage line AVSS is transmitted to the output circuit PAD via the substrate b of the second protection sub-circuit 14, the parasitic resistor 142, and the parasitic diode 141, and since the gate g of the input stage unit 121 is electrically connected to the output circuit PAD, the second protection sub-circuit 14 clamps the gate g-oxide layer voltage difference of the input stage unit 121 to a lower level through the parasitic diode 141 and the parasitic resistor 142.
In one possible implementation, when negative ESD is generated between the output circuit PAD and the first voltage line AVSS, the sum of the voltage of the parasitic diode 141 of the second protection sub-circuit 14 and the voltage of the parasitic resistor 142 of the second protection sub-circuit 14 is smaller than the gate g oxide breakdown voltage of the input stage unit 121.
Specifically, when negative ESD is generated between the output circuit PAD and the first voltage line AVSS, the second protection sub-circuit 14 clamps the gate g oxide voltage difference of the input stage unit 121 to a lower level. In this embodiment, the voltage difference between the two ends of the parasitic diode 141 of the second protection sub-circuit 14 is 0.6V, and the voltage difference between the two ends of the parasitic resistor 142 of the second protection sub-circuit 14 is 2V, that is, the voltage difference between the gate g and the oxide layer of the input stage unit 121 is clamped to 2.6V by the second protection sub-circuit 14.
Based on the above, the breakdown voltage of the gate g oxide layer of the input stage protection unit is usually 3V, that is, the sum of the voltage of the parasitic diode 141 of the second protection sub-circuit 14 and the voltage of the parasitic resistor 142 of the second protection sub-circuit 14 is smaller than the breakdown voltage of the gate g oxide layer of the input stage unit 121, so that when a negative ESD is generated between the output circuit PAD and the first voltage line AVSS, the generated electrostatic current cannot break down the gate g oxide layer of the input stage unit 121, thereby achieving the purpose of protecting the input stage unit 121.
In one possible implementation, referring again to fig. 2, the CDM ESD protection circuit 1 further includes a clamp sub-circuit 15, the first sub-circuit 11 is further electrically connected to a second voltage line VSS, and the first voltage line AVSS is electrically connected to the second voltage line VSS through the clamp sub-circuit 15.
In this embodiment, the first sub-circuit 11 and the second sub-circuit 12 may be different chip integrated circuits, or may be the same chip integrated circuit, that is, the voltage value of the voltage signal transmitted by the first voltage line AVSS may be different from the voltage value of the voltage signal transmitted by the second voltage line VSS.
Specifically, the clamping sub-circuit 15 is configured to clamp the voltage values of the voltage signals transmitted by the two ends of the first voltage line AVSS and the second voltage line VSS to a certain range, so as to prevent the input stage unit 121 from being damaged by an excessive current due to an excessive voltage difference between the two ends.
In one possible implementation, referring again to fig. 2, the CDM ESD protection circuit 1 further includes a resistor sub-circuit 16, and the second sub-circuit 12 is electrically connected to the output circuit PAD through the resistor sub-circuit 16.
It should be noted that, in general, two circuits may need to be electrically connected to each other through a peripheral circuit, so as to realize a certain function.
In one possible implementation, referring to fig. 2 again, the first sub-circuit 11 includes at least one first pull-up unit 111 and at least one pull-down unit 112, a source s of the first pull-up unit 111 is electrically connected to a third voltage line VDD, a drain d of the first pull-up unit 111 is electrically connected to the output circuit PAD, a source s of the pull-down unit 112 is electrically connected to a second voltage line VSS, and a drain d of the pull-down unit 112 is electrically connected to the output circuit PAD; the second sub-circuit 12 further includes at least one second pull-up unit 122, a source s of the second pull-up unit 122 is electrically connected to the fourth voltage line AVDD, a drain d of the second pull-up unit 122 is electrically connected to the drain d of the input stage unit 121, and a gate g of the second pull-up unit 122 is electrically connected to the gate g of the input stage unit 121.
It should be noted that, in fig. 2, the number of the second pull-up units 122 is two, which plays a role in voltage division and current limitation. It is understood that, in other possible embodiments, the number of the second pull-up units 122 may be other, which is not limited in this application.
Specifically, the first pull-up unit 111 is configured to control the first sub-circuit 11 to output a pull-up signal to the output circuit PAD, so as to raise a waveform of the output circuit PAD; the pull-down unit 112 is configured to control the first sub-circuit 11 to output a pull-down electrical signal to the output circuit PAD, so that the waveform of the output circuit PAD is decreased, and the output circuit PAD can output a periodic waveform signal, thereby implementing a certain function. Similarly, the second pull-up unit 122 is configured to control the second sub-circuit 12 to output a pull-up electrical signal to the output circuit PAD, and the input stage unit 121 is configured to control the second sub-circuit 12 to output a pull-down electrical signal to the output circuit PAD.
In this embodiment, the voltage value of the voltage signal transmitted by the fourth voltage line AVDD is greater than the voltage value of the voltage signal transmitted by the first voltage line AVSS; the voltage value of the voltage signal transmitted by the third voltage line VDD is greater than the voltage value of the voltage signal transmitted by the second voltage line VSS. It can be understood that, since the first sub-circuit 11 and the second sub-circuit 12 may be the same chip integrated circuit or different chip integrated circuits, the voltage value of the voltage signal transmitted by the fourth voltage line AVDD and the voltage value of the voltage signal transmitted by the third voltage line VDD may be equal or unequal, which is not limited in this application.
It can be understood that, in the present embodiment, since the first protection sub-circuit 13 is disposed in series with the input stage unit 121, and the second protection sub-circuit 14 is disposed in parallel with the input stage unit 121, damage to the input stage unit 121 caused by ESD is prevented, so that the first sub-circuit 11 and the second sub-circuit 12 can operate normally.
In one possible implementation, please refer to fig. 5 and fig. 6 together, in which fig. 5 is a schematic cross-sectional view of a PMOS according to an embodiment of the present application; fig. 6 is a schematic cross-sectional view of an NMOS provided in an embodiment of the present application. The first pull-up unit 111 and the second pull-up unit 122 are P-type Metal Oxide semiconductors (PMOS), and the pull-down unit 112, the input stage unit 121, the first protection sub-circuit 13, and the second protection sub-circuit 14 are NMOS.
Specifically, as shown in fig. 5, the PMOS device is formed by a gate g and an N-type semiconductor encapsulating two P-type semiconductors, wherein one P-type semiconductor is a source s and the other is a drain d. The gate g is a metal electrode, and an insulating layer I is further disposed between the gate g and the source s and the drain d. As trivalent element impurities are doped in the P-type semiconductor material, most carriers in the P-type semiconductor are holes, and the holes are positively charged. When the transistor is a PMOS, a low potential is loaded on the grid g, and the two P-type semiconductors form a channel to conduct the source s and the drain d.
As shown in fig. 6, the NMOS is formed by a gate g and a P-type semiconductor wrapping two N-type semiconductors, one of which is a source s and the other is a drain d. The gate g is a metal electrode, and an insulating layer I is further disposed between the gate g and the source s and the drain d. Since pentavalent element impurities are doped in the N-type semiconductor material, most carriers in the N-type semiconductor are electrons, and the electrons are negatively charged. When the transistor is an NMOS, a high voltage is applied to the gate g, and the two N-type semiconductors form a channel to turn on the source s and the drain d.
It can be understood that, due to the characteristics of particles, PMOS has a fast turn-on speed and low power consumption compared to NMOS, and therefore PMOS is used as the first pull-up unit 111 and the second pull-up unit 122 to control pull-up, and NMOS is used as the pull-down unit 112, the input stage unit 121, the first protection sub-circuit 13, and the second protection sub-circuit 14 to control pull-down.
The principle and the embodiment of the present application are explained herein by applying specific examples, and the above description of the embodiment is only used to help understand the core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims (6)

1. A CDM ESD protection circuit, wherein the CDM ESD protection circuit comprises a first sub-circuit, a second sub-circuit, a first protection sub-circuit and a second protection sub-circuit, the first sub-circuit is electrically connected to an output circuit and the second sub-circuit, the second sub-circuit comprises at least one input stage unit, the input stage unit is electrically connected to the output circuit and a first voltage line, the gate of the first protection sub-circuit is used for receiving a scan signal, the scan signal is used for controlling the on/off of the first protection sub-circuit, the drain of the first protection sub-circuit is electrically connected to the input stage unit, the source of the first protection sub-circuit is electrically connected to the first voltage line, the substrate of the first protection sub-circuit is electrically connected to the first voltage line, the gate of the second protection sub-circuit is electrically connected to the first voltage line, the drain electrode of the second protection sub-circuit is electrically connected with the output circuit, the source electrode of the second protection sub-circuit is electrically connected with the first voltage line, the substrate of the second protection sub-circuit is electrically connected with the first voltage line, and the second sub-circuit is electrically connected with the first voltage line; when negative ESD is generated between the output circuit and the first voltage line, the sum of the parasitic diode voltage of the second protection sub-circuit and the parasitic resistance voltage of the second protection sub-circuit is smaller than the gate oxide layer breakdown voltage of the input stage unit; when positive ESD is generated between the output circuit and the first voltage line, the drain junction breakdown voltage of the second protection sub-circuit is smaller than the sum of the gate oxide layer breakdown voltage of the input stage unit and the source-drain channel breakdown voltage of the first protection sub-circuit.
2. The CDM ESD protection circuit of claim 1 in which the parasitic diode and the parasitic resistance are formed between the source, drain and substrate of the second protection subcircuit.
3. The CDM ESD protection circuit of claim 1 further comprising a clamp subcircuit, the first subcircuit further electrically connected to a second voltage line, the first voltage line electrically connected to the second voltage line through the clamp subcircuit.
4. The CDM ESD protection circuit of claim 1 further comprising a resistive subcircuit through which the second subcircuit is electrically connected with the output circuit.
5. The CDM ESD protection circuit of claim 1, wherein the first sub-circuit comprises at least one first pull-up unit and at least one pull-down unit, the gate of the first pull-up unit is configured to receive a first control signal, the first control signal is configured to control on/off of the first pull-up unit, the source of the first pull-up unit is electrically connected to a third voltage line, the drain of the first pull-up unit is electrically connected to the output circuit, the gate of the pull-down unit is configured to receive a second control signal, the second control signal is configured to control on/off of the pull-down unit, the source of the pull-down unit is electrically connected to a second voltage line, and the drain of the pull-down unit is electrically connected to the output circuit; the second sub-circuit further comprises at least one second pull-up unit, wherein a source electrode of the second pull-up unit is electrically connected with a fourth voltage line, a drain electrode of the second pull-up unit is electrically connected with a drain electrode of the input stage unit, and a grid electrode of the second pull-up unit is electrically connected with a grid electrode of the input stage unit.
6. The CDM ESD protection circuit of claim 5, wherein the first pull-up unit and the second pull-up unit are PMOS, and the pull-down unit, the input stage unit, the first protection sub-circuit and the second protection sub-circuit are NMOS.
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US5637900A (en) * 1995-04-06 1997-06-10 Industrial Technology Research Institute Latchup-free fully-protected CMOS on-chip ESD protection circuit
CN102148499B (en) * 2010-02-10 2015-04-01 上海华虹宏力半导体制造有限公司 CDM (Charged Device Model) ESD (Electro-Static Discharge) protection circuit
JP5603277B2 (en) * 2011-03-29 2014-10-08 セイコーインスツル株式会社 ESD protection circuit for semiconductor integrated circuit
CN104319271A (en) * 2014-10-17 2015-01-28 武汉新芯集成电路制造有限公司 CDM (Charged-Device-Model) electrostatic protection circuit
CN109326593A (en) * 2018-11-09 2019-02-12 珠海格力电器股份有限公司 ESD protection device, IO circuit and ESD protection method thereof

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