JP2013191767A - Esd protective transistor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an ESD protective transistor element the characteristic deterioration of which due to occurrence of soft leak can be prevented.SOLUTION: In a well 12 formed on a semiconductor substrate 11, a first semiconductor region 13 of a conductivity type reverse to that of the well 12 is formed so as to be separated while holding the well 12 or a semiconductor region of a conductivity type same as that of the well 12. Since the first semiconductor region 13 does not come into direct contact with an element isolation film 15, even if a high voltage high current is applied to the first semiconductor region 13 by electrostatic discharge (ESD), occurrence of crystal defect at the end of the element isolation film is suppressed, and occurrence of soft leak can be prevented.

Description

  The present invention relates to an ESD protection transistor element that protects a semiconductor integrated circuit from electrostatic discharge (ESD) caused by external static electricity.

  In a semiconductor integrated circuit composed of a plurality of semiconductor elements, an ESD protection circuit is used to protect the semiconductor elements and the circuit from electrostatic discharge (ESD) caused by external static electricity. Such an ESD protection circuit includes an ESD protection element, and a high electric field / high voltage due to ESD is applied to the ESD protection element, whereby a high electric field / high voltage is applied to the internal circuit, and the semiconductor provided in the internal circuit The element is prevented from being destroyed.

  FIG. 11 shows a schematic diagram of a cross-sectional structure of a general ESD protection element having a conventional configuration described in Patent Document 1. In FIG. A parasitic bipolar transistor is formed by the first N + diffusion layer 41 coupled to the coupling pad 40 (collector) and the second N + diffusion layer 42 coupled to the power supply voltage Vss (emitter) on the low voltage side, and the two diffusion layers 41 and 42 are connected to each other. They are separated by field oxide 43. The parasitic bipolar transistor thus formed conducts a large amount of ESD discharge current by a self-bias mechanism.

Japanese Patent No. 4856803

  On the other hand, when a high electric field / voltage due to ESD is applied to such an ESD protection transistor element, even if the ESD protection transistor element does not break down, a soft leak occurs and should be originally non-conductive. Nevertheless, a leakage current may flow. One cause of this soft leak is a crystal defect.

  At the edge of the element isolation film such as LOCOS, a crystal defect is likely to occur due to some external stimulus due to stress concentration at the time of forming the element isolation film, and external heat such as ESD due to high voltage and high current is applied. Crystal defects are generated by mechanical stimulation. This crystal defect causes a soft leak and reduces the electrostatic resistance of the ESD protection transistor element. As a result, a leak current is generated at a terminal connected to the ESD protection transistor element.

  In view of the above situation, an object of the present invention is to provide an ESD protection transistor element that can suppress crystal defects generated at the edge of an element isolation film and prevent soft leakage.

In order to achieve the above object, an ESD protection transistor element according to the present invention comprises:
A first conductivity type well formed on the substrate, an element isolation film formed on the well, and a first active region partitioned by the element isolation film, formed on the substrate surface layer in the well A first semiconductor region of a second conductivity type opposite to the well formed, and a second semiconductor region of the second conductivity type formed on the substrate surface layer in the well so as to be separated from the first semiconductor region. And a third semiconductor region of the first conductivity type at a higher concentration than the well connected to the well on the substrate surface layer in the well,
The first semiconductor region is formed so as to be separated from the element isolation film across the well on the entire outer periphery.

An ESD protection transistor element according to the present invention having the above characteristics is provided as follows:
A bipolar transistor structure may be employed in which the first semiconductor region is a collector region, the second semiconductor region is an emitter region, and the well between the first semiconductor region and the second semiconductor region is a base region. .

An ESD protection transistor element according to the present invention having the above characteristics is provided as follows:
The first semiconductor region is a drain region, the second semiconductor region is a source region, the third semiconductor region is a body region, and a gate insulating film is interposed on the well separating the drain region and the source region. A structure having a MOS transistor structure in which electrodes are formed can be employed.

An ESD protection transistor element according to the present invention having the above characteristics is provided as follows:
The second semiconductor region may be formed in a second active region separated from the first active region and partitioned by the element isolation film.

An ESD protection transistor element according to the present invention having the above characteristics is provided as follows:
The third semiconductor region may be formed in a third active region that is partitioned by the element isolation film and is different from the first active region.

  In the ESD protection transistor element according to the present invention having the above characteristics, it is preferable that the dummy electrode is formed in an isolation region on the well that separates the first semiconductor region from the element isolation film via an insulating film. .

  In the ESD protection transistor element according to the present invention having the above characteristics, it is preferable that a predetermined fixed voltage is applied to the dummy electrode.

  According to the ESD protection transistor element of the present invention having the above characteristics, the well and the first semiconductor region having the opposite conductivity type formed in the surface layer in the first conductivity type well are not in direct contact with the element isolation film. , Are formed so as to be separated from each other with the well interposed therebetween. As a result, the first semiconductor region is used as the collector of the bipolar transistor that constitutes the ESD protection element, and the drain of the MOS transistor. Crystal defects generated at the film edge are suppressed, and soft leakage can be prevented.

  Here, on the well that separates the first semiconductor region from the element isolation film, a dummy electrode is formed through an insulating film so that ion implantation for forming the first semiconductor region is performed using the dummy electrode as a mask. It can be carried out. Such a dummy electrode is formed in the same material and in the same process as the gate electrode of the MOS transistor formed in the internal circuit, so that the first semiconductor region is separated from the separation region with no additional mask process. It can be formed so as to be separated from the film.

Sectional structure figure which shows typically the device structure of the ESD protection transistor element concerning 1st Embodiment of this invention The figure which shows the layout on the board | substrate surface of the ESD protection transistor element which concerns on 1st Embodiment of this invention. Sectional structure figure which shows typically the device structure of the ESD protection transistor element concerning 1st Embodiment of this invention The figure which shows the layout on the board | substrate surface of the ESD protection transistor element which concerns on 1st Embodiment of this invention. Sectional structure figure which shows typically the device structure of the ESD protection transistor element concerning 2nd Embodiment of this invention The figure which shows the layout on the board | substrate surface of the ESD protection transistor element which concerns on 2nd Embodiment of this invention. Sectional structure figure which shows typically the device structure of the ESD protection transistor element concerning 2nd Embodiment of this invention The figure which shows the layout on the board | substrate surface of the ESD protection transistor element which concerns on 2nd Embodiment of this invention. Sectional structure figure which shows typically the device structure of the ESD protection transistor element concerning another embodiment of this invention Sectional structure figure which shows typically the device structure of the ESD protection transistor element concerning another embodiment of this invention Cross-sectional structure diagram schematically showing the device structure of a conventional ESD protection element

  Hereinafter, a configuration example of the ESD protection transistor element of the present invention (hereinafter, appropriately referred to as “the element of the present invention”) will be described in detail with reference to the drawings. In the drawings shown below, for the convenience of explanation, the main parts are emphasized and the dimensional ratios such as the thicknesses and lengths of the constituent members may not necessarily match the actual dimensional ratios.

<First Embodiment>
FIG. 1 is a schematic view of a cross-sectional structure of an ESD protection transistor element 1 (hereinafter, referred to as “present invention element 1” as appropriate) according to an embodiment of the present invention, and FIG. 1 is a cross-sectional structure diagram in the XX ′ direction of FIG.

  A well 12 of the same first conductivity type is formed on a semiconductor substrate 11 of a first conductivity type (here, P type), and a second conductivity of a conductivity type opposite to the first conductivity type is formed on the surface layer of the well 12. High-concentration semiconductor regions 13 and 14 of a type (that is, N type) are formed separated by an element isolation film 15. On the other hand, a high concentration semiconductor region 16 of the same conductivity type (that is, P type) as the first conductivity type is formed on the surface layer of the well 12 so as to be separated from both the semiconductor regions 13 and 14 by the element isolation film 15. Yes. In other words, the high-concentration semiconductor regions 13, 14, and 16 are each formed in another active region. The element isolation film 15 is an oxide film formed by, for example, the LOCOS method.

  The semiconductor region (first semiconductor region) 13 is connected to the collector electrode 21 through a contact plug 19 a that penetrates the gate insulating film 17 and the interlayer insulating film 18. Similarly, the semiconductor region (second semiconductor region) 14 is connected to the emitter electrode 22 through a contact plug 19 b that penetrates the gate insulating film 17 and the interlayer insulating film 18. Similarly, the semiconductor region (third semiconductor region) 16 is connected to the base electrode 23 via a contact plug 19 c that penetrates the gate insulating film 17 and the interlayer insulating film 18. That is, the element 1 of the present invention has an NPN bipolar transistor structure in which the semiconductor region 13 is a collector region, the semiconductor region 14 is an emitter region, and the well 12 between the collector region and the emitter region is a base region. . The semiconductor region 16 supplies a base potential to the base region.

  As shown in FIGS. 1 and 2, the element 1 of the present invention is a semiconductor region on the substrate surface layer that is the well 12 without the collector region 13 being in direct contact with the element isolation film 15 at all end boundaries of the collector region 13. It is formed so as to be separated from each other. As a result, in the element 1 of the present invention, even when a high voltage and a high current due to electrostatic discharge (ESD) are applied to the collector region 13, the generation of crystal defects at the end of the element isolation film 15 is suppressed. The occurrence of soft leaks can be prevented.

  As for the separation distance between the collector region 13 and the element isolation film 15, the optimum distance varies depending on the manufacturing process (particularly, the difference in the heat treatment process). However, about 0.5 μm to 1.0 μm is preferable for a general semiconductor device manufacturing process.

  3 and 4 show another configuration example of the element of the present invention having a bipolar transistor structure. The ESD protection transistor element 2 (hereinafter referred to as “present invention element 2” as appropriate) shown in the schematic diagram of the cross-sectional structure in FIG. 3 and the layout on the substrate plane in FIG. 4 is the element isolation film in the present invention element 1 described above. A dummy electrode 20 is formed via a gate insulating film 17 on a well 12 on the surface layer of the substrate that separates 15 and the collector region 13 so as to straddle the element isolation film 15 located at the outer boundary of the active region. . FIG. 3 is a cross-sectional structure diagram in the X-X ′ direction of FIG. 4.

  The dummy electrode 20 is formed by the same material and the same process as the gate electrode of the MOS transistor formed in the internal circuit, and serves as a mask when forming the collector region 13 and the emitter region 14 by ion implantation of N-type impurities. The N-type semiconductor region is prevented from being formed in the well 12 below the dummy electrode 20. After forming the ESD element, a predetermined fixed voltage (for example, power supply voltage Vss or Vdd) may be applied to the dummy electrode 20, or a voltage may not be applied and the dummy electrode 20 may be floating. However, when a predetermined fixed voltage is applied to the dummy electrode 20, when a surge current due to ESD flows to the element 2 of the present invention, the potential of the dummy electrode 20 fluctuates in an unstable manner, resulting in variations in element characteristics. Is more preferable.

  The element 2 of the present invention does not require a separate mask in order to form the collector region 13 apart from the element isolation film 15, thereby preventing the occurrence of the above-described soft leak without changing the process and increasing the process cost. An ESD protection device can be provided.

  In the present invention elements 1 and 2, the configuration of the ESD protection element having the NPN type bipolar transistor structure has been described. However, the present invention can be similarly applied to the ESD protection element having the PNP type bipolar transistor structure. .

Second Embodiment
FIG. 5 is a schematic diagram of a cross-sectional structure of an ESD protection transistor element 3 (hereinafter, appropriately referred to as “present invention element 3”) according to an embodiment of the present invention, and FIG. 6 shows a layout on the substrate plane. 5 is a cross-sectional structure diagram in the YY ′ direction of FIG.

  A well 12 of the same first conductivity type is formed on a semiconductor substrate 11 of a first conductivity type (here, P type), and a second conductivity of a conductivity type opposite to the first conductivity type is formed on the surface layer of the well 12. The high concentration semiconductor regions 24 and 25 of the type (that is, N type) are formed in the same active region so as to face each other with the well 12 interposed therebetween. On the other hand, a high concentration semiconductor region 26 of the same conductivity type (that is, P type) as the first conductivity type is formed on the surface layer of the well 12 so as to be separated from both of the semiconductor regions 24 and 25 by the element isolation film 15. Yes. In other words, the high concentration semiconductor region 26 is formed in an active region different from the semiconductor regions 24 and 25. The element isolation film 15 is an oxide film formed by, for example, the LOCOS method.

  The semiconductor region (first semiconductor region) 24 is connected to the drain electrode 28 via a contact plug 27 a penetrating the gate insulating film 17 and the interlayer insulating film 18. Similarly, the semiconductor region (second semiconductor region) 25 is connected to the source electrode 29 through a contact plug 27 b that penetrates the gate insulating film 17 and the interlayer insulating film 18. Similarly, the semiconductor region (third semiconductor region) 26 is connected to the body electrode 30 via a contact plug 27 c that penetrates the gate insulating film 17 and the interlayer insulating film 18. That is, the element 2 of the present invention has an N-channel MOS transistor structure in which the semiconductor region 24 is a drain region, the semiconductor region 25 is a source region, and the well 12 on the substrate surface layer separating the drain region and the source region is a channel region. doing. The semiconductor region 26 supplies a potential supplied from the body electrode 30 to the well 12 of the channel region. A gate electrode 31 is formed above the channel region via a gate insulating film 17.

  As shown in FIGS. 5 and 6, the element 3 of the present invention has a semiconductor region on the substrate surface layer which is the well 12 without the drain region 24 being in direct contact with the element isolation film 15 at all end boundaries of the drain region 24. It is formed so as to be separated from each other. Thereby, in the element 3 of the present invention, even when a high voltage and a high current due to electrostatic discharge (ESD) are applied to the drain region 24, generation of crystal defects at the end of the element isolation film 15 is suppressed. The occurrence of soft leaks can be prevented.

  As for the separation distance between the drain region 24 and the element isolation film 15, the optimum distance varies depending on the manufacturing process (particularly, the difference in the heat treatment process). However, about 0.5 μm to 1.0 μm is preferable for a general semiconductor device manufacturing process.

  7 and 8 show another configuration example of the element of the present invention having a MOS transistor structure. The ESD protection transistor element 4 (hereinafter referred to as “present invention element 4” as appropriate) shown in the schematic diagram of the cross-sectional structure in FIG. 7 and the layout on the substrate plane in FIG. 8 is the element isolation film in the present invention element 3 described above. The dummy electrode 20 is formed on the well 12 of the substrate surface layer separating the drain 15 and the drain region 24 via the gate insulating film 17 so as to straddle the element isolation film 15 located at the outer boundary of the active region. Formed in the same manner. 7 is a cross-sectional structure diagram in the Y-Y ′ direction of FIG. 8.

  In this embodiment, the dummy electrode 20 is formed of the same material and in the same process as the gate electrode of the MOS transistor formed in the internal circuit, and is integrally formed with the gate electrode 31 of the element 4 of the present invention. Thus, the dummy electrode 20 formed integrally with the gate electrode 31 at the drain region 24 side boundary between the drain region 24 and the element isolation film 15 forms the drain region 24 and the source region 25 by ion implantation of N-type impurities. It acts as a mask at the time of preventing the drain region 24 from being formed in contact with the element isolation film 15. After the ESD element is formed, a predetermined fixed voltage may be applied to the dummy electrode 20, or a voltage may not be applied and the dummy electrode 20 may be floating.

  However, since the dummy electrode 20 is integrally formed with the gate electrode 31 in the element 4 of the present invention, when the voltage is applied to the dummy electrode 20, the same voltage is also applied to the gate electrode 31. When an N-channel MOS transistor is used as an ESD protection element, the N-channel MOS transistor needs to be kept in a non-conductive state in normal use. Therefore, the dummy electrode 20 (and It is necessary to control the potential of the gate electrode 31) below the threshold voltage.

  For the above reason, in the case of the element 4 of the present invention, the dummy electrode 20 and the gate electrode 31 have a low-voltage power supply so that the N-channel MOS transistor constituting the ESD protection transistor element becomes non-conductive in normal use. It is preferable to apply the voltage Vss.

  In the present invention elements 3 and 4, the configuration of the ESD protection element having the N-channel MOS transistor structure has been described. However, the present invention can be similarly applied to the ESD protection element having the P-channel MOS transistor structure.

  However, when a P-channel MOS transistor is used as an ESD protection element, the P-channel MOS transistor does not form a channel in the P-channel MOS transistor so that a non-conducting state is maintained in normal use. It is necessary to control the potential of the gate electrode 31). For this reason, when a P-channel MOS transistor is used in the configuration of the element 4 of the present invention in which the dummy electrode 20 is integrally formed with the gate electrode 31, the P-channel MOS transistor constituting the ESD protection element is in a non-conductive state in normal use. As described above, it is preferable to apply the power supply voltage Vdd on the high voltage side to the dummy electrode 20 and the gate electrode 31.

  As described above, according to the elements 1 to 4 of the present invention, the first semiconductor region 13 or 24 having the opposite conductivity type to the well 12 sandwiches the semiconductor region of the substrate surface layer which is the well 12 without directly contacting the element isolation film 15. Therefore, even when a high voltage / high current due to ESD is applied to the first semiconductor region, generation of crystal defects at the end of the element isolation film 15 is suppressed, Soft leaks can be prevented.

  In addition, about the manufacturing method of the said this invention elements 1-4, since all are realizable by a well-known manufacturing process, detailed description was omitted.

<Another embodiment>
Another embodiment will be described below.

  <1> In the first embodiment, in the present invention elements 1 and 2, the collector region (first semiconductor region) 13, the emitter region (second semiconductor region) 14, and the semiconductor region (third semiconductor region) 16 are Each of the semiconductor regions 13, 14, and 16 is formed in a different active region. However, like the ESD protection transistor element 5 having the bipolar transistor structure shown in the cross-sectional structure diagram of FIG. It may be formed. As long as the semiconductor region 13 is formed so as not to be in direct contact with the element isolation film 15 so as to be separated from the semiconductor region 13 with the opposite conductivity type semiconductor region interposed therebetween, generation of soft leak can be prevented.

  <2> On the other hand, in the second embodiment, in the present invention elements 3 and 4, the drain region (first semiconductor region) 24 and the source region (second semiconductor region) 25 are formed in the same active region. However, a configuration in which the drain region and the source region are formed in different active regions as in the ESD protection transistor element 6 having the MOS transistor structure shown in the cross-sectional structure diagram of FIG.

  <3> In the above embodiment, the semiconductor region (third semiconductor region) 16 or 26 is formed in an active region different from the first and second semiconductor regions. It may be formed in the same active region as at least one of the semiconductor regions.

  <4> The present invention relates to a layout for constructing an ESD protection transistor element, and the first semiconductor region 13 or 24 is not in direct contact with the element isolation film 15, and the first semiconductor region and the opposite conductivity type. Each semiconductor region (the first semiconductor regions 13, 24, the second semiconductor regions 14, 25, the third semiconductor regions 16, 26, the well 12, etc.) The size (depth and area), impurity concentration, and material constituting the device are not limited at all. The element isolation film 15 is not limited to a film formed by the LOCOS method.

  The present invention can be used for an ESD protection transistor element that is provided in a semiconductor integrated circuit and protects the circuit from ESD caused by external static electricity.

1 to 6: ESD protection transistor element according to one embodiment of the present invention (element of the present invention)
11: Semiconductor substrate 12: First conductivity type well 13: Second conductivity type high concentration semiconductor region (collector region)
14: Second conductivity type high concentration semiconductor region (emitter region)
15: Element isolation film 16, 26: High concentration semiconductor region of first conductivity type 17: Gate insulating film 18: Interlayer insulating films 19a to 19c, 27a to 27c: Contact plug 20: Dummy electrode 21: Collector electrode 22: Emitter electrode 23: Base electrode 24: High conductivity semiconductor region (drain region) of the second conductivity type
25: High conductivity semiconductor region of second conductivity type (source region)
28: Drain electrode 29: Source electrode 30: Body electrode 31: Gate electrode 40: Bonding pad (collector)
41: 1st N + diffusion layer 42: 2nd N + diffusion layer 43: Field oxide Vdd: High-voltage side power supply voltage Vss: Low-voltage side power supply voltage

Claims (7)

A first conductivity type well formed on the substrate;
An element isolation film formed on the well;
A first conductive region of a second conductivity type opposite to the well formed in the substrate surface layer in the well in a first active region partitioned by the element isolation film;
A second semiconductor region of the second conductivity type formed on the substrate surface layer in the well and spaced apart from the first semiconductor region;
A third semiconductor region of the first conductivity type at a higher concentration than the well connected to the well on the substrate surface layer in the well;
The ESD protection transistor element, wherein the first semiconductor region is formed so as to be separated from the element isolation film across the well on the entire outer periphery.   2. A bipolar transistor structure in which the first semiconductor region is a collector region, the second semiconductor region is an emitter region, and the well between the first semiconductor region and the second semiconductor region is a base region. Item 2. The ESD protection transistor element according to Item 1.   The first semiconductor region is a drain region, the second semiconductor region is a source region, the third semiconductor region is a body region, and a gate insulating film is interposed on the well separating the drain region and the source region. 2. The ESD protection transistor element according to claim 1, which has a MOS transistor structure in which an electrode is formed.   The said 2nd semiconductor region is formed in the 2nd active region different from the said 1st active region divided by the said element isolation film, The any one of Claims 1-3 characterized by the above-mentioned. The ESD protection transistor element according to 1.   The said 3rd semiconductor region is formed in the 3rd active region different from the said 1st active region divided by the said element isolation film, The any one of Claims 1-4 characterized by the above-mentioned. The ESD protection transistor element according to 1.   6. The dummy electrode according to claim 1, wherein a dummy electrode is formed in an isolation region on the well that separates the first semiconductor region from the element isolation film via an insulating film. The ESD protection transistor element as described. The ESD protection transistor element according to claim 6, wherein a predetermined fixed voltage is applied to the dummy electrode.