TWI678790B - Electrostatic discharge protection device - Google Patents

Abstract

An electrostatic discharge protection element includes a substrate, a high-voltage N-well region, and a high-voltage P-well region. The substrate has a first region and a second region, and the second region surrounds the first region. The high-pressure N well area is arranged on the base, and the high-pressure P well area is arranged on the high-pressure N well area. The first region is configured on the high-voltage N-well region, and includes a first doped region having a first conductivity type, a second doped region having a second conductivity type and surrounding the first doped region, a first conductivity type and surrounding A third doped region of the second doped region. The second region is configured on the high-voltage P-well region and includes a plurality of fourth doped regions having a second conductivity type and a fifth doped region having a first conductivity type. The plurality of fourth doped regions are arranged at intervals and surround the first region, and the fifth doped region surrounds each of the first region and the plurality of fourth doped regions.

Description

ESD protection components

The present invention relates to a semiconductor device, and more particularly, to an electrostatic discharge protection element having an electrostatic discharge protection function.

High-voltage electrostatic discharge (ESD) components designed with the Triple Well Process have been widely used. Used in high-voltage electrostatic discharge protection components, high-voltage MOSFET (Metal-Oxide- Semiconductor Field-Effect Transistor) components usually have low on-resistance (Rdson) characteristics, so during an electrostatic discharge event, the electrostatic discharge current may be concentrated on the surface of the component or The drain edge causes high current and high electric field to physically destroy the junction area of the element. In addition, based on the low on-resistance (Rdson) requirements, the surface or lateral layout design rules are generally not changed due to electrostatic discharge protection performance in high-voltage processes. However, the electrostatic discharge protection performance of high-voltage electrostatic discharge components usually depends on the overall width, surface, and lateral layout design rules.

In terms of electrostatic discharge protection performance, high-voltage electrostatic discharge devices generally have a high breakdown voltage, but the trigger voltage of high-voltage electrostatic discharge devices is usually much higher than the breakdown voltage. Therefore, during an electrostatic discharge event, the protected component or internal circuit usually has a risk of damage before the high-voltage electrostatic discharge element is triggered for electrostatic discharge protection. Conventional techniques design additional electrostatic discharge detection circuits to reduce the trigger voltage, but electrostatic discharge detection circuits increase the layout area. On the other hand, adding additional masks and steps to the process to reduce the trigger voltage will increase manufacturing costs.

In view of this, the present invention provides a semiconductor device that can use the existing Mitsui manufacturing process to produce an electrostatic discharge protection element with a low trigger voltage, a high withstand current, and a small layout area.

An embodiment of the present invention provides an ESD protection element, wherein the ESD protection element includes, but is not limited to, a substrate, a high-voltage N-well region, and a high-voltage P-well region. The substrate has a first region and a second region, the second region surrounds the first region, and the substrate has a first conductivity type. The high-voltage N well region has a second conductivity type and is disposed on the substrate, and the high-voltage P well region has a first conductivity type and is disposed on the high-voltage N well region. The first region is disposed on the high-voltage N-well region. The first region includes a first doped region, a second doped region, and a third doped region. The first doped region has a first conductivity type, the second doped region has a second conductivity type and surrounds the first doped region, and the third doped region has a first conductivity type and surrounds the second doped region. The second region is disposed on the high-voltage P-well region, and the second region includes a plurality of fourth doped regions and fifth doped regions. The plurality of fourth doped regions have a second conductivity type, and the plurality of fourth doped regions are arranged at intervals and surround the first region. The fifth doped region has a first conductivity type, and the fifth doped region surrounds each of the first region and the plurality of fourth doped regions.

Based on the above, the present invention provides an electrostatic discharge protection element with a low trigger voltage. A ring-shaped N + doped region and a P + doped region are arranged outside the P + doped region in the high-pressure N well region, and a plurality of P + doped regions are arranged in the high-pressure P well region surrounding the high-pressure N well region. The N + doped regions are arranged at intervals to provide multiple parasitic bipolar transistors in the ESD path, further reducing the trigger voltage of the ESD protection element, and improving the ESD protection capability.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

In the following embodiments, the first conductivity type is a P-type and the second conductivity type is an N-type for illustration, but the present invention is not limited thereto. In another embodiment, the first conductivity type may be an N-type, and the second conductivity type may be a P-type.

FIG. 1 is a simplified top view of an electrostatic protection circuit according to an embodiment of the present invention. Fig. 2 is a schematic cross-sectional view taken along a section line A-A 'of Fig. 1. Fig. 3 is a schematic cross-sectional view taken along the line B-B 'in Fig. 1.

Please refer to FIG. 1, FIG. 2 and FIG. 3 at the same time. In one embodiment, the ESD protection element 10 includes a substrate 110, a high-voltage N-well region 120, a high-voltage P-well region 130, a first doped region 141, a second doped region 142, a third doped region 143, and a fourth The doped region 144, the fifth doped region 145, the field oxide region 150, and the polycrystalline silicon region 160.

In one embodiment, the substrate 110 is a P-type silicon substrate having a first conductivity type. The substrate 110 has a first region A1 and a second region A2, and the second region A2 surrounds the first region A1, as shown in FIG. 1. In another embodiment, the substrate may also be a P-epi layer.

In one embodiment, the high-pressure N-well region 120 is disposed on the substrate 110, and the high-pressure P-well region 130 is disposed on the high-pressure N-well region 120. In one embodiment, the high-voltage N-well region 120 is a doped region with a second conductivity type, and the high-voltage P-well region 130 is a doped region with a first conductivity type. In an embodiment, the high-pressure N-well region 120 may be an N-epi, a single N + buried layer, or a stack of multiple N + buried layers. The high-pressure P-well region 130 may be a P-type well, a P-type buried layer, or a P-type implanted region.

The first region A1 is disposed on the high-pressure N-well region 120. The first region A1 includes a first doped region 141, a second doped region 142, and a third doped region 143. Referring to FIG. 1, the first doped region 141 is a high-concentration doped region (P +) having a first conductivity type. The second doped region 142 is a high-concentration doped region (N +) having a second conductivity type, and the second doped region 142 surrounds the first doped region 141. The third doped region 143 is a high-concentration doped region (P +) having a first conductivity type, and the third doped region 143 surrounds the second doped region 142. Referring to FIGS. 2 and 3, the first doped region 141, the second doped region 142, and the third doped region 143 are electrically connected to the positive electrode of the power source.

The second area A2 is disposed on the high-pressure P-well area 130. The second region A2 includes a plurality of fourth doped regions 144 and fifth doped regions 145. Referring to FIG. 1, the plurality of fourth doped regions 144 are high-concentration doped regions (N +) having the second conductivity type. The plurality of fourth doped regions 144 are arranged at intervals and surround the first region A1. The plurality of fourth doped regions 144 have the same size. For example, the plurality of fourth doped regions 144 on the upper and lower sides of FIG. 1 have the same width a, and the plurality of fourth doped regions 144 on the left and right sides of FIG. 1. They have the same width x. In one embodiment, the width a and the width x are, for example, 7.2 μm. In another embodiment, the width a may not be equal to the width x, depending on the actual design requirements. The plurality of fourth doped regions 144 have the same spacing distance in the same arrangement direction. For example, a distance c between the plurality of fourth doped regions on the upper and lower sides of FIG. 1 is a distance c, and a distance c between the plurality of fourth doped regions on the left and right sides of FIG. 1 is a distance z, In one embodiment, the pitch c and the pitch z are, for example, 1.2 μm. In another embodiment, the distance c may not be equal to the distance z, which depends on the actual design requirements. In addition, although there are four fourth doped regions 144 on the upper and lower sides of FIG. 1 and eight fourth doped regions 144 on the left and right sides of FIG. 1, the present invention does not limit the plurality of fourth doped regions 144. The actual configuration method depends on the actual design requirements. The fifth doped region 145 is a high-concentration doped region (P +) having a first conductivity type. The fifth doped region 145 surrounds the first region A1, and the fifth doped region 145 also surrounds each of the plurality of fourth doped regions 144. Referring to FIGS. 2 and 3, the fourth doped region 144 and the fifth doped region 145 are electrically connected to the negative electrode of the power source.

It must be noted that the difference between FIG. 2 and FIG. 3 is that the section line AA ′ includes a plurality of fourth doped regions 144 and fifth doped regions 145 on the upper and lower sides of FIG. 1, and the section line B-B ′ Only the fifth doped regions 145 on the upper and lower sides are included. In addition, the above-mentioned first doped region 141, second doped region 142, third doped region 143, fourth doped region 144, and fifth doped region 145 are high-concentration doped regions, which means that their doped regions The impurity concentration is higher than the doping concentration of the substrate 110, the high-pressure N-well region 120, and the high-pressure P-well region 130.

Referring to FIGS. 2 and 3, the ESD protection device 10 further includes a field oxide region 150 and a polycrystalline silicon region 160. The field oxidation region 150 is disposed between the third doped region 143 and the fifth doped region 145. The polycrystalline silicon region 160 is configured on the field oxidation region 150. The polycrystalline silicon region 160 is electrically connected to the positive electrode of the power source. The polycrystalline silicon can be made by a single-layer single-poly process or a double-poly process. The present invention is not limited thereto. .

FIG. 4 is an equivalent circuit diagram of a schematic cross-sectional view taken along a section line A-A 'of FIG. 1. FIG. Referring to FIG. 4, FIG. 4 shows an equivalent circuit of the ESD protection element 10 in a section line A-A '. The equivalent circuit includes parasitic bipolar transistors B1-B10. Taking the left side of FIG. 4 as an example, the second doped region 142 (N +), the high-voltage N well region 120, the high-voltage P well region 130, and the fourth doped region 144 (N +) constitute a parasitic bipolar transistor B1, where the parasitic bipolar Transistor B1 is an NPN transistor. The third doped region 143 (P +), the high-voltage N well region 120, the high-voltage P well region 130, and the fifth doped region 145 (P +) constitute two parasitic bipolar transistors B2 and B3, among which the parasitic bipolar transistor B2 And B3 belongs to PNP transistor. 1 and 4, the fifth doped region 145 includes a portion far from the A1 side and a portion near the A1 side, and the fifth doped region 145 far from the A1 side becomes a collector of the parasitic bipolar transistor B2, The five-doped region 145 becomes the collector of the parasitic bipolar transistor B3. Similarly, the first doped region 141 (P +), the high-voltage N-well region 120, the high-voltage P-well region 130, and the fifth doped region 145 (P +) constitute two parasitic bipolar transistors B4 and B5, where the parasitic bipolar Transistors B4 and B5 are PNP transistors. 1 and 4, the fifth doped region 145 includes a portion far from the A1 side and a portion near the A1 side, and the fifth doped region 145 near the A1 side becomes a collector of the parasitic bipolar transistor B4, and the first portion far from the A1 side. The five-doped region 145 becomes the collector of the parasitic bipolar transistor B5. By analogy, the parasitic bipolar transistors B6-B10 on the right side of FIG. 4 are as described above, and will not be described again.

FIG. 5 is a simplified diagram of the equivalent circuit of FIG. 4. Referring to FIG. 4 and FIG. 5 at the same time, parasitic bipolar transistor B1 and parasitic bipolar transistor B6 can be equivalent to parasitic bipolar transistor NPN1, and parasitic bipolar transistor B2-5 and parasitic bipolar transistor B7-10 can Equivalent to parasitic bipolar transistor PNP2-5. That is, the electrostatic discharge protection element 10 can be equivalent to an equivalent circuit including a parasitic bipolar transistor NPN1 and a parasitic bipolar transistor PNP2-5. In other words, when an electrostatic discharge power is provided from the positive pole of the power supply to the negative pole of the power At this time, the electrostatic discharge protection element 10 can discharge the electrostatic current through a plurality of electrostatic discharge paths generated after the parasitic bipolar transistor NPN1 and the parasitic bipolar transistor PNP2-5 are turned on. Compared with the conventional technology, the parasitic bipolar transistor NPN1 and the parasitic bipolar transistor PNP2-5 can further reduce the trigger voltage and the on-resistance of the electrostatic discharge protection element 10 and improve the protection ability of the electrostatic discharge.

FIG. 6 is an equivalent circuit diagram of a schematic cross-sectional view taken along a section line B-B 'of FIG. 1. FIG. Similar to FIG. 4, FIG. 6 shows an equivalent circuit of the ESD protection element 10 in a section line B-B '. Referring to Fig. 6, the equivalent circuit in section line B-B 'includes parasitic bipolar transistors B11-B14. Taking the left side of FIG. 6 as an example, the third doped region 143 (P +), the second doped region 142 (N +) and the high-pressure N-well region 120, the high-pressure P-well region 130, and the fifth doped region 145 (P +) constitute parasitics. Bipolar transistor B11. The first doped region 141 (P +), the second doped region 142 (N +) and the high-voltage N well region 120, the high-voltage P well region 130 and the fifth doped region 145 (P +) constitute a parasitic bipolar transistor B12, where Parasitic bipolar transistors B11 and B12 are PNP transistors. By analogy, the parasitic bipolar transistors B13-B14 on the right side of FIG. 4 are as described above, and will not be described again.

In summary, the present invention provides an electrostatic discharge protection element with a low trigger voltage. A ring-shaped N + doped region and a P + doped region are arranged outside the P + doped region in the high-pressure N well region, and a plurality of P + doped regions are arranged in the high-pressure P well region surrounding the high-pressure N well region The N + doped regions are arranged at intervals to provide multiple parasitic bipolar transistors in the ESD path, further reducing the trigger voltage of the ESD protection element, and improving the ESD protection capability.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

10‧‧‧ Electrostatic discharge protection element

110‧‧‧ substrate

120‧‧‧High-pressure N well area

130‧‧‧High-pressure P well area

141‧‧‧first doped region

142‧‧‧second doped region

143‧‧‧third doped region

144‧‧‧ Fourth doped region

145‧‧‧ fifth doped region

150‧‧‧field oxidation zone

160‧‧‧Polycrystalline silicon area

A1‧‧‧ District 1

A2‧‧‧Second District

B1-B14, NPN1, PNP2, PNP3, PNP4, PNP5‧‧‧parasitic bipolar transistor

A-A ’, B-B’‧‧‧ hatching

a, b, x, y‧‧‧width

c, z‧‧‧ pitch

FIG. 1 is a simplified top view of an electrostatic protection circuit according to an embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view taken along a section line AA ′ of FIG. 1.
FIG. 3 is a schematic cross-sectional view taken along a section line BB ′ in FIG. 1.
FIG. 4 is an equivalent circuit diagram of a schematic cross-sectional view taken along a section line AA ′ of FIG. 1.
FIG. 5 is a simplified diagram of the equivalent circuit of FIG. 4.
FIG. 6 is an equivalent circuit diagram of a schematic cross-sectional view taken along a section line BB ′ in FIG. 1.

Claims (10)

An electrostatic discharge protection element includes:
A substrate having a first region and a second region, the second region surrounding the first region, and the substrate having a first conductivity type;
A high-pressure N-well region having a second conductivity type and being disposed on the substrate; and a high-pressure P-well region having the first conductivity type and being disposed on the high-pressure N-well region;
The first area is configured on the high-pressure N-well area and includes:
A first doped region having the first conductivity type;
A second doped region having the second conductivity type and surrounding the first doped region; and a third doped region having the first conductivity type and surrounding the second doped region,
The second zone is configured on the high-pressure P-well zone and includes:
A plurality of fourth doped regions have the second conductivity type, the plurality of fourth doped regions are arranged at intervals and surround the first region; and a fifth doped region has the first conductivity type, The fifth doped region surrounds each of the first region and the plurality of fourth doped regions. The electrostatic discharge protection element according to item 1 of the scope of patent application, wherein the plurality of fourth doped regions have the same size. The electrostatic discharge protection element according to item 1 of the scope of patent application, wherein the plurality of fourth doped regions have the same separation distance in the same arrangement direction. The electrostatic discharge protection element according to item 1 of the patent application scope, wherein the first doped region, the second doped region, and the third doped region are electrically connected to a positive electrode of a power source, and the fourth The doped region and the fifth doped region are electrically connected to the negative electrode of the power source. The electrostatic discharge protection element according to item 1 of the patent application scope further includes:
A field oxidation region is disposed between the third doped region and the fifth doped region; and a polycrystalline silicon region is disposed on the field oxidation region, and the polycrystalline silicon region is electrically connected to a positive electrode of a power source. The electrostatic discharge protection element according to item 5 of the scope of the patent application, wherein the polycrystalline silicon region is a single polycrystalline silicon or a double polycrystalline silicon. The electrostatic discharge protection element according to item 1 of the patent application scope, wherein the substrate is a P-type silicon substrate or a P-type epitaxial layer. The electrostatic discharge protection element according to item 1 of the scope of patent application, wherein the high-voltage N-well area is an N-type epitaxial layer, a single N-type buried layer or multiple N-type buried layers, and the high-voltage P-well area is P-type well, P-type buried layer, or P-type low-doped region. The electrostatic discharge protection element according to item 1 of the scope of patent application, wherein the first conductivity type and the second conductivity type have opposite electrical properties. The electrostatic discharge protection element according to item 1 of the scope of patent application, wherein the first doped region, the second doped region, the third doped region, the fourth doped region, and the The doping concentration of the fifth doped region is higher than that of the substrate, the high-pressure N-well region, and the high-pressure P-well region.