TWI708364B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device and a manufacturing method thereof are provided. First, an epitaxial layer is formed on a substrate, and the epitaxial layer is divided into an active region and a electrostatic discharge (ESD) protection region. A first body region is formed in the active region of the epitaxial region, and a second body region is formed in the ESD protection region. Thereafter, a laminated structure is formed on the surface of the epitaxial layer and located at the ESD protection region, and the laminated structure includes an insulating layer and a semiconductor layer having a first heavily doped region. A second heavily doped region is then formed in the semiconductor layer. The first and second heavily doped regions jointly form a ESD protection layer, in which the ESD protection layer completely overlaps with the second body region.

Description

Semiconductor element and its manufacturing method

The present invention relates to a semiconductor element and a manufacturing method thereof, in particular to a semiconductor element with an electrostatic protection layer and a manufacturing method thereof.

In the application field of semiconductor power components, the ability of semiconductor power components to protect against electrostatic discharge has become an important indicator. Some small-signal semiconductor power components have a small chip size, and therefore have poor ESD protection capabilities, and even fail to meet the minimum standards for ESD protection. Although some semiconductor power components have a larger chip size, they can have a larger electrostatic discharge protection capability, but they may need to be in a harsh environment (such as a dry environment with a relative humidity of <65%, or an environment with more dust ), so there are higher requirements for the electrostatic discharge protection of semiconductor power components.

Therefore, in the existing technology, the electrostatic discharge protection structure is integrated into the semiconductor power device to increase the ability of the semiconductor power device to withstand electrostatic discharge. However, in the existing manufacturing process, due to the limitation of the process conditions and the process window, the position of the electrostatic discharge protection structure is easily shifted from the predetermined position. In addition, in existing semiconductor power devices, the electrostatic discharge protection structure directly connects the drift region and the base region, and an arc-shaped interface extending along the thickness direction of the epitaxial layer is formed between the drift region and the base region.

Therefore, when the semiconductor power device is operating, the electric field strength at the arc-shaped interface between the drift region and the base region is relatively strong, causing the collapse phenomenon to often occur in the area near the arc-shaped interface, and reducing the withstand voltage of the semiconductor power device itself.

On the other hand, for existing semiconductor power devices, the breakdown voltage Breakdown voltage and on-resistance are more important parameters. Among them, the on-resistance affects the conducting loss of semiconductor power devices. Currently, the industry tends to increase the doping concentration of the drift region to further reduce the on-resistance of the semiconductor power device. However, the existing semiconductor power devices have relatively low withstand voltage after integrating the electrostatic discharge protection structure, and it is more difficult to comply with the current industry trend.

One of the technical problems to be solved by the present invention is to overcome the problem of low withstand voltage of the semiconductor element with the electrostatic discharge protection structure.

In order to solve the above-mentioned technical problems, one of the technical solutions adopted by the present invention is to provide a method for manufacturing a semiconductor device. The aforementioned manufacturing method includes the following steps. An epitaxial layer is formed on a substrate, and the epitaxial layer is divided into at least one device area and an electrostatic protection area. A first base area is formed in the element area and a second base area is formed in the electrostatic protection area. A stacked structure is formed on the surface of the epitaxial layer. The stacked structure is located in the electrostatic protection area and includes an insulating layer and a semiconductor layer on the insulating layer. The semiconductor layer has a first heavily doped area. At least one second heavily doped region is formed in the semiconductor layer, and the second heavily doped region and the first heavily doped region together form an electrostatic protection layer. The static electricity protection layer is located above the second base region, and the static electricity protection layer completely overlaps within the second base region.

Another technical solution adopted by the present invention is to provide a semiconductor device, which is divided into a device area and an electrostatic protection area, and the semiconductor device includes an epitaxial layer, a gate structure and an electrostatic protection layer. The epitaxial layer includes a first base area located in the device area and a second base area located in the electrostatic protection area. The gate structure is arranged in the element area and connected to at least the first base area. The electrostatic protection layer is arranged on a surface of the epitaxial layer and is isolated from the epitaxial layer. The static electricity protection layer is located above the second base region, and the static electricity protection layer completely overlaps within the second base region.

The beneficial effect of the present invention is that the semiconductor element and the manufacturing method thereof provided by the present invention adopts "the electrostatic protection layer is completely overlapped within the range of the second base region" The technical means can make the semiconductor element with the electrostatic protection layer meet the electrostatic discharge protection standard, and also have a higher withstand voltage.

In order to further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are only for reference and description, and are not used to limit the present invention.

M1, M2‧‧‧Semiconductor components

10‧‧‧Substrate

11, 11’, 11"‧‧‧Epitaxial layer

R1‧‧‧Component area

R2‧‧‧Static protection zone

11h‧‧‧Groove

11s‧‧‧surface

110, 110’‧‧‧Drift Zone

111‧‧‧First matrix area

112‧‧‧Second base area

112a‧‧‧Extension

113a‧‧‧First source region

113b‧‧‧Second source region

12‧‧‧Gate structure

120‧‧‧Gate insulation layer

121‧‧‧Gate

13’‧‧‧Initial insulation

14P‧‧‧Undoped semiconductor layer

P1’‧‧‧Laminated structure

14"‧‧‧Initial semiconductor layer

14’‧‧‧Semiconductor layer

P1‧‧‧Static protection stack

13‧‧‧Insulation layer

14‧‧‧Static protection layer

140、140’‧‧‧First heavily doped area

141‧‧‧Second heavily doped area

15, 15’‧‧‧Interlayer dielectric layer

15h‧‧‧Contact window

16‧‧‧Conductive structure

161‧‧‧The first conductive pillar

162‧‧‧Second conductive pillar

17‧‧‧Pad set

171‧‧‧First pad

172‧‧‧Second pad

18‧‧‧Protection layer

20‧‧‧Matrix doping steps

30‧‧‧Heavy doping step

111’‧‧‧First initial matrix doped area

112’‧‧‧The second initial matrix doped area

PR‧‧‧Photoresist layer

S100~S130‧‧‧Process steps

FIG. 1 shows a flowchart of a semiconductor device according to one embodiment of the invention.

2A is a schematic partial cross-sectional view of a semiconductor device in a manufacturing process according to an embodiment of the present invention.

2B is a schematic partial cross-sectional view of the semiconductor device in the manufacturing process of the embodiment of the present invention.

2C is a schematic partial cross-sectional view of the semiconductor device in the manufacturing process of the embodiment of the present invention.

2D is a schematic partial cross-sectional view of the semiconductor device in the manufacturing process of the embodiment of the present invention.

2E is a schematic partial cross-sectional view of the semiconductor device in the manufacturing process of an embodiment of the present invention.

2F is a schematic partial cross-sectional view of the semiconductor device in the manufacturing process of the embodiment of the present invention.

2G is a schematic partial cross-sectional view of the semiconductor device in the manufacturing process of the embodiment of the present invention.

3 is a schematic partial cross-sectional view of a semiconductor device according to an embodiment of the invention.

4 is a schematic partial cross-sectional view of a semiconductor device in a manufacturing process according to another embodiment of the invention.

5 is a schematic partial cross-sectional view of a semiconductor device in a manufacturing process according to another embodiment of the present invention.

6 is a schematic partial cross-sectional view of a semiconductor device according to an embodiment of the invention.

Please refer to Figure 1. FIG. 1 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the invention. Specifically, the present invention provides a method for manufacturing a semiconductor device with an electrostatic protection layer, and at least has the following steps.

In step S100, an epitaxial layer is formed on a substrate, wherein the epitaxial layer is divided into at least one device area and an electrostatic protection area. In step S110, a first base area and a second base area are formed in the device area and the electrostatic protection area, respectively. In step S120, a stacked structure located in the electrostatic protection zone is formed on the surface of the epitaxial layer. The stacked structure includes an insulating layer and a semiconductor layer located on the insulating layer, wherein the semiconductor layer has a first heavily doped Miscellaneous area. In step S130, at least one second heavily doped region is formed in the semiconductor layer, and the second heavily doped region and the first heavily doped region together form an electrostatic protection layer. The static electricity protection layer is located above the second base region, and the static electricity protection layer completely overlaps within the second base region.

The specific steps in the manufacturing method of the semiconductor element will be described in detail below. In this embodiment, a trench semiconductor power device is taken as an example to illustrate the manufacturing method of the embodiment of the present invention in detail.

Please refer to FIG. 2A, which shows a partial cross-sectional view of a semiconductor device in a manufacturing process according to an embodiment of the present invention. An epitaxial layer 11 has been formed on the substrate 10. The substrate 10 is, for example, a silicon substrate, which has a first-type conductivity impurity with a high doping concentration to serve as a drain of the semiconductor power device.

The aforementioned first conductivity type impurities may be N-type or P-type conductivity impurities. Assuming that the substrate 10 is a silicon substrate, the N-type conductive impurity is a pentavalent element ion, such as phosphorus ion or arsenic ion, and the P-type conductive impurity is a trivalent element ion, such as boron ion, aluminum ion or gallium ion.

If the trench power semiconductor element is an N-type power MOSFET, the substrate 10 is doped with N-type conductive impurities. On the other hand, if the trench-type power semiconductor element is a P-type trench-type power MOSFET, the substrate 10 is doped with P-type conductive impurities.

The epitaxial layer 11" is formed on the substrate 10 and has a low concentration of first-type conductivity impurities. Taking NMOS transistors as an example, the substrate 10 is made of high-concentration N-type doping (N ⁺ ), and the epitaxy layer 11 "was a low concentration of N type dopant (N ^-). Conversely, taking the PMOS transistor as an example, the substrate 10 is high-concentration P-doping (P ⁺ doping), and the epitaxial layer 11" is low-concentration P-doping (P ^- doping).

In this embodiment, the epitaxial layer 11" has a surface 11s, and the epitaxial layer 11" is divided into a device region R1 and an electrostatic protection region R2. It should be noted that although FIG. 2A shows that the electrostatic protection area R2 is surrounded by the element area R1, the present invention does not limit the positions of the electrostatic protection area R2 and the element area R1. In another embodiment, the element area R1 may be located on one side of the electrostatic protection area R2. In yet another embodiment, the element region R1 may be surrounded by the electrostatic protection region R2. In other words, the configuration position and shape of the static electricity protection area R2 and the element area R1 can be changed according to actual requirements, and the present invention is not limited.

As shown in FIG. 2A, at least one gate structure 12 (a plurality of which are shown in FIG. 2A as an example) has been formed in the device region R1, and the gate structure 12 includes a gate insulating layer 120 and a gate 121. In addition, the gate structure 12 may be a planar gate structure or a trench gate structure.

In this embodiment, the gate structure 12 is a trench gate structure. In the step of forming the gate structure 12, a plurality of trenches 11h located in the element region R1 are first formed in the epitaxial layer 11", and then a gate insulating layer 120 and a gate electrode 121 are sequentially formed in the trenches 11h.

As shown in FIG. 2A, a matrix doping step 20 is performed on the epitaxial layer 11" to form a first initial matrix doping region 111' in the element region R1 and a second initial matrix doping region R2. District 112'.

2B, an initial insulating layer 13' and an undoped semiconductor layer 14P are sequentially formed on the surface 11s of the epitaxial layer 11". The initial insulating layer 13' will cover the entire surface 11s of the epitaxial layer 11". The material of the initial insulating layer 13' can be oxide or nitride, such as silicon oxide or silicon nitride.

In addition, the thickness of the initial insulating layer 13' is adjusted according to the magnitude of the gate-source bias (Vgs) of the semiconductor power element. As the gate-source voltage (Vgs) of the semiconductor power element is larger, the thickness of the initial insulating layer 13' is thicker.

The undoped semiconductor layer 14P is formed on the initial insulating layer 13' to be isolated from the epitaxial layer 11". The undoped semiconductor layer 14P may be an undoped polysilicon layer. After that, the undoped semiconductor layer 14P is performed A heavy doping step 30.

Please refer to FIG. 2C, performing a substrate thermal immersion step to form a first substrate region 111 and a second substrate region 112 in the epitaxial layer 11'. On the other hand, in the step of thermally advancing the substrate, the first heavily doped region 140' will be simultaneously formed in the undoped semiconductor layer 14P to form an initial semiconductor layer 14".

In this embodiment, in the heavy doping step 30 and the matrix doping step 20, impurities with the same conductivity type are used. In other words, the first heavily doped region 140', the first body region 111, and the second body region 112 all have the same conductivity type, but this is only an example and does not limit the present invention. In other embodiments, the first heavily doped region 140', the first body region 111, and the second body region 112 can also be subjected to different conductivity types to add additional processing steps to achieve the doping result.

It should be noted that, in this embodiment, the step of forming the initial semiconductor layer 14" is completed before performing the substrate heat-trending step. However, in other embodiments, the substrate heat-trending step may also be performed first. The first body region 111 and the second body region 112 are formed. After that, another thermal approach step is performed to form the initial semiconductor layer 14" with the first heavily doped region 140'.

In other embodiments, the first base region 111 and the second base region 112 may be formed in the epitaxial layer 11" before forming the gate structure 12 in the device region R1.

As shown in FIG. 2C, the first base region 111 is located in the element region R1 of the epitaxial layer 11' and surrounds the gate structure 12. The other regions in the epitaxial layer 11' form the drift region 110' of the trench semiconductor device. The second base region 112 is located in the static electricity protection region R2 and connected to the initial insulating layer 13'.

2D, a part of the initial insulating layer 13' and a part of the initial semiconductor layer 14" in the device region R1 are removed to form a stacked structure P1' in the electrostatic protection region R2.

Specifically, a photoresist layer PR can be formed on the initial semiconductor layer 14" to define the position of the laminated structure P1', and then an etching step is performed to remove a part of the initial semiconductor layer 14" and a part of the initial semiconductor layer 14" located in the element region R1. Insulation layer 13'. The other part of the initial semiconductor layer 14" and the initial insulating layer 13' covered by the photoresist layer PR will be retained, and a laminated structure P1' is formed in the electrostatic protection region R2.

Accordingly, the stacked structure P1' includes a semiconductor layer 14' and an insulating layer 13 in the electrostatic protection region R2, and the semiconductor layer 14' has a first heavily doped region 140'. By forming the stacked structure P1' through the above steps, the position shift of the stacked structure P1' can be avoided, which may cause the semiconductor layer 14' to directly contact the epitaxial layer 11'. In this embodiment, the lateral width of the semiconductor layer 14' is approximately the same as the lateral width of the insulating layer 13. Specifically, the difference between the width of the semiconductor layer 14' and the width of the insulating layer 13 is less than 0.5um.

2E, at least one second heavily doped region 141 is further formed in the semiconductor layer 14', so that the at least one second heavily doped region 141 and the first heavily doped region 140 together form an electrostatic protection layer 14. The static electricity protection layer 14 is disposed on the insulating layer 13, and the static electricity protection layer 14 and the insulating layer 13 together form the static electricity protection stack P1.

In detail, a mask pattern layer (not shown) can be pre-formed on the semiconductor layer 14' to define the position of the second heavily doped region 141. After that, by sequentially performing a doping step and a heat sinking step, the second heavily doped region 141 can be formed in the semiconductor layer 14'.

The second heavily doped region 141 and the first heavily doped region 140 have opposite conductivity types, respectively. Therefore, a PN junction is formed at the interface between the second heavily doped region 141 and the first heavily doped region 140.

In the embodiment of FIG. 2E, two separate second heavily doped regions 141 are formed in the semiconductor layer 14', and the first heavily doped regions 140 are located in the two second heavily doped regions Between 141, a bipolar diode is formed, such as a PNP double junction diode or an NPN double junction diode.

In addition, in the step of forming the second heavily doped region 141, at least one first source region 113a (a plurality of them are shown in FIG. 2E) can be simultaneously formed in the element region R1. Accordingly, the first source region 113a and the second heavily doped region 141 will have the same conductivity type.

It should be noted that the position of the second heavily doped region 141 can be adjusted by changing the mask pattern layer to form different electrostatic protection layers 14. Please refer to FIG. 4 first, which shows a schematic cross-sectional view of a semiconductor device in the manufacturing process of another embodiment of the present invention, and the step of FIG. 2D can be continued.

In the embodiment of FIG. 4, only a second heavily doped region 141 is formed in the semiconductor layer 14' to form a PN junction diode. Therefore, as long as the electrostatic discharge protection effect can be achieved, the electrostatic protection layer 14 may be a double junction diode, a PN diode or other components.

Please refer to FIG. 5 again, which shows a schematic cross-sectional view of a semiconductor device in the manufacturing process of another embodiment of the present invention, and the step of FIG. 2D can be continued. In the step of forming the second heavily doped region 141, at least one first source region 113a (multiple are shown in FIG. 5) and at least one second source are formed in the electrostatic protection region R2 simultaneously in the element region R1 Polar regions 113b (two are shown in Figure 5).

In the embodiment of FIG. 5, the first source region 113 a is located above the first body region 111 and is connected to at least one gate structure 12. In addition, the second base region 112 has an extension portion 112a, and the extension portion 112a is connected to the gate structure 12 closest to the electrostatic protection region R2. The second source region 113b is formed on the upper part of the extension portion 112a and is connected to the gate structure 12 closest to the electrostatic protection region R2.

It is worth noting that through the above steps, a transistor structure can be formed on the element R1 and an electrostatic protection stack P1 can be formed in the electrostatic protection region R2. Accordingly, in the process steps of the embodiment of the present invention, the step of forming the electrostatic protection layer P1 can be integrated with the step of forming the transistor structure, thereby reducing the manufacturing cost.

Please refer to Figure 2F, Figure 2G and Figure 3 to form a redistributed circuit structure to The transistor structure and the static protection stack P1 can be electrically connected to an external control circuit. In detail, as shown in FIG. 2F, an interlayer dielectric layer 15' is formed on the surface 11s of the electrostatic protection layer 14 and the epitaxial layer 11. Next, as shown in FIG. 2G, a plurality of contact windows 15h are formed in the interlayer dielectric layer 15, and a plurality of conductive structures 16 are formed in the plurality of contact windows 15h.

The conductive structure 16 includes a plurality of first conductive pillars 161 and a plurality of second conductive pillars 162. Each first conductive pillar 161 is electrically connected to the corresponding first source region 113a through the corresponding contact window 15h. Each second conductive pillar 162 is electrically connected to the first heavily doped region 140 or the second heavily doped region 141 of the electrostatic protection layer 14 through the corresponding contact window 15h. In addition, the first heavily doped region 140 may or may not be connected to the second conductive pillar 162, depending on application requirements.

Please refer to FIG. 3, which shows a schematic partial cross-sectional view of a semiconductor device according to an embodiment of the present invention. In this embodiment, a pad set 17 is further formed on the interlayer dielectric layer 15. The pad set 17 includes a plurality of first pads 171 and a plurality of second pads 172. The first pad 171 is electrically connected to the first source region 113 a and the second source region 113 b through the corresponding first conductive pillar 161. The second pad 172 is electrically connected to the first heavily doped region 140 or the second heavily doped region 141 through the corresponding second conductive pillar 162.

After that, a protective layer 18 is formed on the pad set 17. The protective layer 18 has a plurality of openings, and each opening exposes the corresponding first pad 171 (or second pad 172), so that the plurality of first pads 171 and the plurality of second pads 172 can be electrically connected To the external control circuit.

Accordingly, as shown in FIG. 3, an embodiment of the present invention provides a semiconductor device M1 integrated with the electrostatic protection layer 14. The semiconductor element M1 is, for example, a trench metal oxide semi-transistor, a lateral diffusion metal oxide semi-transistor, or a planar metal oxide semi-transistor.

The semiconductor device M1 can be divided into a device area R1 and an electrostatic protection area R2. The area of the electrostatic protection zone R2 can be adjusted according to actual application requirements. If the semiconductor element M1 needs to meet a higher ESD protection specification, that is, it has a greater ESD tolerance, the area of the ESD protection zone R2 will also be larger.

The semiconductor device M1 includes a substrate 10, an epitaxial layer 11, a gate structure 12, and an electrostatic protection stack P1. The epitaxial layer 11 is disposed on the substrate 10 and has a drift region 110, a first body region 111, a second body region 112, and a first source region 113a. The drift region 110 is located on the side of the epitaxial layer 11 close to the substrate 10 and extends from the device region R1 to the electrostatic protection region R2.

The first base region 111 is located in the device region R1 and is located on a side away from the substrate 10. In other words, the first base region 111 is located above the drift region 110. In addition, the first source region 113a is located above the first base region 111 and connected to the surface 11s of the epitaxial layer 11.

The second base region 112 is located in the electrostatic protection region R2 and is located on the side of the epitaxial layer 11 away from the substrate 10, that is, above the drift region 110.

When the semiconductor device M1 is a trench metal oxide semi-transistor, the epitaxial layer 11 further includes at least one trench 11h located in the device region R1, and the gate structure 12 is disposed in the trench 11h.

As shown in FIG. 3, the gate structure 12 includes a gate insulating layer 120 and a gate 121. The gate insulating layer 120 covers the inner wall surface of the trench 11 h to electrically insulate the gate electrode 121 from the epitaxial layer 11. The gate structure 12 located in the device region R1 is connected to the first body region 111 and the first source region 113a.

In this embodiment, the second base region 112 is connected to the gate structure 12 closest to the electrostatic protection region R2.

The electrostatic protection stack P1 is disposed on the epitaxial layer 11 and is located in the electrostatic protection area R2 to protect the semiconductor element M1 from electrostatic discharge damage. The static electricity protection stack P1 includes an insulating layer 13 and an static electricity protection layer 14, and the insulating layer 13 is located between the static electricity protection layer 14 and the epitaxial layer 11 to isolate the static electricity protection layer 14 from the second base region 112. Accordingly, the insulating layer 13 will be directly connected to the second base region 112.

In addition, since one end of the electrostatic protection layer 14 is at the same potential with the gate 121, the thickness of the insulating layer 13 can be determined according to the source gate bias (Vgs) applied to the semiconductor device M1. When the source gate bias (Vgs) is greater, the thickness of the insulating layer 13 Need to be thicker.

The electrostatic protection layer 14 includes at least one first heavily doped region 140 and at least one second heavily doped region 141. In one embodiment, the first heavily doped region 140, the first body region 111 and the second body region 112 have the same conductivity type, for example, both are P-type doped regions. The second heavily doped region 141 and the first source region 113a have the same conductivity type, for example, both are N-type doped regions, but the invention is not limited. Different conductivity types can also be used to add additional process steps to achieve doping results.

In addition, the lateral width of the static electricity protection layer 14 is substantially the same as the lateral width of the insulating layer 13. Furthermore, the difference between the width of the static electricity protection layer 14 and the width of the insulating layer 13 is less than 0.5 um. In one embodiment, the static electricity protection layer 14 is located above the second base region 112, and the static electricity protection layer 14 completely overlaps within the range of the second base region 112.

It is worth noting that the static electricity protection layer 14 of the embodiment of the present invention is located above the second base region, and the static electricity protection layer completely overlaps the second base region. Compared with the existing semiconductor power device, the current The bottom of the electrostatic protection stack P1 of the embodiment of the invention is not directly connected to the drift region 110, but only to the second base region 112. Therefore, in the electrostatic protection region R2, the interface formed between the second base region 112 and the drift region 110 extends substantially along the direction parallel to the surface 11s.

Since in the semiconductor device M1 provided by the present invention, the static electricity protection stack P1 is only connected to the second base region 112, when the semiconductor device M1 is operating, the electric field intensity at the interface between the second base region 112 and the drift region 110 is relatively high. It is uniform, so that the semiconductor element M1 of the embodiment of the present invention has a higher withstand voltage. Accordingly, compared with the existing semiconductor power device, the semiconductor device M1 of the embodiment of the present invention not only has the electrostatic discharge protection capability, but also has a certain withstand voltage capability.

Please refer to FIG. 6, which shows a partial cross-sectional view of a semiconductor device according to another embodiment of the present invention. Elements in this embodiment that are the same as those in the embodiment of FIG. 3 have the same reference numerals, and the same parts will not be repeated.

The difference between this embodiment and the embodiment of FIG. 3 is that the semiconductor of this embodiment In the body element M2, the gate structure 12 is a planar gate structure. In other words, the gate structure 12 is disposed on the surface 11s of the epitaxial layer 11. In addition, in the element region R1, the epitaxial layer 11 includes a plurality of first base regions 111 separated from each other, and each first source region 113a is respectively surrounded by a corresponding first base region 111.

In addition, in this embodiment, the second base region 112 will be connected to the gate structure 12 closest to the electrostatic protection region R2. Specifically, the second body region 112 is connected to the gate insulating layer 120 of the gate structure 12.

The manufacturing method of the embodiment of the present invention can also be used to form the semiconductor element M2. Specifically, after forming the first base region 111 and the second base region 112, the gate structure 12 can be formed on the surface 11s of the epitaxial layer 11 in the device region R1.

Accordingly, in the manufacturing method of the semiconductor device of the present invention, as long as the second base region 112 can be formed under the electrostatic protection stack P1 completely overlapping with it, the order of the steps can be based on the structure of the semiconductor device itself or the requirements of the manufacturing process. Adjustment.

Based on the above, the beneficial effect of the present invention lies in the semiconductor device and the manufacturing method provided by the technical solution of the present invention. The second method is to form the second layer located in the electrostatic protection region R2 in the epitaxial layer 11 before forming the electrostatic protection stack P1. The technical means of "base area 112" and "the electrostatic protection layer is completely overlapped within the scope of the second base area" can make the semiconductor element with the electrostatic protection laminate P1 meet the electrostatic discharge protection standards and have a higher withstand voltage .

In addition, in the semiconductor device manufacturing method of the embodiment of the present invention, the step of forming the ESD protection layer P1 in the ESD protection region R2 can be integrated with the step of forming the transistor structure in the device R1, thereby reducing the manufacturing cost.

The content disclosed above is only the preferred and feasible embodiments of the present invention, and does not limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made using the content of the description and drawings of the present invention are included in the application of the present invention. Within the scope of the patent.

S100~S130‧‧‧Process steps

Claims (15)

A method for manufacturing a semiconductor device, comprising: forming an epitaxial layer on a substrate, wherein the epitaxial layer is divided into at least one element area and an electrostatic protection area; forming a first layer in the element area A base area, and a second base area is formed in the static electricity protection area; a laminated structure is formed on the surface of the epitaxial layer, and the laminated structure is located in the static electricity protection area and includes an insulation Layer and a semiconductor layer on the insulating layer, wherein the semiconductor layer has a first heavily doped region; and at least one second heavily doped region is formed in the semiconductor layer, wherein the first heavily doped region The double doped region and the first heavily doped region together form an electrostatic protection layer, and the electrostatic protection layer is located above the second base region, and the electrostatic protection layer completely overlaps the second base Within the area. The manufacturing method according to claim 1, in the step of forming at least one second heavily doped region in the semiconductor layer, the step includes: sequentially performing a doping step and a thermal approach step to simultaneously At least one first source region is formed in the first body region of the element region, and the second heavily doped region is formed in the semiconductor layer, and the first heavily doped region and the second heavily doped region are formed in the semiconductor layer. The interface of the doped region is a PN junction. The manufacturing method according to claim 2, further comprising: forming at least one gate structure in the element region, wherein the second base region has an extended portion and is connected to at least one gate structure, and In the step of forming the first source region, a second source region on the extension portion is simultaneously formed. The manufacturing method according to claim 3, wherein the gate structure is a trench gate Pole structure or planar gate structure. The manufacturing method according to claim 1, wherein the step of forming the first base region and the second base region includes: performing a matrix doping step on the epitaxial layer to form the element region A first initial matrix doped region and a second initial matrix doped region are formed in the electrostatic protection region; and a matrix thermal approach step is performed to form the first matrix region and the second matrix region. The manufacturing method according to claim 5, wherein the step of forming the laminated structure includes: sequentially forming an initial insulating layer and an undoped semiconductor layer on the surface of the epitaxial layer; Forming the first heavily doped region in the undoped semiconductor layer to form an initial semiconductor layer; and removing a part of the initial insulating layer and a part of the initial semiconductor layer in the device region to form The laminated structure of the electrostatic protection zone. The manufacturing method according to claim 1, wherein the first heavily doped region, the first body region, and the second body region have the same conductivity type, and the first source region and the The second heavily doped regions have the same conductivity type. The manufacturing method according to claim 1, wherein the semiconductor layer is isolated from the epitaxial layer by the insulating layer, and the difference between the width of the semiconductor layer and the width of the insulating layer is less than 0.5 um. The manufacturing method according to claim 1, wherein in the step of forming the second heavily doped region in the semiconductor layer, the first heavily doped region is sandwiched between two second heavily doped regions. Between doped regions. A semiconductor device is divided into a device area and an electrostatic protection area, and the semiconductor device includes: an epitaxial layer, which includes a first substrate area located in the device area and an electrostatic protection area A second base region; a gate structure disposed in the device region and connected to at least the first base region; and an electrostatic protection layer disposed on a surface of the epitaxial layer and Isolated from the epitaxial layer, wherein the static electricity protection layer is located above the second base region, and the static electricity protection layer completely overlaps within the range of the second base region. The semiconductor device according to claim 10, wherein the electrostatic protection layer includes a first heavily doped region and a second heavily doped region, and the first heavily doped region and the second heavily doped region The interface of the zone is a PN junction. The semiconductor device according to claim 10, further comprising an insulating layer located between the electrostatic protection layer and the epitaxial layer, the insulating layer connected to the second base region, and The difference between the width of the electrostatic protection layer and the width of the insulating layer is less than 0.5um. The semiconductor device according to claim 10, wherein the gate structure is a trench gate structure or a planar gate structure. The semiconductor device according to claim 10, wherein the epitaxial layer further includes a first source region located in the device region, and the first source region is connected to the One side of the gate structure, and the first body region surrounds the first source region. The semiconductor device according to claim 14, wherein the second body region has an extension portion and is connected to the other side of the gate structure, and a second source region is located on the extension portion.

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