TW201436159A - Semiconductor element and manufacturing method and operating method of the same - Google Patents

Abstract

A semiconductor element and a manufacturing method and an operating method of the same are provided. The semiconductor element includes a substrate, a first well, a first heavily doping region, at least a second heavily doping region, a gate layer, a third heavily doping region, and a fourth heavily doping region. The first well and the third heavily doping region are disposed on the substrate. The first and fourth heavily doping regions are disposed in the first well. The second heavily doping region is disposed in the first heavily doping region. The gate layer is disposed on the first well. The first, third, and fourth heavily doping regions having a first type doping are separated from one another. The first well and the second heavily doping region have a second type doping complementary to the first type doping.

Description

Semiconductor component, manufacturing method and operating method thereof

The present disclosure relates to a semiconductor device, a method of fabricating the same, and a method of fabricating the same, and more particularly to a semiconductor device for electrostatic discharge (ESD) protection, a method of fabricating the same, and a method of operation.

Extended drain MOSFET (EDMOSFET), lateral double-diffused MOSFET (LDMOSFET) and reduced surface field (RESURF) technology due to extended drain metal etched semiconductor field effect transistor (EDMOSFET) Compatible with existing complementary metal oxide semiconductor (CMOS) processes, it is a high voltage component commonly used to make output drivers. The effectiveness of electrostatic discharge (ESD) of a typical high voltage device often depends on all widths and surface or side rules of the corresponding device.

A typical characteristic of a high voltage device is that it has a low on-state resistance ( Rdson), a high breakdown voltage, and a low holding voltage. During the event of an electrostatic discharge, the low on-resistance can concentrate the current of the electrostatic discharge on the surface of the device or on the edge of the drain region of the device. The action of high current and strong electric field will cause physical damage to the surface joint of the device. Surface or side rules may no longer increase due to the typical condition that low on-resistance must be met. Therefore, the protection of electrostatic discharge will be a big challenge.

In general, the high breakdown voltage characteristic of the high voltage device indicates that the breakdown voltage is higher than the operating voltage, and the trigger voltage Vt1 (trigger voltage, Vt1) is higher than the breakdown voltage. Therefore, the internal circuitry of the high voltage device may be at risk of damage during the electrostatic discharge before the high voltage device turns on the electrostatic discharge protection. The low-maintenance voltage characteristics of high-voltage devices cause power-on peak voltage or surge voltage to cause noise, and also make high-voltage devices in normal operation, possibly due to noise. Triggered, causing a latch-up. Since the distribution of the electric field is sensitive to circuit routing, such that the high voltage device may experience a field plate effect, during the event of the electrostatic discharge, the current of the electrostatic discharge is concentrated on the surface of the device or the bungee Possible on the edge of the area.

Techniques for improving the effectiveness of electrostatic discharge in high voltage devices, including the use of reticle or additional steps to create a larger size in a Bipolar Junction Transistor (BJT) component Polar bodies, and/or in metal oxide semiconductor transistors (MOS transistors), increase their surface or side rules.

Therefore, improving the structure for providing electrostatic discharge protection is a subject worthy of development.

The disclosure relates to a semiconductor device, a method of fabricating the same, and a method of operation. In the semiconductor device, a good electrostatic discharge (ESD) protection effect can be provided by providing a diode and an existing metal oxide semiconductor (MOS).

According to an embodiment of the present disclosure, a semiconductor component is proposed. The semiconductor device includes a substrate, a first well, a first heavily doped region, at least one second heavily doped region, a gate layer, a third heavily doped region, and a The fourth heavily doped region. The first well is disposed on the substrate, the first heavily doped region is disposed in the first well, the second heavily doped region is disposed in the first heavily doped region, the gate layer is disposed on the first well, and the third heavily doped The impurity region is disposed on the substrate, and the fourth heavily doped region is disposed in the first well. The first heavily doped region, the third heavily doped region, and the fourth heavily doped region have a first doping type and are separated from each other, and the first well and the second heavily doped region have a second doping type The first doped profile is complementary to the second doped profile.

According to another embodiment of the present disclosure, a method of fabricating a semiconductor device is proposed. The method of manufacturing a semiconductor element includes the following steps. Providing a substrate; forming a first well on the substrate; forming a first heavily doped region in the first well; forming at least one second heavily doped region in the first heavily doped region; forming a gate layer Forming a third heavily doped region on the substrate; and forming a fourth heavily doped region in the first well; wherein the first heavily doped region, the third heavily doped region, and the fourth heavy The doped regions have a first doping profile and are separated from each other. The first well and the second heavily doped region have a second doping profile, and the first doping profile is complementary to the second doping profile.

According to still another embodiment of the present disclosure, a method of operating a semiconductor device is proposed. The method for operating a semiconductor device includes: providing a semiconductor device, including a substrate, a first well, a first heavily doped region, at least one second heavily doped region, and a gate layer a third heavily doped region and a fourth heavily doped region; and applying a gate voltage to the gate layer and the fourth heavily doped region. In the semiconductor device, the first well is disposed on the substrate, the first heavily doped region is disposed in the first well, the second heavily doped region is disposed in the first heavily doped region, and the gate layer is disposed on the first well. The third heavily doped region is disposed on the substrate, and the fourth heavily doped region is disposed in the first well, and the first heavily doped region, the third heavily doped region, and the fourth heavily doped region have a first doping The patterns are separated from each other, and the first well and the second heavily doped region have a second doping profile, and the first doping profile is complementary to the second doping profile. When the gate voltage is higher than a reverse bias, a diode formed by the fourth heavily doped region and the first well is electrically conductive; when the gate voltage is lower than the reverse bias, A metal oxide semiconductor (MOS) formed by the first heavily doped region, the third heavily doped region, and the gate layer is electrically conductive.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

100, 200, 300, 400, 500, 600. . . Semiconductor component

110P. . . Substrate

121P. . . First well

123N, 223N, 323N. . . Second well

125N. . . Third well

131N. . . First heavily doped region

133P. . . Second heavily doped region

135N. . . Third heavily doped region

137N. . . Fourth heavily doped region

139P. . . Fifth heavily doped region

140. . . Gate layer

150d, 150g, 150s. . . Contact point

160. . . Field oxide layer

170, 270. . . Gate oxide layer

180N. . . First lightly doped region

223N-1. . . First area

223N-2. . . Second area

271. . . First gate oxide layer

273. . . Second gate oxide layer

2A-2A', 2B-2B', 2C-2C', 4A-4A', 4B-4B', 5B-5B', 6B-6B'. . . Section line

BJT. . . Double carrier transistor

D. . . Extreme

D1. . . distance

G. . . Gate extreme

NMOS. . . Gold oxide semiconductor component

S. . . Source extreme

T1, T2. . . thickness

Fig. 1 is a top view of a semiconductor element according to a first embodiment.
Fig. 2A is a cross-sectional view taken along line 2A-2A' of Fig. 1.
Fig. 2B is a cross-sectional view taken along line 2B-2B' of Fig. 1.
Fig. 2C is a cross-sectional view taken along line 2C-2C' of Fig. 1.
Fig. 3 is a top view of the semiconductor element according to the second embodiment.
Fig. 4A is a cross-sectional view taken along line 4A-4A' of Fig. 3.
Fig. 4B is a cross-sectional view taken along line 4B-4B' of Fig. 3.
Fig. 5A is a top view of the semiconductor element according to the third embodiment.
Figure 5B is a cross-sectional view taken along line 5B-5B' of Figure 5A.
Fig. 6A is a top view of the semiconductor element according to the fourth embodiment.
Figure 6B is a cross-sectional view taken along line 6B-6B' of Figure 6A.
Fig. 7 is a cross-sectional view showing a semiconductor device according to a fifth embodiment.
Figure 8 is a cross-sectional view showing a semiconductor device according to a sixth embodiment.
FIG. 9 is a circuit diagram of a semiconductor device in accordance with an embodiment.
FIG. 10A is a diagram showing an equivalent circuit of a semiconductor device according to an embodiment.
FIG. 10B is another equivalent circuit diagram of a semiconductor device according to an embodiment.

First embodiment

1 is a top view of the semiconductor device 100 according to the first embodiment, FIG. 2A is a cross-sectional view taken along line 2A-2A' of FIG. 1, and FIG. 2B is a cross-sectional view taken along line 1 2B-2B' is a cross-sectional view, and FIG. 2C is a cross-sectional view taken along line 2C-2C' of Fig. 1.

Please refer to Figures 1 and 2A~2C. The semiconductor device 100 includes a substrate 110P, a first well 121P, a first heavily doped region 131N, at least one second heavily doped region 133P, a gate layer 140, and a third heavily doped region 135N. And a fourth heavily doped region 137N. The first well 121P is disposed on the substrate 110P, the first heavily doped region 131N is disposed in the first well 121P, the second heavily doped region 133P is disposed in the first heavily doped region 131N, and the gate layer 140 is disposed in the first well 121N On one well 121P, the third heavily doped region 135N is disposed on the substrate 110P, and the fourth heavily doped region 137N is disposed in the first well 121P. The first heavily doped region 131N, the third heavily doped region 135N, and the fourth heavily doped region 137N have a first doping profile and are spaced apart from each other, and the first well 121P and the second heavily doped region 133P have a first The two doping type, the first doping type is complementary to the second doping type.

In the embodiment, the material of the substrate 110P is, for example, a P-type N or an N-type 矽. The material of the gate layer 140 and the fourth heavily doped region 137N is, for example, polysilicon. The first doping type is, for example, one of P-type doping or N-type doping, and the second doping type is, for example, the other different from the first doping type.

In the embodiment, the first heavily doped region 131N, the third heavily doped region 135N, and the fourth heavily doped region 137N are, for example, N type heavily doping regions (N+), the first well 121P and The second heavily doped regions 133P are, for example, a P type well and a P type heavily doping region (P+), respectively. The doping concentration of the first heavily doped region 131N, the second heavily doped region 133P, the third heavily doped region 135N, and the fourth heavily doped region 137N is greater than the doping concentration of the first well 121P.

In the embodiment, as shown in FIG. 1 , the second heavily doped region 133P is disposed in the first heavily doped region 131N, and both of them are electrically connected to the source terminal S at the same time, which can reduce the area of the source terminal S. And the periphery of the second heavily doped region 133P is adjacent to the first heavily doped region 131N, and a plurality of equivalent bipolar transistor (BJT) can be formed, thereby having better electrostatic discharge protection capability.

As shown in FIG. 1, the semiconductor device 100 further includes a plurality of contacts 150s. The contact points 150s are electrically connected to the first heavily doped region 131N and the second heavily doped region 133P to the source terminal S. In the embodiment, as shown in FIG. 1, the semiconductor device 100 includes a plurality of second heavily doped regions 133P in the first heavily doped region 131N, and the contact points 150s are alternately electrically connected to the second heavily doped regions. The first heavily doped region 131N between the impurity region 133P and each of the second heavily doped regions 133P. In an embodiment, the ratio of the number of contacts 150s electrically connected to the first heavily doped region 131N to the number of electrically connected to the second heavily doped region 133P is about 1:1. The material of the contact point 150s is, for example, tungsten.

In the embodiment, as shown in FIG. 1, the periphery of the contact point 150s completely falls into the second heavily doped region 133P, and the size of the contact point 150s is smaller than the size of the second heavily doped region 133P, which can prevent the subsequent process. The problem of misalignment.

In the embodiment, as shown in FIGS. 1 and 2A-2C, the gate layer 140 and the fourth heavily doped region 137N are electrically connected to the gate terminal G via the contact point 150g, and the third heavily doped region 135N is via the contact point 150d. Electrically connected to the 汲 extreme D. In the embodiment, the distance D1 between the contact point 150d and the gate layer 140 is about 3.5 micrometers (μm).

In the embodiment, as shown in FIG. 2C, the fourth heavily doped region 137N is disposed in the first well 121P and has a junction with the first well 121P, the fourth heavily doped region 137N and the first well. 121P forms a clamp diode.

As shown in FIGS. 1 and 2A-2B, in one embodiment, the semiconductor device 100 further includes a second well 123N, and the second well 123N is disposed in the third heavily doped region 135N and extends toward the substrate 110P. The doping concentration of the third heavily doped region 135N is greater than the doping concentration of the second well 123N. In an embodiment, the second well 123N has a first doping profile, such as an N-type well. The second well 123N can change the current effect, making the electrostatic discharge current flow more easily, and the breakdown voltage can also be lowered.

As shown in FIGS. 1 and 2A-2C, in one embodiment, the semiconductor device 100 further includes a third well 125N, and the third well 125N is disposed between the substrate 110P and the third heavily doped region 135N. In an embodiment, the third well 125N has a first doping profile, such as a deep N type well, and the second well 123N extends into the third well 125N. The doping concentrations of the first heavily doped region 131N, the second heavily doped region 133P, the third heavily doped region 135N, and the fourth heavily doped region 137N are greater than the doping concentrations of the second well 123N and the third well 125N.

In an embodiment, the semiconductor device 100 further includes a field oxide layer 160 disposed between the first well 121P and the third heavily doped region 135N. The material of the field oxide layer 160 is, for example, hafnium oxide (SiO ₂ ). . In the embodiment, as shown in FIGS. 2A-2B, the gate layer 140 is partially disposed on one of the field oxide layers 160. In an embodiment, the semiconductor device 100 further includes a gate oxide layer 170 disposed between the gate layer 140 and the third well 125N adjacent to the junction of the first well 121P and the third well 125N. At the office.

Second embodiment

3 is a top view of the semiconductor device 200 according to the second embodiment, FIG. 4A is a cross-sectional view taken along line 4A-4A' of FIG. 3, and FIG. 4B is a cross-sectional view taken along line 3 Sectional view of 4B-4B'. The semiconductor element 200 of the present embodiment is different from the semiconductor element 100 of the first embodiment described above in the design of the second well 223N, and the rest of the same is not repeated.

As shown in FIGS. 3 and 4A-4B, in the semiconductor device 200, the second well 223N includes a first region 223N-1 and a second region 223N-2, and the first region 223N-1 and the second region 223N-2 are in contact with each other. Separated. In the embodiment, as shown in FIG. 3, the first region 223N-1 and the second region 223N-2 are spaced apart from each other to expose the surface of the intermediate portion of the third heavily doped region 135N.

The electrostatic discharge generally occurs from the middle portion of the surface of the element. Therefore, in the embodiment, the first region 223N-1 and the second region 223N-2 of the second well 223N are spaced apart from each other to expose the third heavily doped region 135N. The surface of the middle portion, the resistance of the second well 223N is lower than the resistance of the third heavily doped region 135N, and is relatively easy to be electrically conductive, which can help the electrostatic discharge current generated in the middle portion of the surface of the component to be the first on both sides. The region 223N-1 and the second region 223N-2 further enhance the effect of electrostatic protection.

Third embodiment

Fig. 5A is a top view of the semiconductor device 300 according to the third embodiment, and Fig. 5B is a cross-sectional view taken along line 5B-5B' of Fig. 5A. The semiconductor element 300 of the present embodiment is different from the semiconductor element 200 of the second embodiment described above in the design of the fifth heavily doped region 139P, and the rest of the same is not repeated.

As shown in FIGS. 5A-5B, the semiconductor device 300 further includes at least one fifth heavily doped region 139P, and the fifth heavily doped region 139P is disposed in the third heavily doped region 135N and located in the first region 223N-1 and Between the second regions 223N-2. The fifth heavily doped region 139P has a second doped type, such as a P-type heavily doped region. In this way, a parasitic silicon control rectifier (SCR) can be generated to contribute to electrostatic discharge protection.

In the embodiment, as shown in FIG. 5A, the semiconductor device 300 includes, for example, four fifth heavily doped regions 139P on both sides of the contact point 150d between the first region 223N-1 and the second region 223N-2, respectively. . The third heavily doped region 135N and the fifth heavily doped region 139P are electrically connected to the 汲 terminal D via the contact point 150d.

Fourth embodiment

Fig. 6A is a top view of the semiconductor device 400 according to the fourth embodiment, and Fig. 6B is a cross-sectional view taken along line 6B-6B' of Fig. 6A. The semiconductor device 400 of the present embodiment is different from the semiconductor device 100 of the first embodiment described above in the design of the first lightly doping region 180N, and the rest of the same is not repeated.

As shown in FIG. 6B, the semiconductor device 400 further includes a first lightly doped region 180N, and the first lightly doped region 180N is disposed between the first well 121P and the fourth heavily doped region 137N. The first lightly doped region 180N has a first doped type, such as an N-type lightly doped region. In an embodiment, the first lightly doped region 180N completely encapsulates the fourth heavily doped region 137N, while the first well 121P and the fourth heavily doped region 137N are completely separated. As a result, the breakdown voltage of the entire semiconductor element can be increased to, for example, 15 to 30 volts.

Fifth embodiment

Fig. 7 is a cross-sectional view showing the semiconductor device 500 according to the fifth embodiment. The semiconductor device 500 of the present embodiment is different from the semiconductor device 100 of the first embodiment described above in the design of the second well 323N, and the rest of the same is not repeated.

As shown in FIG. 7, in the semiconductor device 500, the second well 323N is disposed on the substrate 110P, and the third heavily doped region 135N is disposed in the second well 323N. The second well 323N has a first doping profile, such as an N-type well. In the embodiment, the first well 121P is adjacent to the substrate 110P and the second well 323N.

Sixth embodiment

FIG. 8 is a cross-sectional view showing the semiconductor device 600 according to the sixth embodiment. The semiconductor device 600 of the present embodiment is different from the semiconductor device 100 of the first embodiment described above in the design of the gate oxide layer 270, and the rest of the same portions will not be repeatedly described.

As shown in FIG. 8, the gate oxide layer 270 includes a first gate oxide layer portion 271 and a second gate oxide layer portion 273. The gate oxide layer 270 is disposed between the gate layer 140 and the third well 125N adjacent to the junction of the first well 121P and the third well 125N. The first gate oxide layer portion 271 is disposed between the gate layer 140 and the first well 121P, and the second gate oxide layer portion 273 is disposed between the first gate oxide layer portion 271 and the field oxide layer 160. . The thickness T1 of the first gate oxide layer section 271 is smaller than the thickness T2 of the second gate oxide layer section 273.

In the embodiment, the thickness T1 of the first gate oxide layer portion 271 is, for example, 0.008 to 0.02 μm, and the thickness T2 of the second gate oxide layer portion 273 is, for example, 0.025 to 0.09 μm. As a result, the withstand voltage capability of the entire component can be improved, so that the breakdown voltage of the semiconductor component can be greatly increased by about 10 volts.

The P-type well in the foregoing embodiment may also be replaced by a P-type body implantation to form a laterally diffused metal oxide semiconductor. The N-type deep well in the foregoing embodiment may also be replaced by an N-type well or an N-type well having an N type buried layer (NBL).

FIG. 9 is a circuit diagram of a semiconductor device in accordance with an embodiment. As shown in FIG. 9, the dotted portion is a circuit diagram of the semiconductor device of the embodiment of the present invention, wherein the fourth heavily doped region 137N and the first well 121P form a diode, the first heavily doped The region 131N, the third heavily doped region 135N, and the gate layer 140 form a metal oxide semiconductor (MOS). The diode has an impedance of at least 0.7 volts (V) in the forward bias and an impedance of at least 12-20 volts in the reverse bias.

In an embodiment, the method of operating a semiconductor device includes the steps of: providing a semiconductor device as described in the foregoing embodiments, and applying a gate voltage to the gate layer 140 and the fourth heavily doped region 137N. When the gate voltage is higher than a reverse bias, the two-pole system is electrically conductive; when the gate voltage is lower than a reverse bias, the metal-oxide semiconductor is electrically conductive. The reverse bias is, for example, 12V. In this way, the gate oxide layer can be protected from high voltage damage.

The semiconductor element of the embodiment can be used as an electrostatic discharge protection device. 10A is an equivalent circuit diagram of a semiconductor device according to an embodiment, and FIG. 10B is another equivalent circuit diagram of a semiconductor device according to an embodiment.

As shown in FIG. 10A, the semiconductor element ESD of the embodiment is electrically connected to another MOS device NMOS. When a positive ESD is generated in the element, the NMOS NMOS is a large-width extended drain N-type metal oxide semiconductor (large width EDNMOS), the fourth heavily doped region 137N and the first well 121P. The formed clamp diode has an RC coupling in the reverse bias voltage and a parasitic capacitance formed between the drain and the gate of the large-width extended-drain N-type metal oxide semiconductor, so that the MOS device is formed. Since the NMOS is electrically turned on from the gate, the positive electrostatic discharge current can be smoothly grounded via the NMOS device NMOS.

Furthermore, when a positive electrostatic discharge is generated, as shown in FIG. 10A, a parasitic NPN bipolar transistor BJT is also generated, and the positive electrostatic discharge current can be smoothly grounded via the bipolar transistor BJT. Moreover, the trigger voltage of the bipolar transistor BJT is lower than the trigger voltage of the large-width extension-drain N-type metal oxide semiconductor (such as the MOS semiconductor NMOS shown in FIG. 10A), so that it can be reached in the MOS device NMOS. The positive electrostatic discharge current is directed to the bipolar transistor BJT before the breakdown voltage, so that the MOS semiconductor device NMOS is protected by good electrostatic discharge. That is to say, the positive electrostatic discharge current can be grounded from two paths, and the positive electrostatic discharge energy can be grounded via the MOS semiconductor element NMOS, and the positive electrostatic discharge energy can also be grounded via the bipolar transistor BJT.

When a negative electrostatic discharge (negative ESD) occurs in the element, as shown in FIG. 10B, the MOS semiconductor element NMOS and the semiconductor element ESD generate a plurality of equivalent diodes. The diode has good electrostatic discharge protection capability, so the semiconductor component of the embodiment also has good protection against negative electrostatic discharge.

In practical applications, a plurality of MOS devices may be included in the semiconductor device, and only a few of the plurality of MOS devices are selected to be improved according to the embodiment of the present invention, so that the entire semiconductor device can have good static electricity. The discharge protection effect, and the semiconductor element modified as an electrostatic protection element can still have a predetermined operational function of the MOS element. In this way, it is possible to reduce the size of the entire semiconductor device without additionally providing an electrostatic discharge protection element.

The following is a method of fabricating a semiconductor device of some embodiments, which are for illustrative purposes only and are not intended to limit the invention. Those having ordinary knowledge may modify or change the steps as needed according to the actual implementation.

Please refer to Figures 1 and 2A~2C. In an embodiment, the manufacturing method of the semiconductor device 100 includes the following steps: providing a substrate 110P; forming a first well 121P on the substrate 110P; forming a first heavily doped region 131N in the first well 121P; forming at least a second weight The doped region 133P is in the first heavily doped region 131N; the gate layer 140 is formed on the first well 121P; the third heavily doped region 135N is formed on the substrate 110P; and the fourth heavily doped region 137N is formed. One well 121P inside. The first heavily doped region 131N, the third heavily doped region 135N, and the fourth heavily doped region 137N have a first doping type and are separated from each other, and the first well 121P and the second heavily doped region 133P have The second doping profile is complementary to the second doping profile.

In one embodiment, as shown in FIGS. 1 and 2A to 2C, a plurality of contacts 150s may be formed to electrically connect the first heavily doped region 131N and the second heavily doped region 133P to the source terminal. S.

In one embodiment, as shown in FIGS. 1 and 2A-2C, the second well 123N is further formed in the third heavily doped region 135N and extends toward the substrate 110P, wherein the second well 123N has the first doping type. .

In one embodiment, as shown in FIGS. 1 and 2A-2C, a third well 125N may be formed between the substrate 110P and the third heavily doped region 135N, wherein the third well 125N has a first doping type. The second well 123N extends into the third well 125N.

In one embodiment, as shown in FIGS. 1 and 2A-2C, a field oxide layer 160 may be formed between the first well 121P and the third heavily doped region 135N, and a gate oxide layer 170 may be formed on the gate layer. Between 140 and the third well 125N are adjacent to the junction of the first well 121P and the third well 125N.

In an embodiment, the step of forming the field oxide layer 160 may also form a shallow trench isolation (STI) replacement.

In one embodiment, as shown in Figures 3 and 4A-4B, a second well 223N can be formed, including a first region 223N-1 and a second region 223N-2 that are spaced apart from each other.

In one embodiment, as shown in FIGS. 5A-5B, at least one fifth heavily doped region 139P may be formed in the third heavily doped region 135N and located in the first region 223N-1 and the second region 223N-2. Between the fifth heavily doped regions 139P has a second doping profile.

In one embodiment, as shown in FIGS. 6A-6B, the first lightly doped region 180N may be formed between the first well 121P and the fourth heavily doped region 137N, wherein the first lightly doped region 180N has a first A doped form.

In one embodiment, as shown in FIG. 7, a second well 323N may be formed on the substrate 110P, and a third heavily doped region 135N may be disposed in the second well 323N. The second well 323N has a first doping profile.

In an embodiment, the first well 121P and the second well 323N are fabricated, for example, in a twin well process, without adding an additional mask or step, wherein the process may also include an epi process, a single Single poly process and/or double poly process.

In one embodiment, as shown in FIG. 8, a gate oxide layer 270 can be formed. The method of manufacturing the gate oxide layer 270 is, for example, the steps of forming a first gate oxide layer portion 271 between the gate layer 140 and the first well 121P, and forming a second gate oxide layer portion 273 at the first gate Between the pole oxide layer section 271 and the field oxide layer 160, the thickness T1 of the first gate oxide layer section 271 is smaller than the thickness T2 of the second gate oxide layer section 273.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100. . . Semiconductor component

110P. . . Substrate

121P. . . First well

123N. . . Second well

131N. . . First heavily doped region

133P. . . Second heavily doped region

135N. . . Third heavily doped region

137N. . . Fourth heavily doped region

140. . . Gate layer

150d, 150g, 150s. . . Contact point

160. . . Field oxide layer

2A-2A', 2B-2B', 2C-2C'. . . Section line

D1. . . distance

Claims (10)

A semiconductor component comprising:
a substrate;
a first well disposed on the substrate;
a first heavily doping region disposed in the first well;
At least one second heavily doped region disposed in the first heavily doped region;
a gate layer disposed on the first well;
a third heavily doped region disposed on the substrate; and a fourth heavily doped region disposed in the first well;
The first heavily doped region, the third heavily doped region, and the fourth heavily doped region have a first doping profile and are separated from each other, the first well and the second heavily doped region There is a second doping profile, the first doping profile being complementary to the second doping profile. The semiconductor device of claim 1, further comprising a plurality of contacts electrically connecting the first heavily doped region and the second heavily doped region to a source terminal. The semiconductor device of claim 1, further comprising a second well disposed in the third heavily doped region and extending toward the substrate, wherein the second well has the first doping type. The semiconductor device of claim 3, further comprising a third well disposed between the substrate and the third heavily doped region, wherein the third well has the first doping type, The second well extends into the third well. The semiconductor device of claim 3, wherein the second well comprises a first region and a second region, the first region and the second region are separated from each other, and the semiconductor component further comprises at least A fifth heavily doped region is disposed in the third heavily doped region and between the first region and the second region, wherein the fifth heavily doped region has the second doped type. The semiconductor device of claim 1, further comprising a first lightly doping region disposed between the first well and the fourth heavily doped region, wherein the first light The doped region has the first doped form. The semiconductor device of claim 1, further comprising a second well disposed on the substrate, wherein the third heavily doped region is disposed in the second well, and the second well has the first Doping type. For example, the semiconductor component described in claim 1 of the patent scope further includes:
An oxide layer disposed between the first well and the third heavily doped region; and a gate oxide layer comprising:
a first gate oxide layer disposed between the gate layer and the first well; and a second gate oxide layer disposed in the first gate oxide layer and the field oxide Between layers;
Wherein the thickness of the first gate oxide layer segment is less than the thickness of the second gate oxide layer segment. A method of manufacturing a semiconductor device, comprising:
Providing a substrate;
Forming a first well on the substrate;
Forming a first heavily doped region in the first well;
Forming at least one second heavily doped region in the first heavily doped region;
Forming a gate layer on the first well;
Forming a third heavily doped region on the substrate; and forming a fourth heavily doped region in the first well;
The first heavily doped region, the third heavily doped region, and the fourth heavily doped region have a first doping profile and are separated from each other, the first well and the second heavily doped region There is a second doping profile, the first doping profile being complementary to the second doping profile. A method of operating a semiconductor component, comprising:
Providing a semiconductor component, including:
a substrate;
a first well disposed on the substrate;
a first heavily doping region disposed in the first well;
At least one second heavily doped region disposed in the first heavily doped region;
a gate layer disposed on the first well;
a third heavily doped region disposed on the substrate; and a fourth heavily doped region disposed in the first well;
The first heavily doped region, the third heavily doped region, and the fourth heavily doped region have a first doping profile and are separated from each other, the first well and the second heavily doped region a second doping profile, the first doping profile being complementary to the second doping profile; and applying a gate voltage to the gate layer and the fourth heavily doped region;
Wherein, when the gate voltage is higher than a reverse bias, a diode formed by the fourth heavily doped region and the first well is electrically conductive; when the gate voltage is Below the reverse bias, a metal oxide semiconductor (MOS) formed by the first heavily doped region, the third heavily doped region, and the gate layer is electrically conductive.