CN111384148A - Semiconductor assembly and its manufacturing method - Google Patents

Semiconductor assembly and its manufacturing method Download PDF

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Publication number
CN111384148A
CN111384148A CN201811625563.4A CN201811625563A CN111384148A CN 111384148 A CN111384148 A CN 111384148A CN 201811625563 A CN201811625563 A CN 201811625563A CN 111384148 A CN111384148 A CN 111384148A
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region
layer
substrate
heavily doped
electrostatic protection
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李立民
徐献松
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Wuxi U Nikc Semiconductor Co ltd
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Wuxi U Nikc Semiconductor Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses a semiconductor assembly and a manufacturing method thereof. The method for manufacturing a semiconductor component comprises at least the following steps. An epitaxial layer is formed on a substrate, and the epitaxial layer is divided into at least one device region and an electrostatic protection region. A first substrate region is formed in the component region and a second substrate region is formed in the electrostatic protection region. And forming a laminated structure positioned in the electrostatic protection region on the surface of the epitaxial layer, wherein the laminated structure comprises an insulating layer and a semiconductor layer positioned on the insulating layer, the semiconductor layer is provided with a first heavily doped region, at least one second heavily doped region is formed, and the semiconductor layer and the at least one second heavily doped region form an electrostatic protection layer together, the electrostatic protection layer is positioned above the second substrate region, and the electrostatic protection layer is completely overlapped in the range of the second substrate region.

Description

Semiconductor assembly and its manufacturing method
Technical Field
The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly, to a semiconductor device having an electrostatic discharge protection layer and a method for fabricating the same.
Background
In the application field of semiconductor power devices, the electrostatic discharge protection capability of the semiconductor power device has become an important index. Some small signal semiconductor power devices have a smaller chip size, and thus have a poor electrostatic discharge protection capability, even fail to meet the minimum standard of electrostatic discharge protection. Although some semiconductor power devices have larger chip size and thus larger esd protection capability, they may need to be operated in a harsher environment (e.g., dry environment with a relative humidity of less than 65% or dusty environment), and thus have higher requirements for esd protection capability.
Therefore, in the prior art, the esd protection structure is integrated into the semiconductor power device to increase the endurance of the semiconductor power device against esd. However, in the conventional process, the position of the esd protection structure is easily shifted from the predetermined position due to the limitation of the process conditions and the process margin (process window). In addition, in the conventional semiconductor power device, the electrostatic discharge protection structure is directly connected to the drift region and the body region, and an arc interface extending along the thickness direction of the epitaxial layer is formed between the drift region and the body region.
Therefore, when the semiconductor power component operates, the electric field strength at the arc-shaped interface between the drift region and the body region is strong, causing a breakdown phenomenon to often occur in the region near the arc-shaped interface, and lowering the withstand voltage of the semiconductor power component itself.
On the other hand, for the conventional semiconductor power device, breakdown voltage (breakdown voltage) and on-resistance (on-resistance) are important parameters, wherein the on-resistance affects the on-loss of the semiconductor power device. The present industry is moving towards increasing the doping concentration of the drift region to further reduce the on-resistance of the semiconductor power device. However, the conventional semiconductor power device has a relatively low withstand voltage after the esd protection structure is integrated, and thus it is more difficult to meet the current trend in the industry.
Disclosure of Invention
One of the technical problems to be solved by the present invention is to overcome the problem of low withstand voltage of a semiconductor device having an esd protection structure.
In order to solve the above technical problems, one of the technical solutions of the present invention is to provide a method for manufacturing a semiconductor device. The aforementioned manufacturing method includes the following steps. An epitaxial layer is formed on a substrate, and the epitaxial layer is divided into at least one device region and an electrostatic protection region. A first substrate region is formed in the assembly region and a second substrate region is formed in the electrostatic protection region. A laminated structure is formed on the surface of the epitaxial layer, the laminated structure is located in the electrostatic protection area and comprises an insulating layer and a semiconductor layer located on the insulating layer, and the semiconductor layer is provided with a first heavily doped area. At least one second heavily doped region is formed in the semiconductor layer, and the second heavily doped region and the first heavily doped region jointly form an electrostatic protection layer. The static protection layer is positioned above the second substrate area, and the static protection layer is completely overlapped in the range of the second substrate area.
Another technical solution adopted by the present invention is to provide a semiconductor device, which is divided into a device region and an electrostatic protection region, and the semiconductor device includes an epitaxial layer, a gate structure and an electrostatic protection layer. The epitaxial layer includes a first substrate region in the device region and a second substrate region in the electrostatic protection region. The grid structure is arranged in the component area and is at least connected with the first substrate area. The electrostatic protection layer is disposed on a surface of the epitaxial layer and isolated from the epitaxial layer. The static protection layer is positioned above the second substrate area, and the static protection layer is completely overlapped in the range of the second substrate area.
The semiconductor assembly and the manufacturing method thereof have the advantages that the semiconductor assembly with the electrostatic protection layer can meet the electrostatic discharge protection standard and have higher withstand voltage through the technical means that the electrostatic protection layer is completely overlapped in the range of the second base region.
For a better understanding of the features and technical content of the present invention, reference should be made to the following detailed description of the invention and accompanying drawings, which are provided for purposes of illustration and description only and are not intended to limit the invention.
Drawings
Fig. 1 is a flow chart of a semiconductor device according to an embodiment of the invention. Fig. 2A is a schematic partial cross-sectional view of a semiconductor device in a manufacturing process according to an embodiment of the invention.
Fig. 2B is a partial cross-sectional view of a semiconductor device in a manufacturing process according to an embodiment of the present invention.
Fig. 2C is a schematic partial cross-sectional view of a semiconductor device in a manufacturing process according to an embodiment of the invention.
Fig. 2D is a schematic partial cross-sectional view of a semiconductor device in a manufacturing process according to an embodiment of the invention.
Fig. 2E is a schematic partial cross-sectional view of a semiconductor device in a manufacturing process according to an embodiment of the invention.
Fig. 2F is a schematic partial cross-sectional view of a semiconductor device in a manufacturing process according to an embodiment of the invention.
Fig. 2G is a schematic partial cross-sectional view of a semiconductor device in a manufacturing process according to an embodiment of the invention.
Fig. 3 is a partial cross-sectional view of a semiconductor device according to an embodiment of the invention.
Fig. 4 is a partial cross-sectional view of a semiconductor device in a manufacturing process according to another embodiment of the present invention.
Fig. 5 is a schematic partial cross-sectional view of a semiconductor device in a manufacturing process according to yet another embodiment of the invention.
Fig. 6 is a partial cross-sectional view of a semiconductor device in accordance with an embodiment of the present invention.
Detailed Description
Please refer to fig. 1. Fig. 1 is a flow chart of a method of manufacturing a semiconductor device according to an embodiment of the invention. Specifically, the present invention provides a method for manufacturing a semiconductor device having an electrostatic discharge protection layer, and at least comprises the following steps.
In step S100, an epitaxial layer is formed on a substrate, wherein the epitaxial layer is divided into at least a device region and an electrostatic discharge protection region. In step S110, a first substrate region and a second substrate region are formed in the component region and the esd protection region, respectively. In step S120, a stacked structure located in the esd protection region is formed on the surface of the epitaxial layer, where the stacked structure includes an insulating layer and a semiconductor layer located on the insulating layer, and the semiconductor layer has a first heavily doped region. In step S130, at least a second heavily doped region is formed in the semiconductor layer, and the second heavily doped region and the first heavily doped region together form an electrostatic protection layer. The static protection layer is positioned above the second substrate area, and the static protection layer is completely overlapped in the range of the second substrate area.
Specific steps in the method of manufacturing a semiconductor device will be described in detail below. In the present embodiment, a trench semiconductor power device is taken as an example to describe the manufacturing method of the present invention in detail.
Referring to fig. 2A, a partial cross-sectional view of a semiconductor device in a manufacturing process according to an embodiment of the invention is shown. An epitaxial layer (epitaxial layer)11 has been formed on the substrate 10. The substrate 10 is, for example, a silicon substrate (silicon substrate) having a high doping concentration of first-type conductivity impurities as a drain (drain) of a semiconductor power device.
The first conductive type impurity may be an N-type or P-type conductive type impurity. Assuming that the substrate 10 is a silicon substrate, the N-type conductivity impurity is a pentavalent ion, such as a phosphorous ion or an arsenic ion, and the P-type conductivity impurity is a trivalent ion, such as a boron ion, an aluminum ion, or a gallium ion.
If the trench power semiconductor device is an N-type power mosfet, the substrate 10 is doped with N-type conductivity impurities. On the other hand, if the trench power semiconductor device is a P-type trench power mosfet, the substrate 10 is doped with P-type conductivity impurities.
The epitaxial layer 11 ″ is formed on the substrate 10 and has a low concentration of the first-type conductive impurities. In the case of an NMOS transistor, the substrate 10 is heavily doped N-type (N)+) The epitaxial layer 11' is doped with low concentration N-type dopant (N)-). On the contrary, the PMOS transistor is used asFor example, the substrate 10 is heavily doped P-type (P)+doping), and the epitaxial layer 11' is doped with low concentration P-type (P)-doping)。
In the present embodiment, the epitaxial layer 11 ″ has a surface 11s, and the epitaxial layer 11 ″ is divided into a device region R1 and an esd protection region R2. It should be noted that, although fig. 2A shows that the esd protection region R2 is surrounded by the device region R1, the invention is not limited to the arrangement positions of the esd protection region R2 and the device region R1. In another embodiment, the device region R1 may be located on one side of the esd protection region R2. In yet another embodiment, the component region R1 may be surrounded by the electrostatic protection region R2. That is, the configuration positions and shapes of the esd protection region R2 and the device region R1 may be changed according to actual requirements, and the invention is not limited thereto.
As shown in fig. 2A, at least one gate structure 12 (fig. 2A shows a plurality of examples) has been formed in the device region R1, and the gate structure 12 includes a gate insulating layer 120 and a gate electrode 121. In addition, the gate structure 12 may be a planar gate structure or a trench gate structure.
In the present embodiment, the gate structure 12 is a trench gate structure. In the step of forming the gate structure 12, a plurality of trenches 11h are formed in the epitaxial layer 11 ″ in the device region R1, and then the gate insulating layer 120 and the gate 121 are sequentially formed in the trenches 11 h.
As shown in fig. 2A, a body doping step 20 is performed on the epitaxial layer 11 ″ to form a first initial body doping region 111 'in the device region R1 and a second initial body doping region 112' in the esd protection region R2.
Referring to fig. 2B, an initial insulating layer 13' and an undoped semiconductor layer 14P are sequentially formed on the surface 11s of the epitaxial layer 11 ″. The initial insulating layer 13' covers the entire surface 11s of the epitaxial layer 11 ". The material of the initial insulating layer 13' may be selected from oxides or nitrides, such as: silicon oxide or silicon nitride.
The thickness of the initial insulating layer 13' is adjusted according to the gate-source bias (Vgs) of the semiconductor power device. The greater the gate-source voltage (Vgs) of the semiconductor power device, the thicker the thickness of the initial insulating layer 13'.
An undoped semiconductor layer 14P is formed on the initial insulating layer 13' to be isolated from the epitaxial layer 11 ". The undoped semiconductor layer 14P may be an undoped polysilicon layer. Thereafter, a heavy doping step 30 is performed on the undoped semiconductor layer 14P.
Referring to fig. 2C, a substrate thermal drive-in step is performed to form a first substrate region 111 and a second substrate region 112 in the epitaxial layer 11'. On the other hand, in the substrate heat-drive-in step, the first heavily doped region 140' is also formed in the undoped semiconductor layer 14P simultaneously, so as to form an initial semiconductor layer 14 ".
In the present embodiment, in both the heavy doping step 30 and the base doping step 20, impurities having the same conductivity type are used. That is, the first heavily doped region 140', the first body region 111, and the second body region 112 all have the same conductivity type, but by way of example only, the invention is not limited thereto. In other embodiments, additional process steps of different conductivity types may be added to the first heavily doped region 140', the first body region 111, and the second body region 112 to achieve the doping result.
It should be noted that, in the present embodiment, the step of forming the initial semiconductor layer 14 ″ is completed before the substrate thermal drive-in step is performed. However, in other embodiments, the substrate thermal drive-in step may be performed first to form the first substrate region 111 and the second substrate region 112. Thereafter, another thermal drive-in step is performed to form the initial semiconductor layer 14 ″ having the first heavily doped region 140'.
In other embodiments, the gate structure 12 in the device region R1 may be formed after the first and second substrate regions 111 and 112 are formed in the epitaxial layer 11 ″.
As shown in fig. 2C, the first substrate region 111 is located in the device region R1 of the epitaxial layer 11' and surrounds the gate structure 12. Other regions in the epitaxial layer 11 'form drift regions 110' of the trench semiconductor device. The second substrate region 112 is located within the electrostatic protection region R2 and is connected to the initial insulating layer 13'.
Referring to fig. 2D, a portion of the initial insulating layer 13 'and a portion of the initial semiconductor layer 14 ″ in the device region R1 are removed to form a stacked structure P1' in the esd protection region R2.
Specifically, a photoresist layer PR may be formed on the initial semiconductor layer 14 ″ to define the position of the stack P1 ', and an etching step is performed to remove a portion of the initial semiconductor layer 14 ″ and a portion of the initial insulating layer 13' in the device region R1. The other portion of the initial semiconductor layer 14 ″ covered by the photoresist layer PR and the initial insulating layer 13 'are remained to form the stacked structure P1' in the ESD protection region R2.
Accordingly, the stacked structure P1 'includes the semiconductor layer 14' located in the esd protection region R2 and an insulating layer 13, and the semiconductor layer 14 'has the first heavily doped region 140'. By forming the stacked structure P1 'through the above steps, the position shift of the stacked structure P1' can be avoided, so that the semiconductor layer 14 'is directly contacted with the epitaxial layer 11'. In the present embodiment, the lateral width of the semiconductor layer 14' is substantially the same as the lateral width of the insulating layer 13. Specifically, the difference between the width of the semiconductor layer 14' and the width of the insulating layer 13 is less than 0.5 um.
Referring to fig. 2E, at least one second heavily doped region 141 is further formed in the semiconductor layer 14', such that the at least one second heavily doped region 141 and the first heavily doped region 140 together form an electrostatic protection layer 14. The electrostatic protection layer 14 is disposed on the insulating layer 13, and the electrostatic protection layer 14 and the insulating layer 13 together form an electrostatic protection stack P1.
In detail, a shielding pattern layer (not shown) may be formed on the semiconductor layer 14' in advance to define the position of the second heavily doped region 141. Thereafter, a second heavily doped region 141 is formed in the semiconductor layer 14' by sequentially performing a doping step and a thermal drive-in step.
The second heavily doped region 141 and the first heavily doped region 140 have opposite conductivity types, respectively. Therefore, a PN junction is formed at the interface between the second heavily doped region 141 and the first heavily doped region 140.
In the embodiment of fig. 2E, two second heavily doped regions 141 separated from each other are formed in the semiconductor layer 14', and the first heavily doped region 140 is located between the two second heavily doped regions 141, so as to form a triode (bipolar diode), such as: PNP triode or NPN triode.
In addition, in the step of forming the second heavily doped region 141, at least one first source region 113a (fig. 2E shows a plurality of regions) may be simultaneously formed in the device region R1. Accordingly, the first source region 113a and the second heavily doped region 141 have the same conductivity type.
It should be noted that the position of the second heavily doped region 141 can be adjusted by changing the shielding pattern layer, so as to form different electrostatic protection layers 14. Referring first to fig. 4, a cross-sectional view of a semiconductor device in a manufacturing process according to another embodiment of the invention is shown, which can be followed by the step of fig. 2D.
In the embodiment of fig. 4, only a second heavily doped region 141 is formed in the semiconductor layer 14' to form a PN junction diode (diode). Therefore, the esd protection layer 14 may be a transistor, a PN diode or other components as long as esd protection is achieved.
Referring again to fig. 5, a cross-sectional view of a semiconductor device in a manufacturing process according to another embodiment of the invention is shown and may be continued with the step of fig. 2D. In the step of forming the second heavily doped region 141, at least one first source region 113a (fig. 5 shows a plurality of) and at least one second source region 113b (fig. 5 shows two) may be simultaneously formed in the device region R1 and the esd protection region R2.
In the embodiment of fig. 5, the first source region 113a is located above the first body region 111 and is connected to the at least one gate structure 12. In addition, the second substrate region 112 has an extension portion 112a, and the extension portion 112a is connected to the gate structure 12 closest to the esd protection region R2. The second source region 113b is formed on the upper portion of the extension portion 112a and is connected to the gate structure 12 closest to the esd protection region R2.
It is noted that, through the above steps, a transistor structure can be formed in the device R1, and the esd protection stack P1 can be formed in the esd protection region R2. Accordingly, in the process steps of the embodiment of the invention, the step of forming the esd protection stack P1 can be integrated with the step of forming the transistor structure, thereby reducing the manufacturing cost.
Referring to fig. 2F, fig. 2G and fig. 3, a redistribution circuit structure is formed such that the transistor structure and the esd protection stack P1 can be electrically connected to an external control circuit. In detail, as shown in fig. 2F, an interlayer dielectric layer 15' is formed on the electrostatic protection layer 14 and the surface 11s of the epitaxial layer 11. Next, as shown in fig. 2G, a plurality of contact holes 15h are formed in the interlayer dielectric layer 15, and a plurality of conductive structures 16 are formed in the plurality of contact holes 15 h.
The conductive structure 16 includes a plurality of first conductive pillars 161 and a plurality of second conductive pillars 162. Each of the first conductive pillars 161 is electrically connected to the corresponding first source region 113a through the corresponding contact window 15 h. Each of the second conductive pillars 162 is electrically connected to the first heavily doped region 140 or the second heavily doped region 141 of the electrostatic protection layer 14 through the corresponding contact window 15 h. In addition, the first heavily doped region 140 may or may not be connected to the second conductive pillar 162, depending on the application requirements.
Referring to fig. 3, a partial cross-sectional view of a semiconductor device according to an embodiment of the invention is shown. In this embodiment, a pad set 17 is further formed on the interlayer dielectric layer 15. The pad set 17 includes a plurality of first pads 171 and a plurality of second pads 172. The first pad 171 is electrically connected to the first source region 113a and the second source region 113b through the corresponding first conductive pillar 161. The second pads 172 are electrically connected to the first heavily doped region 140 or the second heavily doped region 141 through the corresponding second conductive pillars 162.
Then, a passivation layer 18 is formed on the pad set 17. The passivation layer 18 has a plurality of openings, each opening exposes a corresponding first pad 171 (or second pad 172), so that the first pads 171 and the second pads 172 can be electrically connected to an external control circuit.
Accordingly, as shown in fig. 3, the embodiment of the present invention provides a semiconductor device M1 integrated with an electrostatic protection layer 14. The semiconductor device M1 is, for example, a trench mosfet, a lateral diffusion mosfet, or a planar mosfet.
The semiconductor device M1 can be divided into a device region R1 and an esd protection region R2. The area of the electrostatic protection region R2 is adjusted according to the actual application requirements. If the semiconductor device M1 is required to meet the higher esd protection specification, i.e. to have a larger esd tolerance, the area of the esd protection region R2 is larger.
The semiconductor device M1 includes a substrate 10, an epitaxial layer 11, a gate structure 12, and an esd protection stack P1. The epitaxial layer 11 is disposed on the substrate 10 and has a drift region 110, a first body region 111, a second body region 112, and a first source region 113 a. The drift region 110 is located on a side of the epitaxial layer 11 close to the substrate 10 and extends from the device region R1 to the esd protection region R2.
The first base region 111 is located within the assembly region R1 and on the side away from the substrate 10. That is, the first body region 111 is located above the drift region 110. In addition, the first source region 113a is located above the first body region 111 and connected to the surface 11s of the epitaxial layer 11.
The second body region 112 is located in the electrostatic protection region R2 and on a side of the epitaxial layer 11 away from the substrate 10, that is, above the drift region 110.
When the semiconductor device M1 is a trench mosfet, the epitaxial layer 11 further includes at least one trench 11h located in the device region R1, and the gate structure 12 is disposed in the trench 11 h.
As shown in fig. 3, the gate structure 12 includes a gate insulating layer 120 and a gate electrode 121. The gate insulating layer 120 covers an inner wall of the trench 11h to electrically insulate the gate 121 from the epitaxial layer 11. The gate structure 12 in the device region R1 is connected to the first body region 111 and the first source region 113 a.
In this embodiment, the second substrate region 112 is connected to the gate structure 12 closest to the esd protection region R2.
The esd protection stack P1 is disposed on the epitaxial layer 11 and located in the esd protection region R2 for protecting the semiconductor device M1 from esd damage. The esd protection stack P1 includes an insulating layer 13 and an electrostatic protection layer 14, and the insulating layer 13 is located between the electrostatic protection layer 14 and the epitaxial layer 11 to isolate the electrostatic protection layer 14 from the second substrate region 112. Accordingly, the insulating layer 13 is directly connected to the second substrate region 112.
In addition, since one end of the electrostatic protection layer 14 is at the same potential as the gate electrode 121, the thickness of the insulating layer 13 may be determined according to the source-gate bias voltage (Vgs) applied to the semiconductor device M1. The thickness of the insulating layer 13 needs to be thicker as the source-gate bias voltage (Vgs) is larger.
The electrostatic protection layer 14 includes at least one first heavily doped region 140 and at least one second heavily doped region 141. In one embodiment, the first heavily doped region 140 has the same conductivity type as the first body region 111 and the second body region 112, for example, both are P-type doped regions. The second heavily doped region 141 and the first source region 113a have the same conductivity type, for example, both are N-type doped regions, but the invention is not limited thereto. Additional process steps of different conductivity types may also be added to achieve the doping result.
In addition, the lateral width of the electrostatic shield 14 is substantially the same as the lateral width of the insulating layer 13. Further, the difference between the width of the electrostatic protection layer 14 and the width of the insulating layer 13 is less than 0.5 um. In one embodiment, the electrostatic protection layer 14 is located above the second substrate region 112, and the electrostatic protection layer 14 completely overlaps the second substrate region 112.
It should be noted that, compared to the conventional semiconductor power device, the electrostatic protection layer 14 of the embodiment of the present invention is located above the second body region and completely overlaps the second body region, the bottom of the electrostatic protection stack P1 of the embodiment of the present invention is not directly connected to the drift region 110, but only connected to the second body region 112. Therefore, in the electrostatic protection region R2, the interface formed between the second base region 112 and the drift region 110 extends substantially in the direction parallel to the surface 11 s.
Since the esd protection stack P1 of the semiconductor device M1 of the present invention is connected to only the second body region 112, when the semiconductor device M1 operates, the electric field intensity at the interface between the second body region 112 and the drift region 110 is relatively uniform, so that the semiconductor device M1 of the present embodiment has a relatively high breakdown voltage. Accordingly, compared to the conventional semiconductor power device, the semiconductor device M1 of the embodiment of the present invention has a certain voltage withstanding capability in addition to the esd protection capability.
Referring to fig. 6, a partial cross-sectional view of a semiconductor device according to another embodiment of the invention is shown. The same components in this embodiment as those in the embodiment of fig. 3 have the same reference numerals, and the description of the same parts is omitted.
The difference between this embodiment and the embodiment of fig. 3 is that in the semiconductor device M2 of this embodiment, the gate structure 12 is a planar gate structure. That is, the gate structure 12 is disposed on the surface 11s of the epitaxial layer 11. In addition, in the device region R1, the epitaxial layer 11 includes a plurality of first body regions 111 separated from each other, and each of the first source regions 113a is surrounded by a corresponding first body region 111.
In addition, in the present embodiment, the second substrate region 112 is connected to the gate structure 12 closest to the esd protection region R2. Specifically, the second body region 112 is connected to the gate insulating layer 120 of the gate structure 12.
The manufacturing method of the embodiment of the invention can also be used for forming the semiconductor component M2. Specifically, after the first and second substrate regions 111 and 112 are formed, the gate structure 12 may be formed on the surface 11s of the epitaxial layer 11 in the device region R1.
Accordingly, in the method of fabricating a semiconductor device according to the present invention, the sequence of steps can be adjusted according to the structure of the semiconductor device itself or the process requirements, as long as the second body region 112 can be formed under the esd protection stack P1 and completely overlapped therewith.
In summary, the semiconductor device and the manufacturing method thereof according to the present invention have the beneficial effects that the semiconductor device having the esd protection stack P1 can meet the esd protection standard and have a higher withstand voltage by the technical means of forming the second substrate region 112 in the esd protection region R2 and completely overlapping the esd protection layer in the second substrate region in the epitaxial layer 11 before forming the esd protection stack P1.
In addition, in the method for manufacturing a semiconductor device according to the embodiment of the invention, the step of forming the esd protection stack P1 in the esd protection region R2 can be integrated with the step of forming the transistor structure in the device R1, thereby reducing the manufacturing cost.
The disclosure is only a preferred embodiment of the invention and should not be taken as limiting the scope of the invention, so that the invention is not limited by the disclosure of the invention.
Description of the symbols
Semiconductor devices M1, M2
Substrate 10
Epitaxial layers 11, 11'
Component region R1
Electrostatic protection area R2
Channel 11h
Surface 11s
Drift regions 110, 110'
First substrate region 111
Second substrate region 112
Extension 112a
The first source region 113a
The second source region 113b
Gate structure 12
Gate insulating layer 120
Gate 121
Initial insulating layer 13'
Undoped semiconductor layer 14P
Laminated structure P1'
Initial semiconductor layer 14 "
Semiconductor layer 14'
Electrostatic protection stack P1
Insulating layer 13
Electrostatic shield 14
First heavily doped regions 140, 140'
Second heavily doped region 141
Interlayer dielectric layers 15, 15'
Contact window 15h
Conductive structure 16
First conductive post 161
Second conductive pillar 162
Pad set 17
First pad 171
Second pad 172
Protective layer 18
Matrix doping step 20
Heavy doping step 30
First initial matrix doped region 111'
Second initial matrix doped region 112'
Photoresist layer PR
Flow Steps S100 to S130

Claims (15)

1. A method of manufacturing a semiconductor device, comprising:
forming an epitaxial layer on a substrate, wherein the epitaxial layer is divided into at least one device region and an electrostatic protection region;
forming a first substrate region in the assembly region and a second substrate region in the electrostatic protection region;
forming a laminated structure on the surface of the epitaxial layer, wherein the laminated structure is positioned in the electrostatic protection region and comprises an insulating layer and a semiconductor layer positioned on the insulating layer, and the semiconductor layer is provided with a first heavily doped region; and
and forming at least one second heavily doped region in the semiconductor layer, wherein the second heavily doped region and the first heavily doped region together form a static protective layer, the static protective layer is positioned above the second substrate region, and the static protective layer is completely overlapped in the range of the second substrate region.
2. The method of claim 1, wherein the step of forming at least a second heavily doped region in the semiconductor layer comprises: and sequentially performing a doping step and a thermal drive-in step to simultaneously form at least a first source region in the first body region of the component region and a second heavily doped region in the semiconductor layer, wherein the interface of the first heavily doped region and the second heavily doped region is a PN junction.
3. The manufacturing method according to claim 2, further comprising: and forming at least one gate structure in the device region, wherein the second body region has an extension part and is connected with at least one gate structure, and simultaneously forming a second source region on the extension part in the step of forming the first source region.
4. The method of claim 3, wherein the gate structure is a trench gate structure or a planar gate structure.
5. The method of manufacturing of claim 1, wherein the step of forming the first and second substrate regions comprises:
performing a substrate doping step on the epitaxial layer to form a first initial substrate doping area in the device area and a second initial substrate doping area in the electrostatic protection area; and
and performing a substrate heat drive-in step to form the first substrate region and the second substrate region.
6. The manufacturing method according to claim 5, wherein the step of forming the laminated structure includes:
sequentially forming an initial insulating layer and an undoped semiconductor layer on the surface of the epitaxial layer;
forming the first heavily doped region in the undoped semiconductor layer to form an initial semiconductor layer; and
and removing a part of the initial insulating layer and a part of the initial semiconductor layer in the component area to form the laminated structure in the electrostatic protection area.
7. The method of claim 1, wherein the first heavily doped region, the first body region, and the second body region have a same conductivity type, and the first source region and the second heavily doped region have a same conductivity type.
8. The method according to claim 1, wherein the semiconductor layer is separated from the epitaxial layer by the insulating layer, and a difference between a width of the semiconductor layer and a width of the insulating layer is less than 0.5 um.
9. The manufacturing method according to claim 1, wherein in the step of forming the second heavily doped region in the semiconductor layer, the first heavily doped region is sandwiched between two of the second heavily doped regions.
10. A semiconductor device divided into a device region and an esd region, the semiconductor device comprising:
an epitaxial layer including a first substrate region in the device region and a second substrate region in the electrostatic protection region;
a gate structure disposed in the device region and connected to at least the first substrate region; and
and the electrostatic protection layer is arranged on one surface of the epitaxial layer and is isolated from the epitaxial layer, wherein the electrostatic protection layer is positioned above the second substrate area, and the electrostatic protection layer is completely overlapped in the range of the second substrate area.
11. The semiconductor device of claim 10, wherein the electrostatic protection layer comprises a first heavily doped region and a second heavily doped region, and an interface between the first heavily doped region and the second heavily doped region is a PN junction.
12. The semiconductor device of claim 10, further comprising an insulating layer between the electrostatic protection layer and the epitaxial layer, the insulating layer being coupled to the second substrate region, wherein a difference between a width of the electrostatic protection layer and a width of the insulating layer is less than 0.5 um.
13. The semiconductor device of claim 10, wherein the gate structure is a trench gate structure or a planar gate structure.
14. The semiconductor device of claim 10, wherein the epitaxial layer further comprises a first source region in the device region, the first source region being connected to one side of the gate structure, and the first body region surrounding the first source region.
15. The semiconductor device of claim 14, wherein the second body region has an extension and is connected to another side of the gate structure, and a second source region is located above the extension.
CN201811625563.4A 2018-12-28 2018-12-28 Semiconductor assembly and its manufacturing method Pending CN111384148A (en)

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