CN209249463U - Semiconductor subassembly - Google Patents

Abstract

The utility model discloses a kind of semiconductor subassembly.Semiconductor subassembly is divided into a component area and an electrostatic protection area.Semiconductor subassembly includes epitaxial layer, gate structure and static electricity shield layer.Epitaxial layer includes one second matrix area positioned at one first matrix area in component area and positioned at electrostatic protection area.Gate structure is set in component area, and is attached at least to first matrix area.Static electricity shield layer is set on a surface of epitaxial layer and is isolated with epitaxial layer.Static electricity shield layer is located above the second matrix area, and static electricity shield layer is completely overlapped within the scope of the second matrix area.There is the utility model the semiconductor subassembly of static electricity shield layer to meet electrostatic discharge protective standard, and can pressure resistance with higher.

Description

Semiconductor subassembly

Technical field

The utility model relates to a kind of semiconductor subassemblies, more particularly to a kind of semiconductor group with static electricity shield layer Part.

Background technique

In the application field of semiconductor power component, semiconductor power component, which has become ESD protection, attaches most importance to Want index.Some small signal semiconductor power components are poor to ESD protection because having lesser chip size, very To the minimum standard for being unable to reach electrostatic discharge (ESD) protection.Although part semiconductor (PCC) power has biggish chip size, and There can be biggish ESD protection, but may need (such as: the drying of relative humidity < 65% compared with harsh environment Environment or the more environment of dust) under operate, thus have higher want to the ESD protection of semiconductor power component It asks.

Therefore, in existing technology, ESD-protection structure is integrated into semiconductor power component, to increase Ability to bear of the semiconductor power component to static discharge.However, in existing processing procedure, due to process conditions and process latitudes degree The limitation of (process window), the position of ESD-protection structure are easy offset predetermined position.In addition, existing partly lead In body (PCC) power, ESD-protection structure can be directly connected to drift region and matrix area, and meeting between drift region and matrix area Form the arc-shaped interface extended along the thickness direction of epitaxial layer.

Therefore, when semiconductor power component operates, the electric field strength of the arc-shaped interface between drift region and matrix area Pressure resistance that is relatively strong, causing region of the collapse phenomenon often near arc-shaped interface to occur, and reduce semiconductor power component itself.

On the other hand, for existing semiconductor power component, breakdown voltage (breakdown voltage) and Conducting resistance (on-resistance) is more important parameter, and wherein conducting resistance will affect the conducting of semiconductor power component It is lost (conducting loss).Industry is tended to partly lead by the doping concentration for improving drift region to further decrease at present The conducting resistance of body (PCC) power.However, existing semiconductor power component has had after integrating ESD-protection structure There is relatively relatively low pressure resistance, it is more difficult to meet the trend of current industry.

Utility model content

The utility model wherein technical problem to be solved is, overcomes partly leading with electrostatic discharge protection structure The relatively low problem of the pressure resistance of body component.

In order to solve the above technical problems, wherein a technical solution is to provide a kind of half used by the utility model Conductor assembly is divided into a component area and an electrostatic protection area, and the semiconductor subassembly includes an epitaxial layer, a grid Pole structure and a static electricity shield layer.Epitaxial layer includes positioned at one first matrix area in component area and positioned at electrostatic protection area One second matrix area.Gate structure is set in component area, and is attached at least to the first matrix area.Static electricity shield layer is set to of heap of stone It is isolated on one surface of crystal layer and with epitaxial layer.Static electricity shield layer is located above second matrix area, and static electricity shield layer is complete Full weight is laminated within the scope of second matrix area.

The beneficial effects of the utility model are that semiconductor subassembly provided by the utility model passes through " electrostatic protection Layer it is completely overlapped within the scope of second matrix area " technological means, the semiconductor subassembly with static electricity shield layer can be made Meet electrostatic discharge protective standard, and can pressure resistance with higher.

For the enabled feature and technology contents for being further understood that the utility model, please refer to below in connection with the utility model Detailed description and accompanying drawings, however provided attached drawing is merely provided for reference and description, is not used to add the utility model With limitation.

Detailed description of the invention

Fig. 1 is painted the flow chart of the utility model wherein semiconductor subassembly of an embodiment.

Fig. 2A is partial cutaway schematic of the semiconductor subassembly of the utility model embodiment in manufacturing process.

Fig. 2 B is partial cutaway schematic of the semiconductor subassembly of the utility model embodiment in manufacturing process.

Fig. 2 C is partial cutaway schematic of the semiconductor subassembly of the utility model embodiment in manufacturing process.

Fig. 2 D is partial cutaway schematic of the semiconductor subassembly of the utility model embodiment in manufacturing process.

Fig. 2 E is partial cutaway schematic of the semiconductor subassembly of the utility model embodiment in manufacturing process.

Fig. 2 F is partial cutaway schematic of the semiconductor subassembly of the utility model embodiment in manufacturing process.

Fig. 2 G is partial cutaway schematic of the semiconductor subassembly of the utility model embodiment in manufacturing process.

Fig. 3 is the partial cutaway schematic of the semiconductor subassembly of an embodiment of the present invention.

Fig. 4 is partial cutaway schematic of the semiconductor subassembly of another embodiment of the utility model in manufacturing process.

Fig. 5 is partial cutaway schematic of the semiconductor subassembly of another embodiment of the utility model in manufacturing process.

Fig. 6 is the partial cutaway schematic of the semiconductor subassembly of an embodiment of the present invention.

Specific embodiment

Please refer to Fig. 1.Fig. 1 is the flow chart of the manufacturing method of the semiconductor subassembly of an embodiment of the present invention.Specifically For, the utility model provides the manufacturing method with the semiconductor subassembly of static electricity shield layer, and at least has the following steps.

In the step s 100, formed an epitaxial layer on a substrate, wherein epitaxial layer be divided at least one set of part area with An and electrostatic protection area.In step s 110, respectively in component area and electrostatic protection area formed one first matrix area and One second matrix area.In the step s 120, the laminated construction for being located at electrostatic protection area, lamination are formed on the surface of epitaxial layer Structure includes an insulating layer and the semi-conductor layer on insulating layer, wherein semiconductor layer has one first heavily doped region. In step s 130, at least one second heavily doped region is formed in semiconductor layer, the second heavily doped region and the first heavily doped region are total With one static electricity shield layer of formation.Static electricity shield layer is located above the second matrix area, and static electricity shield layer is completely overlapped in described the Within the scope of two matrix areas.

It will be detailed below the specific steps in the manufacturing method of semiconductor subassembly.In the present embodiment, with channel-type For semiconductor power component, the manufacturing method of the utility model embodiment is described in detail.

A referring to figure 2. shows part section of the semiconductor subassembly of an embodiment of the present invention in manufacturing process Schematic diagram.An epitaxial layer (epitaxial layer) 11 has been formed on substrate 10.Substrate 10 is, for example, silicon substrate (silicon Substrate), the first type conductive impurities with high-dopant concentration, using the drain electrode as semiconductor power component (drain)。

The first conductive type impurity above-mentioned can be N-type or P-type conductivity impurity.Assuming that substrate 10 is silicon substrate, N-type is led Electrical impurity is pentad ion, such as phosphonium ion or arsenic ion, and P-type conductivity impurity is triad ion, such as Boron ion, aluminium ion or gallium ion.

If channel-type power semiconductor subassembly is N-type power MOSFET pipe, 10 doped N-type of substrate Conductive impurities.On the other hand, if channel-type power semiconductor subassembly is P-type channel formula power metal-oxide-semiconductor field effect Ying Guan, then 10 doped p-type conductive impurities of substrate.

Epitaxial layer 11 " is formed in 10 top of substrate, and the first type conductive impurities with low concentration.With NMOS transistor For, substrate 10 is the n-type doping (N of high concentration⁺), and epitaxial layer 11 " is then the n-type doping (N of low concentration^-).Conversely, with For PMOS transistor, substrate 10 is that the p-type of high concentration adulterates (P⁺Doping), and epitaxial layer 11 " is then mixed for the p-type of low concentration Miscellaneous (P^-doping)。

In the present embodiment, epitaxial layer 11 " have a surface 11s, and epitaxial layer 11 " be divided into a component area R1 and One electrostatic protection area R2.It should be noted that although Fig. 2A is painted electrostatic protection area R2 and is surrounded by component area R1, the utility model It is not intended to limit the allocation position of electrostatic protection area R2 Yu component area R1.In another embodiment, component area R1 can be anti-positioned at electrostatic Protect the wherein side of area R2.In another embodiment, component area R1 can be surrounded by electrostatic protection area R2.That is, electrostatic is anti- The allocation position and shape of shield area R2 and component area R1 can be changed according to actual needs, and the utility model is not intended to limit.

As shown in Figure 2 A, an at least gate structure 12 (Fig. 2A be painted multiple for) has been formed in component area R1, And gate structure 12 includes a lock insulating layer 120 and a grid 121.In addition, gate structure 12 can be plane formula grid knot Structure either channel-type gate structure.

In the present embodiment, gate structure 12 is channel-type gate structure.In the step of forming gate structure 12, first exist Multiple channel 11h in component area R1 are formed in epitaxial layer 11 ", sequentially form lock insulating layer 120 in channel 11h later With with grid 121.

As shown in Figure 2 A, a body dopant step 20 is executed to epitaxial layer 11 ", it is initial to form one first in component area R1 Body dopant area 111 ' and electrostatic protection area R2 formed one second initial substrate doped region 112 '.

B referring to figure 2., sequentially form an initial insulating layer 13 ' and one undoped with semiconductor layer 14P in epitaxial layer 11 " Surface 11s.Initial insulating layer 13 ' can cover the whole surface 11s of epitaxial layer 11 ".The material of initial insulating layer 13 ' can select Selecting oxide, perhaps nitride is such as: silica or silicon nitride.

In addition, the thickness of initial insulating layer 13 ', corresponds to the big of the grid source bias (Vgs) of semiconductor power component It is small to adjust.When the gate-source voltage (Vgs) of semiconductor power component is bigger, the thickness of initial insulating layer 13 ' is thicker.

It is formed on initial insulating layer 13 ' undoped with semiconductor layer 14P, to be isolated with epitaxial layer 11 ".It is undoped partly to lead Body layer 14P can be a undoped polysilicon layer.Later, a heavy doping step 30 is executed to undoped with semiconductor layer 14P.

C referring to figure 2. executes a matrix heat and becomes into step, to form the first matrix area 111 and the in epitaxial layer 11 ' Two matrix areas 112.On the other hand, become in step in matrix heat, it also can be synchronously undoped with forming the in semiconductor layer 14P One heavily doped region 140 ', and form an initial semiconductor layer 14 ".

It in the present embodiment, is all using with same conductivity in heavy doping step 30 and body dopant step 20 Impurity.That is, the first heavily doped region 140 ', the first matrix area 111 and the second matrix area 112 all can be having the same Conductivity type, but only as citing, it is not intended to limit the utility model.It in other embodiments, can also be to the first heavily doped region 140 ', first matrix area 111 and the second matrix area 112 do different conductivity types addition additional process steps and reach doping result.

It should be noted that in the present embodiment, the step of forming initial semiconductor layer 14 ", be execute matrix heat become into It is completed before step.However, in other embodiments, matrix heat can also be first carried out and become into step, to form the first matrix area 111 and second matrix area 112.And then execute another secondary heat and become into step, it is first with the first heavily doped region 140' to be formed Beginning semiconductor layer 14 ".

In other embodiments, the first matrix area 111 and the second matrix area 112 can also be initially formed in epitaxial layer 11 " Interior and then formation is located at the gate structure 12 in component area R1.

As shown in Figure 2 C, the first matrix area 111 is located in the component area R1 of epitaxial layer 11 ', and surrounds gate structure 12.It is of heap of stone Other regions in crystal layer 11 ' form the drift region 110 ' of channel-type semiconductor subassembly.Second matrix area 112 is located at electrostatic protection In area R2, and it is connected to initial insulating layer 13 '.

D referring to figure 2., removal is positioned at the initial insulating layer 13 ' of a part of component area R1 and a part of initial semiconductor Layer 14 ", to form the laminated construction P1 ' for being located at electrostatic protection area R2.

Specifically, photoresist layer PR can be formed on initial semiconductor layer 14 ", to define the position of laminated construction P1 ', An etching step is executed again, and removal is located at a part of initial semiconductor floor 14 " and a part of initial insulating layer of component area R1 13'.Another part can be retained by the initial semiconductor layer 14 " that photoresist layer PR is covered and initial insulating layer 13 ', and be formed The laminated construction P1 ' of R2 in electrostatic protection area.

Accordingly, laminated construction P1 ' includes the semiconductor layer 14 ' and an insulating layer 13 in electrostatic protection area R2, and There is the first heavily doped region 140 ' in semiconductor layer 14 '.Laminated construction P1 ' is formed through the above steps, it can to avoid lamination The positional shift of structure P1 ', and semiconductor layer 14 ' is caused directly to contact with epitaxial layer 11 '.In the present embodiment, semiconductor layer 14 ' transverse width can be roughly the same with the transverse width of insulating layer 13.Specifically, width and the insulation of semiconductor layer 14 ' Difference between the width of layer 13 is less than 0.5um.

E referring to figure 2. re-forms at least one second heavily doped region 141 in semiconductor layer 14 ', makes at least one second weight A static electricity shield layer 14 is collectively formed in doped region 141 and the first heavily doped region 140.Static electricity shield layer 14 is set to insulating layer 13 On, and electrostatic protection lamination P1 is collectively formed in static electricity shield layer 14 and insulating layer 13.

Specifically, shielding pattern layer (not shown) can be pre-formed on semiconductor layer 14 ', it is heavily doped to define second The position in miscellaneous area 141.Later, become by sequentially carrying out a doping step and a heat into step, can in semiconductor layer 14 ' shape At the second heavily doped region 141.

Second heavily doped region 141 is respectively provided with opposite conductivity type with the first heavily doped region 140.Therefore, heavily doped second Interface between miscellaneous area 141 and the first heavily doped region 140 will form a PN junction.

In the embodiment of Fig. 2 E, two the second heavily doped regions 141 being separated from each other are formed in semiconductor layer 14 ', and First heavily doped region 140 is located between two the second heavily doped regions 141, and forms triode (bipolar diode), such as: PNP Triode either NPN triode.

In addition, can synchronously form at least one first in component area R1 in the step of forming the second heavily doped region 141 Source area 113a (Fig. 2 E is painted multiple).Accordingly, the first source area 113a and the second heavily doped region 141 can conductions having the same Type.

It should be noted that adjust the position of the second heavily doped region 141, and can be formed by changing shielding pattern layer Different static electricity shield layers 14.Please also refer to Fig. 4, show that the semiconductor subassembly of another embodiment of the utility model is flowed in manufacture Diagrammatic cross-section in journey, and can hookup 2D the step of.

In the fig. 4 embodiment, one second heavily doped region 141 is only formed in semiconductor layer 14 ', and forms PN junction two Pole pipe (diode).Therefore, as long as can achieve the effect that electrostatic discharge (ESD) protection, static electricity shield layer 14 can be triode, bis- pole PN Pipe either other assemblies.

Referring again to Fig. 5, section of the semiconductor subassembly of another embodiment of the utility model in manufacturing process is shown Schematic diagram, and can hookup 2D the step of.It, can be synchronously in component area R1 in the step of forming the second heavily doped region 141 Form shape at least one second source area 113b at least one first source area 113a (Fig. 5 is painted multiple) and electrostatic protection area R2 (Fig. 5 is painted two).

In the 5 embodiment of figure 5, the first source area 113a is located at 111 top of the first matrix area, and is connected to an at least grid Pole structure 12.In addition, the second matrix area 112 has an extension 112a, and extension 112a can be connected near quiet The gate structure 12 of electric guard plot R2.Second source area 113b is formed in above the 112a of extension part, and connect near The gate structure 12 of electrostatic protection area R2.

It is worth noting that, through the above steps, transistor arrangement can be formed in component R1 together, and in electrostatic protection Area R2 forms electrostatic protection lamination P1.Accordingly, in the fabrication steps of the utility model embodiment, form electrostatic protection lamination P1's Step can be integrated with the step of forming transistor arrangement, and then reduce manufacturing cost.

F, Fig. 2 G and Fig. 3 referring to figure 2. form a redistribution line construction, so that transistor arrangement and electrostatic are anti- Shield lamination P1 can be electrically connected at an external control circuit.Specifically, as shown in Figure 2 F, formed an interlayer dielectric layer 15 ' in On the surface 11s of static electricity shield layer 14 and epitaxial layer 11.Then, as shown in Figure 2 G, multiple connect is formed in interlayer dielectric layer 15 Window 15h is touched, and forms multiple conductive structures 16 in multiple contact hole 15h.

Conductive structure 16 includes multiple first conductive columns 161 and multiple second conductive columns 162.Each first conductive column 161, by corresponding contact hole 15h, are electrically connected at corresponding first source area 113a.Each second conductive column 162 passes through Corresponding contact hole 15h is electrically connected at the first heavily doped region 140 or the second heavily doped region 141 of static electricity shield layer 14.Separately Outside, the first heavily doped region 140, which can connect, can not also connect the second conductive column 162, and visual application demand determines.

Referring to figure 3., the partial cutaway schematic of the semiconductor subassembly of the utility model embodiment is shown.In the present embodiment In, a connection pad group 17 is also further formed on interlayer dielectric layer 15.Connection pad group 17 includes multiple first connection pads 171 and multiple Second connection pad 172.First connection pad 171 is electrically connected at the first source area 113a and the by corresponding first conductive column 161 Two source area 113b.Second connection pad 172 by corresponding second conductive column 162 be electrically connected at the first heavily doped region 140 or Second heavily doped region 141.

Later, a protective layer 18 is formed in connection pad group 17.Protective layer 18 has multiple openings, and each opening exposes pair The first connection pad 171 (or second connection pad 172) answered, so that multiple first connection pads 171 can be electrically connected with multiple second connection pads 172 To external control circuit.

Accordingly, as shown in figure 3, the utility model embodiment provides a kind of semiconductor subassembly for integrating static electricity shield layer 14 M1.Semiconductor subassembly M1 is, for example, trench type metal-oxide semiconductor field-effect tube, sideways diffusion metal-oxide semiconductor (MOS) Field-effect tube or plane formula metal oxide semiconductor field effect tube etc..

Semiconductor subassembly M1 can be divided into component area R1 and electrostatic protection area R2.The area of electrostatic protection area R2 is practical to answer It is adjusted with demand.If semiconductor subassembly M1 needs to meet higher electrostatic discharge protective specification, that is, has biggish quiet The area of discharge of electricity ability to bear, electrostatic protection area R2 also can be bigger.

Semiconductor subassembly M1 includes substrate 10, epitaxial layer 11, gate structure 12 and electrostatic protection lamination P1.Epitaxial layer 11 It is set on substrate 10, and there is drift region 110, the first matrix area 111, the second matrix area 112 and the first source area 113a. Drift region 110 is located at the side in epitaxial layer 11 close to substrate 10, and extends to electrostatic protection area R2 by component area R1.

First matrix area 111 is located in component area R1, and is located remotely from the side of substrate 10.That is, the first matrix Area 111 is located at 110 top of drift region.In addition, the first source area 113a is located at 111 top of the first matrix area, and it is connected to epitaxy The surface 11s of layer 11.

Second matrix area 112 is located in electrostatic protection area R2, and is located at the side in epitaxial layer 11 far from substrate 10, also It is to be located at 110 top of drift region.

When semiconductor subassembly M1 is trench type metal-oxide semiconductor field-effect tube, epitaxial layer 11 further includes being located at group At least one channel 11h in part area R1, and gate structure 12 is arranged in channel 11h.

As shown in figure 3, gate structure 12 includes a lock insulating layer 120 and a grid 121.Lock insulating layer 120 is covered in The inner wall of channel 11h, so that grid 121 is electrically insulated with epitaxial layer 11.Gate structure 12 in component area R1 can connect It is connected to the first matrix area 111 and the first source area 113a.

In the present embodiment, the second matrix area 112 can be connected to the gate structure 12 near electrostatic protection area R2.

Electrostatic protection lamination P1 is set on epitaxial layer 11, and is located at electrostatic protection area R2, to protect semiconductor subassembly M1 is from damage of electrostatic discharge.Electrostatic protection lamination P1 includes an insulating layer 13 and a static electricity shield layer 14, and insulating layer 13 It is between static electricity shield layer 14 and epitaxial layer 11, so that static electricity shield layer 14 and the second matrix area 112 completely cut off.Accordingly, absolutely Edge layer 13 can be directly connected in the second matrix area 112.

In addition, the wherein end point due to static electricity shield layer 14 can be with 121 common-battery position of grid, the thickness of insulating layer 13 It can be determined according to the source grid bias (Vgs) for being applied to semiconductor subassembly M1.When source grid bias (Vgs) is bigger, insulation The thickness of layer 13 needs thicker.

Static electricity shield layer 14 includes at least one first heavily doped region 140 and at least one second heavily doped region 141.It is real one It applies in example, the first heavily doped region 140 and the first matrix area 111 and the conductivity type having the same of the second matrix area 112, such as all It is P-doped zone.Second heavily doped region 141 and the first source area 113a conductivity type having the same, such as be all n-type doping Area, but the utility model is not intended to limit.Different conductivity types addition additional process steps can also be done and reach doping result.

In addition, the transverse width of static electricity shield layer 14 is roughly the same with the transverse width of insulating layer 13.Furthermore, quiet Difference between the width of electric protective layer 14 and the width of insulating layer 13 is less than 0.5um.In one embodiment, static electricity shield layer 14 Above the second matrix area 112, and static electricity shield layer 14 is completely overlapped in 112 range of the second matrix area.

It is worth noting that the static electricity shield layer 14 of the utility model embodiment is located above second matrix area, And static electricity shield layer is completely overlapped within the scope of second matrix area, compared to existing semiconductor power component, this is practical The bottom of the electrostatic protection lamination P1 of new embodiment will not be directly connected to drift region 110, and can only connect the second matrix area 112.Therefore, in electrostatic protection area R2, be formed by between the second matrix area 112 and drift region 110 interface approximately along The direction of parallel surfaces 11s extends.

Since in semiconductor subassembly M1 provided by the utility model, electrostatic protection lamination P1 only connects the second matrix area 112, therefore when semiconductor subassembly M1 running, it is more equal in the electric field strength of the second matrix area 112 and the interface of drift region 110 It is even, to make the semiconductor subassembly M1 pressure resistance with higher of the utility model embodiment.Accordingly, compared to existing semiconductor (PCC) power, the semiconductor subassembly M1 of the utility model embodiment is in addition to also having centainly with electro-static discharge protective ability Voltage endurance capability.

Fig. 6 is please referred to, shows the partial cutaway schematic of the semiconductor subassembly of another embodiment of the utility model.This implementation Example component label having the same identical with the embodiment of Fig. 3, and identical part repeats no more.

Difference between the present embodiment and the embodiment of Fig. 3 is, in the semiconductor subassembly M2 of the present embodiment, gate structure 12 be plane formula gate structure.That is, gate structure 12 is arranged on the surface 11s of epitaxial layer 11.In addition, in component In area R1, epitaxial layer 11 includes multiple the first matrix areas 111 being separated from each other, and each first source area 113a is right respectively The first matrix area 111 answered surrounds.

In addition, in the present embodiment, the second matrix area 112 can be connected to the gate structure near electrostatic protection area R2 12.Specifically, the second matrix area 112 can be connected to the lock insulating layer 120 of gate structure 12.

The manufacturing method of the utility model embodiment can also be used to form semiconductor subassembly M2.Specifically, can formed First matrix area 111 and the second matrix area 112 and then in component area R1, form gate structure 12 in the table of epitaxial layer 11 On the 11s of face.

Accordingly, in the manufacturing method of the semiconductor subassembly of the utility model, as long as can at electrostatic protection lamination P1 Second matrix area 112 completely overlapped with it is formed, the sequence of step all can be according to the structure or system of semiconductor subassembly itself Journey demand adjusts.

In summary, the beneficial effects of the utility model are semiconductor subassembly provided by technical solutions of the utility model And its manufacturing method, by " before forming electrostatic protection lamination P1, first being formed in epitaxial layer 11 and being located at electrostatic protection area R2 The second matrix area 112 " and " static electricity shield layer is completely overlapped within the scope of second matrix area " technological means, can be with The semiconductor subassembly with electrostatic protection lamination P1 is set to meet electrostatic discharge protective standard, and can pressure resistance with higher.

In addition, it is anti-to form electrostatic in electrostatic protection area R2 in the method for producing semiconductor module of the utility model embodiment The step of protecting lamination P1 can be integrated with the step of component R1 forms transistor arrangement, and then reduce manufacturing cost.

Content disclosed above is only the preferred possible embodiments of the utility model, not thereby limits to the utility model Claim, so it is all done with the utility model specification and accompanying drawing content equivalence techniques variation, wrap In claim contained in the utility model.

Symbol description

Semiconductor subassembly M1, M2

Substrate 10

Epitaxial layer 11,11 ', 11 "

Component area R1

Electrostatic protection area R2

Channel 11h

Surface 11s

Drift region 110,110 '

First matrix area 111

Second matrix area 112

Extension 112a

First source area 113a

Second source area 113b

Gate structure 12

Lock insulating layer 120

Grid 121

Initial insulating layer 13 '

Undoped with semiconductor layer 14P

Laminated construction P1 '

Initial semiconductor layer 14 "

Semiconductor layer 14 '

Electrostatic protection lamination P1

Insulating layer 13

Static electricity shield layer 14

First heavily doped region 140,140 '

Second heavily doped region 141

Interlayer dielectric layer 15,15 '

Contact hole 15h

Conductive structure 16

First conductive column 161

Second conductive column 162

Connection pad group 17

First connection pad 171

Second connection pad 172

Protective layer 18

Body dopant step 20

Heavy doping step 30

First initial substrate doped region 111 '

Second initial substrate doped region 112 '

Photoresist layer PR

Process step S100~S130

Claims (6)

1. a kind of semiconductor subassembly is divided into a component area and an electrostatic protection area, which is characterized in that the semiconductor Component includes:

One epitaxial layer comprising positioned at one first matrix area in the component area and positioned at the one second of the electrostatic protection area Matrix area；

One gate structure is set in the component area, and is attached at least to first matrix area；And

One static electricity shield layer is set on a surface of the epitaxial layer and is isolated with the epitaxial layer, wherein the electrostatic Protective layer is located above second matrix area, and the static electricity shield layer is completely overlapped within the scope of second matrix area.

2. the semiconductor subassembly as described in claims 1, which is characterized in that the static electricity shield layer include one first heavily doped region with One second heavily doped region, and the interface of first heavily doped region and second heavily doped region is a PN junction.

3. the semiconductor subassembly as described in claims 1, which is characterized in that the semiconductor subassembly further includes an insulating layer, institute Insulating layer is stated between the static electricity shield layer and the epitaxial layer, the insulating layer is connected to second matrix area, and Difference between the width of the static electricity shield layer and the width of the insulating layer is less than 0.5um.

4. the semiconductor subassembly as described in claims 1, which is characterized in that the gate structure is channel-type gate structure or puts down Face formula gate structure.

5. the semiconductor subassembly as described in claims 1, which is characterized in that the epitaxial layer further includes being located in the component area One first source area, first source area is connected to the wherein side of the gate structure, and first matrix area surrounds First source area.

6. the semiconductor subassembly as described in claims 5, which is characterized in that second matrix area has an extension, and even The other side of the gate structure is connect, and one second source area is located above the extension.