CN113035948B - Power device, power electronic equipment and manufacturing method of power device - Google Patents

Power device, power electronic equipment and manufacturing method of power device Download PDF

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Publication number
CN113035948B
CN113035948B CN201911343176.6A CN201911343176A CN113035948B CN 113035948 B CN113035948 B CN 113035948B CN 201911343176 A CN201911343176 A CN 201911343176A CN 113035948 B CN113035948 B CN 113035948B
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layer
gate structure
type
power device
trench
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CN113035948A (en
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郭依腾
史波
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Gree Electric Appliances Inc of Zhuhai
Zhuhai Zero Boundary Integrated Circuit Co Ltd
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Gree Electric Appliances Inc of Zhuhai
Zhuhai Zero Boundary Integrated Circuit Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The disclosure relates to a power device, power electronic equipment and a manufacturing method of the power device. The power device includes an N-type semiconductor substrate; the P-type well layer is positioned on the front side of the N-type semiconductor substrate; the N-type emitting layer is positioned on the front side of the P-type well layer; the groove penetrates through the N-type emitting layer and the P-type well layer and extends to the inside of the N-type semiconductor substrate; the first dielectric layer at least covers the bottom wall and the side wall of the groove; and the gate structure is filled in the groove and comprises a first part and a second part, wherein the first part is closer to the bottom wall of the groove, and the resistivity of the first part is greater than that of the second part.

Description

Power device, power electronic equipment and manufacturing method of power device
Technical Field
The present disclosure relates to the field of power electronics technologies, and in particular, to a power device, a power electronic apparatus, and a method for manufacturing the power device.
Background
In the Field of power electronics, Metal-Oxide-Semiconductor Field Effect transistors (MOSFETs) and Insulated Gate Bipolar Transistors (IGBTs) are widely used power devices. Among them, the MOSFET is widely used in the field of 4C (i.e., Communication, Computer, Consumer electronics, Car) because of its advantages of high switching speed, good frequency performance, high input impedance, small driving power, good temperature characteristics, no secondary breakdown, and the like. The IGBT is a composite fully-controlled voltage-driven semiconductor power device composed of Bipolar Junction Transistors (BJTs) and MOSFETs, and is very suitable for application in the fields of converter systems with dc voltages of 600V or more, such as ac motors, frequency converters, switching power supplies, lighting circuits, traction drives, and the like.
How to improve the electrical characteristics of these power devices has been a key issue for those skilled in the art to develop.
Disclosure of Invention
The embodiment of the disclosure provides a power device, power electronic equipment and a manufacturing method of the power device, so as to solve the technical problems that the switching speed of the power device is low, the switching loss is large, and the energy efficiency of the device is not ideal in the related technology.
According to an aspect of an embodiment of the present disclosure, there is provided a power device including:
an N-type semiconductor substrate;
the P-type well layer is positioned on the front side of the N-type semiconductor substrate;
an N-type emitter layer positioned at the front side of the P-type well layer;
a trench passing through the N-type emitting layer and the P-type well layer and extending into the N-type semiconductor substrate;
the first dielectric layer at least covers the bottom wall and the side wall of the groove;
and the gate structure is filled in the groove and comprises a first part and a second part, the first part is closer to the bottom wall of the groove, and the resistivity of the first part is greater than that of the second part.
In some embodiments, the resistivity of the first portion of the gate structure is greater than 1000 ohms and the resistivity of the second portion of the gate structure is 8 to 20 ohms.
In some embodiments, the material of the first portion of the gate structure comprises undoped polysilicon and the material of the second portion of the gate structure comprises doped polysilicon.
In some embodiments, the material of the first portion of the gate structure comprises an undoped oxide semiconductor and the material of the second portion of the gate structure comprises a doped oxide semiconductor.
In some embodiments, the junction depth of the P-type well layer is not greater than the fill thickness of the second portion of the gate structure.
In some embodiments, the first dielectric layer also overlies the N-type emitter layer.
In some embodiments, the power device further comprises:
the second dielectric layer is positioned on the front side of the gate structure and is provided with a contact hole leading to the P-type well layer;
the emitter metal is positioned on the front side of the second dielectric layer and is electrically connected with the P-type well layer through the contact hole;
and the protective layer is positioned on the front side of the emitter metal, and part of the emitter metal is exposed by the protective layer.
In some embodiments, the power device further includes:
the buffer layer, the P-type collector layer and the collector metal are sequentially arranged on the back side of the N-type semiconductor substrate and along the direction far away from the N-type semiconductor substrate.
In some embodiments, the power device further includes:
a collector metal connected to a backside of the N-type semiconductor substrate.
According to another aspect of the embodiments of the present disclosure, there is provided a power electronic device including the power device according to any one of the preceding claims.
According to another aspect of the embodiments of the present disclosure, there is provided a method for manufacturing a power device, including:
forming a groove on an N-type semiconductor substrate;
forming a first dielectric layer at least covering the bottom wall and the side wall of the groove;
forming a first part of a gate structure in the trench, wherein the filling thickness of the first part is less than the depth of the trench;
and forming a second part of the gate structure in the trench, wherein the second part is positioned at the front side of the first part, and the resistivity of the first part is greater than that of the second part.
In some embodiments, the forming a first portion of a gate structure within a trench includes:
forming an undoped polysilicon layer in the trench, wherein the filling thickness of the undoped polysilicon layer is greater than the preset filling thickness of the first part of the gate structure;
etching the undoped polysilicon layer to form a first part of the gate structure;
the forming a second portion of the gate structure in the trench includes:
forming a doped polysilicon layer at least filling the trench;
and etching the doped polysilicon layer to form a second part of the gate structure.
In some embodiments, the manufacturing method further includes:
forming a P-type well layer on the front side of the N-type semiconductor substrate, wherein the junction depth of the P-type well layer is not more than the filling thickness of the second part of the gate structure;
and forming an N-type emitting layer on the front side of the P-type well layer, wherein the N-type emitting layer is arranged around the groove.
In some embodiments, the forming a first dielectric layer at least covering the bottom wall and the side wall of the trench includes:
a first dielectric layer is formed overlying the bottom and sidewalls of the trench and the front side surface of the N-type semiconductor substrate.
By adopting the technical scheme of the embodiment of the disclosure, the capacitance formed between the grid and the collector can be effectively reduced, so that the switching speed of the power device is increased, and the switching loss is reduced.
Other features of the present disclosure and advantages thereof will become apparent from the following detailed description of embodiments of the present disclosure with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure.
The present disclosure may be more clearly understood from the following detailed description, taken with reference to the accompanying drawings, in which:
fig. 1 is a schematic cross-sectional view of an IGBT device in the related art;
fig. 2 is a schematic cross-sectional view of a power device (IGBT) according to some embodiments of the present disclosure;
FIG. 3 is a schematic cross-sectional view of a power device (MOSFET) according to further embodiments of the present disclosure;
FIG. 4 is an equivalent circuit schematic diagram of an IGBT device;
FIG. 5 is a flow chart of a method of fabricating a power device according to some embodiments of the present disclosure;
fig. 6a is a detailed flowchart of some embodiments of the disclosure at step S1;
fig. 6b is a schematic diagram of some embodiments of the present disclosure after completion of step S2;
fig. 6c is a detailed flowchart of some embodiments of the disclosure at step S3;
fig. 6d is a detailed flowchart of some embodiments of the disclosure at step S4;
FIG. 7 is a flow chart of a method of fabricating a power device according to further embodiments of the present disclosure;
FIG. 8a is a schematic flow chart of some embodiments of the present disclosure at steps S5-S9;
FIG. 8b is a schematic flow chart of steps S10-S12 according to some embodiments of the present disclosure.
It should be understood that the dimensions of the various parts shown in the drawings are not drawn to scale. Further, the same or similar reference numerals denote the same or similar components.
Detailed Description
Various embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the embodiments is merely illustrative and is in no way intended to limit the disclosure, its application, or uses. The present disclosure may be embodied in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. It should be noted that: the relative arrangement of parts and steps set forth in these embodiments is to be construed as illustrative only and not as a limitation unless specifically stated otherwise.
The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" and similar words mean that the elements preceding the word encompass the elements listed after the word, and does not exclude the possibility that other elements are also encompassed. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
In the present disclosure, when a specific element is described as being located between a first element and a second element, there may or may not be intervening elements between the specific element and the first element or the second element.
All terms (including technical or scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs unless specifically defined otherwise. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In the process of implementing the present application, the inventors of the present application found that, in the related art, a power device adopting a trench gate design, as shown in fig. 1, because the area of the gate 016 is large, the gate capacitance is also large in general, that is, a longer charging time is required for applying a voltage to the gate 016, and due to these reasons, the switching speed of the device is slow, the switching loss is large, and the energy efficiency of the device is not ideal.
In order to solve the technical problem, the embodiment of the disclosure provides a power device, power electronic equipment and a manufacturing method of the power device.
As shown in fig. 2, some embodiments of the present disclosure provide a power device, including:
an N-type semiconductor substrate 11;
a P-type well layer 12 on the front side of the N-type semiconductor substrate 11;
an N-type emitter layer 13 on the front side of the P-type well layer 12;
a trench 14 passing through the N-type emitter layer 13 and the P-type well layer 12 and extending into the inside of the N-type semiconductor substrate 11;
a first dielectric layer 15 at least covering the bottom wall and the side wall of the trench 14;
the gate structure 16, filled in the trench 14, includes a first portion 161 and a second portion 162, the first portion 161 is closer to the bottom wall of the trench 14, and the resistivity of the first portion 161 is greater than that of the second portion 162.
In the embodiment of the present disclosure, the side where the emitter of the power device is located is defined as a front side, and the side where the collector of the power device is located is defined as a back side.
As shown in fig. 2, the power device further includes a second dielectric layer 17, an emitter metal 18 and a protective layer 19 on the front side of the N-type semiconductor substrate 11, wherein the second dielectric layer 17 is located on the front side of the gate structure 16 and has a contact hole 25 leading to the P-type well layer 12, the emitter metal 18 is located on the front side of the second dielectric layer 17 and is electrically connected to the P-type well layer 12 through the contact hole 25, and the protective layer 19 is located on the front side of the emitter metal 18 and exposes a portion of the emitter metal 18. In the embodiment of the present disclosure, the first dielectric layer 15 is used to insulate and space the gate structure 16 in the trench 14 from the N-type semiconductor substrate 11, the P-type well layer 12, and the N-type emitter layer 13. The first dielectric layer 15 may be formed only on the bottom wall and the sidewalls of the trench 14. In some embodiments of the present disclosure, as shown in fig. 2, the first dielectric layer 15 may also cover the N-type emitting layer 13 and the like at the same time for the convenience of manufacturing process.
In the embodiments of the present disclosure, the specific type of the power device is not limited. The specific type of the power device is different, and the specific structure of the power device is also different. The power device shown in fig. 2 is an IGBT device, and the structure further includes a buffer layer 20, a P-type collector layer 21, and a collector metal 22, which are located on the back side of the N-type semiconductor substrate 11 and are sequentially disposed in a direction away from the N-type semiconductor substrate 11. In other embodiments, the power device may also be a MOSFET device, as shown in fig. 3, which further comprises a collector metal 22 connected to the back side of the N-type semiconductor substrate 11. Taking an IGBT device as an example, the N-type semiconductor substrate 11 is usually lightly doped, and the N-type emitter layer 13, the P-type well layer 12, the N-type buffer layer 20, and the P-type collector layer 21 are usually heavily doped, wherein when the power device operates, the N-type semiconductor substrate 11 serves as a drift region of the device, and the buffer layer 20 is used to prevent a depletion region of the device from diffusing to the P-type collector layer 21.
Taking an IGBT device as an example, an equivalent circuit diagram of the IGBT device is shown in fig. 4. When the IGBT device works, in the gate opening process, a gate driving source charges a gate capacitor Cies (Cies is Cge + Cgc), the size of the gate resistor Rg is inversely proportional to the peak current of the gate capacitor Cies, the size of the gate capacitor Cies is proportional to the size of the gate charge Qg, and the working frequency f of the device is inversely proportional to the size of the gate resistor Rg and the size of the gate capacitor Cies.
In the related art IGBT device shown in fig. 1, the gate 016 and the emitter 018 form a Capacitance Cge, the gate 016 and the collector 022 form a Capacitance Cgc, and the Capacitance Cgc is an important component of Miller Capacitance (Miller Capacitance), which has a large influence on the gate Capacitance Cies and the gate charge Qg, and thus affects the switching speed and the switching loss of the device. The miller capacitance is a capacitance connected across the output terminal and the input terminal of the amplifier (device or circuit for amplification operation). The effect of the miller capacitance on the frequency characteristics of the device or circuit is called the miller effect, and the frequency characteristics of the device or circuit can be greatly reduced due to the small miller capacitance.
As shown in fig. 2, in the disclosed embodiment, the gate structure 16 includes two portions, wherein the first portion 161 is closer to the bottom wall of the trench 14, and the resistivity of the first portion 161 is greater than the resistivity of the second portion 162. By reducing the conductivity of the first part 161, the capacitance Cgc formed between the gate and the collector can be reduced, thereby reducing the gate capacitance Cies, and further achieving the purposes of increasing the operating frequency of the device, increasing the switching speed and reducing the switching loss.
In some embodiments of the present disclosure, the first portion 161 of the gate structure 16 has a resistivity greater than 1000 ohms, a negligible conductivity, and the second portion 162 of the gate structure 16 has a resistivity of 8 to 20 ohms.
In some embodiments of the present disclosure, the material of the first portion 161 of the gate structure 16 comprises undoped polysilicon and the material of the second portion 162 of the gate structure 16 comprises doped polysilicon. Polysilicon is used as a semiconductor material, and the conductivity of polysilicon can be significantly improved by heavily doping the polysilicon (such as doping boron or phosphorus), while undoped polysilicon is almost non-conductive. Therefore, the conductivity of the first portion 161 of the gate structure 16 is negligible, thereby greatly reducing the capacitance formed between the gate and the collector, reducing the gate capacitance, enabling the switching speed of the power device to be increased, and reducing the switching loss.
In other embodiments of the present disclosure, the material of the first portion 161 of the gate structure 16 comprises an undoped oxide semiconductor and the material of the second portion 162 of the gate structure 16 comprises a doped oxide semiconductor. Similarly, an oxide semiconductor, such as zinc oxide, indium gallium zinc oxide, etc., as a semiconductor material, can be heavily doped to significantly improve its conductivity, while an undoped oxide semiconductor is almost non-conductive. The scheme can also achieve the beneficial effects.
It is noted that in some embodiments of the present disclosure, the first portion 161 and the second portion 162 of the gate structure 16 may also include doped polysilicon, but the doping concentration of the first portion 161 is much lower than that of the second portion 162, so that the resistivity of the second portion 162 is much lower than that of the first portion 161, which may also achieve similar advantages as described above.
Referring to fig. 2, in the embodiment of the present disclosure, the junction depth H of the P-type well layer 12 is not greater than the filling thickness H of the second portion 162 of the gate structure 16. I.e., the first portion 161 of the gate structure 16 is completely outside the P-type well layer 12, so that other relevant parameters of the device, such as the turn-on voltage Vth and the breakdown voltage BV, are not affected, thereby ensuring the characteristics of the device in other aspects.
The embodiment of the disclosure also provides a power electronic device comprising the power device in any one of the technical schemes. Because the switching speed of the power device is increased, the switching energy consumption is reduced, and the electrical characteristics are improved, the electrical characteristics of the power electronic equipment are also improved, and the product quality is better. Specific product types of power electronics are not limited, including but not limited to household appliances, transportation equipment, traction drive equipment, electric machine equipment, and the like.
As shown in fig. 5, an embodiment of the present disclosure further provides a manufacturing method of the power device. The manufacturing method includes the following steps S1 to S4.
In step S1, a trench is formed on the N-type semiconductor substrate.
In some embodiments, as shown in fig. 6a, step S1 may include the following sub-steps:
substep S101: a first oxide film 151 and a mask oxide layer 23 are sequentially formed on one surface of the N-type semiconductor substrate 11. The N-type semiconductor substrate 11 may be an N-type monocrystalline silicon wafer, and a thin oxide layer serving as a protective layer is grown on the surface of the N-type monocrystalline silicon wafer by using a high-temperature furnace tube growth process to serve as a first oxide film 151, and then a thick oxide layer is continuously grown to serve as a mask oxide layer 23.
Substep S102: and etching the first oxide film 151 and the mask oxide layer 23 to form a mask pattern, wherein the position of the mask pattern corresponding to the groove is a hollow area.
Substep S103: the N-type semiconductor substrate 11 is etched through the hollowed-out region of the mask pattern, thereby forming the trench 14. The etching of the N-type semiconductor substrate 11 may adopt a plasma etching process, and the depth of the trench 14 may be designed accordingly according to the parameter requirements of the device.
Returning to fig. 5, in step S2, a first dielectric layer is formed overlying at least the bottom wall and sidewalls of the trench.
In some embodiments, the structure after step S2 is completed is shown in fig. 6b, in which step a second oxide film 152 is formed on the bottom wall and the side wall of the trench 14, the second oxide film 152 and the etched first oxide film 151 are used as the first dielectric layer 15, and the mask oxide layer 23 is removed in this step. Similar to the first oxide film 151, the second oxide film 152 may be formed on the bottom wall and the sidewall of the trench 14 using a growth process, thereby protecting the surface of the trench 14.
Returning to fig. 5, in step S3, a first portion of the gate structure is formed within the trench, the first portion having a fill thickness less than the depth of the trench.
In some embodiments, as shown in fig. 6c, this step S3 may include the following sub-steps:
substep S301: an undoped polysilicon layer 16a is formed in the trench 14, and the filling thickness of the undoped polysilicon layer 16a is greater than the predetermined filling thickness of the first portion of the gate structure. For example, the undoped polysilicon layer 16a may be deposited inside and outside the trench simultaneously by chemical vapor deposition. It should be noted here that the filling thickness of the undoped polysilicon layer is only required to be greater than the preset filling thickness of the first portion of the gate structure, and therefore, the undoped polysilicon layer meeting the thickness requirement may be deposited only in the trench.
Substep S302: the undoped polysilicon layer 16a is etched to form a first portion 161 of the gate structure. By precisely controlling the etching time, the etching amount can be accurately controlled, thereby ensuring that the thickness of the first portion 161 meets the requirements.
Returning to fig. 5, in step S4, a second portion of the gate structure is formed within the trench, the second portion being located forward of the first portion, wherein the resistivity of the first portion is greater than the resistivity of the second portion.
In some embodiments, as shown in fig. 6d, this step S4 may include the following sub-steps:
substep S401: a doped polysilicon layer 16b is formed to at least fill the trench. For example, the doped polysilicon layer 16b may be deposited inside and outside the trench simultaneously by chemical vapor deposition.
Substep S402: the doped polysilicon layer 16b is etched to form a second portion 162 of the gate structure. For example, epd (end detect) monitoring may be used, and etching is stopped until the first dielectric layer 15 is exposed.
After step S4 is completed, the gate structure is completed.
As shown in fig. 7, after step S4, the fabrication of other structures on the front side of the device may be completed, and as shown in fig. 8a, the steps S5-S9 may be specifically included.
Step S5: a P-type well layer 12 is formed on the front side of an N-type semiconductor substrate 11, and the junction depth of the P-type well layer 12 is not more than the filling thickness of a second part 162 of a gate structure. The P-type well layer 12 is formed by doping a P-type impurity on the front side of the N-type semiconductor substrate 11 by, for example, ion implantation and thermal diffusion processes.
Step S6: an N-type emission layer 13 is formed on the front side of the P-type well layer 12, and the N-type emission layer 13 is disposed around the trench. The N-type emitter layer 13 is formed by doping a predetermined region on the front side of the P-type well layer 12 with an N-type impurity by, for example, ion implantation and thermal diffusion processes.
Step S7: a second dielectric layer 17 is formed on the front side of the gate structure, and the second dielectric layer 17 has a contact hole 25 leading to the P-type well layer 12. The second dielectric layer 17 may be an oxide film layer, deposited by chemical vapor deposition, and then patterned to form the contact hole 25 by an etching process.
Step S8: an emitter metal 18 is formed on the front side of the second dielectric layer 17, and the emitter metal 18 is electrically connected to the P-type well layer 12 through the contact hole 25. A metal layer may be sputtered by physical vapor deposition and then patterned by an etching process to form emitter metal 18.
Step S9: a protective layer 19 is formed on the front side of the emitter metal 18, the protective layer 19 exposing a portion of the emitter metal 18. The protective layer 19 may protect the device from contamination by ambient moisture and impurities, and the portion of the emitter metal 18 exposed by the protective layer 19 is used for electrical connection to external structures.
After step S9, fabrication of other structures on the back side of the device may continue to be completed. The specific type of power device is different, and the specific structure of the power device on the back side of the N-type semiconductor substrate 11 is also different. Taking an IGBT device as an example, as shown in fig. 8b, the fabrication process of the device backside may include the following steps S10-S12.
Step S10: a buffer layer 20 is formed on the back side of the N-type semiconductor substrate 11.
Step S11: a P-type collector layer 21 is formed on the back side of the buffer layer 20.
Step S12: a collector metal 22 is formed on the backside of the P-type collector layer 21.
The buffer layer 20 and the P-type collector layer 21 may be formed by ion implantation and diffusion on the back side of the N-type semiconductor substrate 11, and the collector metal 22 may be formed by sputtering using a physical vapor deposition process.
The power device manufactured by the method of the embodiment of the disclosure can effectively reduce the capacitance formed between the grid and the collector, thereby improving the switching speed of the power device and reducing the switching loss.
Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the foregoing examples are for purposes of illustration only and are not intended to limit the scope of the present disclosure. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims (13)

1. A power device, comprising:
an N-type semiconductor substrate;
the P-type well layer is positioned on the front side of the N-type semiconductor substrate;
an N-type emitter layer positioned at the front side of the P-type well layer;
a trench passing through the N-type emitter layer and the P-type well layer and extending into the N-type semiconductor substrate;
the first dielectric layer at least covers the bottom wall and the side wall of the groove;
and the gate structure is filled in the groove and comprises a first part and a second part, the first part is closer to the bottom wall of the groove, the resistivity of the first part is greater than that of the second part, the resistivity of the first part of the gate structure is greater than 1000 ohms, and the resistivity of the second part of the gate structure is 8-20 ohms.
2. The power device of claim 1, wherein: the material of the first portion of the gate structure comprises undoped polysilicon and the material of the second portion of the gate structure comprises doped polysilicon.
3. The power device of claim 1, wherein: the material of the first portion of the gate structure comprises an undoped oxide semiconductor and the material of the second portion of the gate structure comprises a doped oxide semiconductor.
4. The power device of claim 1, wherein: the junction depth of the P-type well layer is not more than the filling thickness of the second part of the gate structure.
5. The power device of claim 1, wherein: the first dielectric layer also covers the N-type emitting layer.
6. The power device of claim 1, further comprising:
the second dielectric layer is positioned on the front side of the gate structure and is provided with a contact hole leading to the P-type well layer;
the emitter metal is positioned on the front side of the second dielectric layer and is electrically connected with the P-type well layer through the contact hole;
and the protective layer is positioned on the front side of the emitter metal, and part of the emitter metal is exposed by the protective layer.
7. The power device of any of claims 1-6, further comprising:
the buffer layer, the P-type collector layer and the collector metal are located on the back side of the N-type semiconductor substrate and are sequentially arranged along the direction far away from the N-type semiconductor substrate.
8. The power device of any of claims 1-6, further comprising:
a collector metal connected to a backside of the N-type semiconductor substrate.
9. A power electronic device comprising a power device according to any one of claims 1-8.
10. A method for manufacturing a power device comprises the following steps:
forming a groove on an N-type semiconductor substrate;
forming a first dielectric layer at least covering the bottom wall and the side wall of the groove;
forming a first part of a gate structure in the trench, wherein the filling thickness of the first part is less than the depth of the trench;
forming a second portion of the gate structure within the trench, the second portion being located on a front side of the first portion, wherein a resistivity of the first portion is greater than a resistivity of the second portion,
wherein the resistivity of the first portion of the gate structure is greater than 1000 ohms and the resistivity of the second portion of the gate structure is 8 to 20 ohms.
11. The method of manufacturing of claim 10, wherein:
the forming of the first part of the gate structure in the trench includes:
forming an undoped polysilicon layer in the trench, wherein the filling thickness of the undoped polysilicon layer is greater than the preset filling thickness of the first part of the gate structure;
etching the undoped polysilicon layer to form a first part of the gate structure;
the forming a second portion of the gate structure in the trench includes:
forming a doped polysilicon layer at least filling the trench;
and etching the doped polysilicon layer to form a second part of the gate structure.
12. The production method according to claim 10 or 11, further comprising:
forming a P-type well layer on the front side of the N-type semiconductor substrate, wherein the junction depth of the P-type well layer is not more than the filling thickness of the second part of the gate structure;
and forming an N-type emitting layer on the front side of the P-type well layer, wherein the N-type emitting layer is arranged around the groove.
13. The method of claim 12, wherein said forming a first dielectric layer overlying at least the bottom wall and the sidewalls of the trench comprises:
a first dielectric layer is formed overlying the bottom wall and sidewalls of the trench and the front side surface of the N-type semiconductor substrate.
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