KR20040111710A - Trench-gate semiconductor device and method of manufacturing - Google Patents

Abstract

Trench-gate semiconductor devices, such as MOSFETs or IGBTs, with field plates 24 provided below trenched gates 8 are processes with improved reproducibility. It is prepared using. This process involves etching a first groove 28a to receive a gate 8 into the semiconductor body 20 and a second groove into the upper major surface 20a of the semiconductor body 20. Etching 28b, wherein the second groove 28b extends from the bottom of the first groove 28a and is narrower than the first groove. The present invention can better control the vertical range of the gate under the upper major surface 20a of the semiconductor body.

Description

TRENCH-GATE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING}

Prior art trench-gate semiconductor devices are known to have source and drain regions of a first conductivity type isolated by channel-accommodating regions adjacent to the gate. US-A-5998833 discloses a vertical device of the type comprising a trench based source electrode between the gate electrode and the bottom of the trench. Trench based source electrodes are electrically connected to the source electrodes of such devices. It is also proposed to improve the breakdown and high frequency switching characteristics of the device while minimizing the effect on the specific on-state resistance of the device.

EP-A-1170803 discloses a structure similar to the structure mentioned above in connection with US-A-5998833. A "shield gate" is located below the gate electrode, close to the bottom of the trench. In particular, this patent discloses a device in which a shielding gate is connected to a source region. The contents of US-A-5998833 and EP-A-1170803 are incorporated herein by reference.

The present invention is for example insulated-gate field effect power transistors (commonly referred to as "MOSFET"), or insulated-gate bipolar transistors (commonly referred to as "MOSFET"). Is referred to as trench-gate semiconductor devices, such as " IGBT "

1 through 6 are cross-sectional views of transistor cell regions of a semiconductor body in successive fabrication steps in the fabrication of trench-gate semiconductor devices in accordance with one embodiment of the present invention.

FIG. 7 is a cross-sectional view taken along line A-A in the device shown in FIG. 6.

8 is an internal plan view of a package of discrete devices implementing the present invention.

9 is an internal plan view of a package of a module implementing the present invention.

10 and 11 are cross-sectional views of transistor cell regions of a semiconductor body in successive steps in the fabrication of trench-gate semiconductor devices in accordance with another embodiment of the present invention.

It is an object of the present invention to provide an improved method of fabricating a trench-gate semiconductor device having a trenched electrode under the gate.

The present invention provides a method of manufacturing a trench-gate semiconductor device, the trench-gate semiconductor device comprising a first portion of a trench having an insulated gate therein and a trench extending from a bottom of the first trench portion. A semiconductor body having two portions defined therein, wherein the semiconductor body includes a source region and a drain region of a first conductivity type isolated by a channel-receiving region adjacent to the first trench portion, the drain region having a drain contact region; A drain drift region (the drain drift region is between the channel-receiving region and the drain contact region, and the drain drift region is more lightly doped than the drain contact region), and the trench-gate semiconductor device has a gate and drain contact region Field plate in the second part of the trench between Including more, but this method,

(a) etching the first groove into the semiconductor body,

(b) adjoining a sidewall of the first groove, forming a spacer therebetween defining a window;

(c) etching the second groove into the semiconductor body through the window between the spacers, the second groove extending from the bottom of the first groove toward the drain contact region and narrower than the first groove; ,

(d) oxidizing the bottom and sidewalls of the second groove to form a field plate insulating layer.

In the process described above, the vertical range of the field plate insulation layer is self-aligned with respect to the bottom of the first groove due to the presence of the spacer. This results in higher uniformity of the device structure in the manufacture of the device.

In contrast, in the processor presented in US-A-5998833, for example, the vertical extent of the insulating layer around the trench-based source electrode is defined by the endpoint of the etch back step, It is not self aligned depending on the structure.

In a preferred embodiment, the method of the invention,

(e) filling the first and second grooves with electrode material and etching back until the field plate insulating layer is exposed to provide a field plate on the field plate insulating layer in the second groove;

(f) removing the spacers,

(g) forming a gate insulating layer over the field plate and at the bottom and sidewalls of the first groove,

(h) providing a gate over the gate insulating layer.

Thus, the etching back of the field plate electrode has a clearly defined end point, i.e. it is carried out until the top surface of the field plate insulating layer is exposed. Thus, the top of the field plate can be aligned with respect to the bottom of the first groove with reliability and reproducibility. Exposure of the field plate insulation layer can be detected using known spectroscopic techniques.

According to another preferred embodiment, the method of the invention,

(i) removing the spacers,

(j) forming a gate insulating layer on the bottom and sidewalls of the first groove,

(k) filling the first and second grooves with electrode material to form gate and field plates.

The present invention further provides a trench-gate semiconductor device manufactured according to the method disclosed herein, wherein the width of the first trench portion is greater than the width of the second trench portion.

In embodiments where the field plate is insulated from the gate, the field plate may be connected to the source region. Alternatively, the field plate may be connected with a bias potential that is greater than the gate potential and close to the bulk breakdown voltage of the drain drift region. Field plates connected in this manner A device having and a method for manufacturing the device are disclosed in British Patent Application No. 0212564.9 (Representative Document No. PHGB020083), co-pending by the applicant, the contents of which are incorporated herein by reference.

The inventors of the present invention connect this insulated field plate to a potential close to the bulk breakdown voltage of the drain drift region, in particular the voltage drop across the drain drift region when the applied voltage is greater than the bulk breakdown voltage. drop) is distributed more uniformly, confirming that the breakdown voltage of the device is substantially increased. This can result in a higher doping level used in the drain drift region compared to the device even when the field plates do not have the same breakdown characteristics, thereby providing a lower on-state resistivity for the device. have.

The present invention also provides a module comprising a device having a configuration as defined above with one or more other semiconductor devices, where the field plate is conveniently connected to the internal voltage line of the module. Alternatively, an additional external terminal electrically connected to the field plate may be provided above the device (in the case of a discrete device) or the corresponding module. This makes it possible to apply a dedicated voltage level for the field plate.

Next, embodiments of the present invention will be described by way of example with reference to the accompanying schematic drawings.

It is to be noted that the drawings are shown schematically and not to scale. The relative dimensions and proportions of parts in these figures have been exaggerated or reduced in size for clarity and convenience of the figures. In general, like reference numerals have been used to refer to corresponding or identical features within modified embodiments and different embodiments.

6 illustrates an exemplary embodiment of a power semiconductor device according to the present invention. Source and drain regions 2 and 4, each of a first conductivity type (which is n-type in this example), are isolated by a channel-receiving region 6 of a second conductivity type (which is p-type in this example) opposite it. It is.

By way of example, FIG. 6 shows a vertical device structure, where region 4a is a drain drift region formed by an epitaxial layer having a higher resistivity (weak doping) on the substrate, and the drain contact region. 4b has a relatively high conductivity. The drain drift and contact regions 4a and 4b form a junction 4c therebetween. The drain contact region 4b and the region 4a are formed of the same conductivity type (in this example, n-type) to produce a vertical MOSFET, or the opposite conductivity type (in this example, p-type) to form a vertical IGBT. Can be.

Gate 8 is present in first trench portion 10a that passes through regions 2 and 6 and extends to the lower portion of drain drift region 4a. Popularity of the voltage signal to gate 8 in a known manner in the on-state of the device leads to conductive channel 16 in region 6 and between such conductive channel 16 between source and drain regions 2 and 4. Current flow can be controlled within

In the case of a MOSFET, the source region 2 is connected by the source electrode 18 at the upper major surface 20a of the semiconductor body 20 (typically made of single crystal silicon) of the device. In the case of a MOSFET, the drain contact region 4b is connected by an electrode 22 referred to as a drain electrode at the bottom major surface 20b of the device semiconductor body 20. Source and drain electrodes 18 and 22 are known as emitters and collectors in the IGBTs, respectively.

The field plate 24 is provided in the second trench portion 10b between the gate 8 and the drain drift region 4a. The field plate is preferably formed of doped polycrystalline silicon of the first conductivity type. Alternatively, the field plate may be made of metal, for example. The field plate 24 is insulated from the surrounding semiconductor body 20 by the field plate insulating layer 26b. The gate 8 is insulated from the field plate 24, the semiconductor body 20 and the source electrode 28 by the gate insulating layer 26a. This insulating layer may for example be made of silicon dioxide.

In the embodiment shown in FIG. 6, the second trench portion 10b extends into the semiconductor body 20 to a depth close to the junction 4c between the drain drift and the contact regions 4a and 4b. . As is well known in the art, in practice, there is a doping transition region between region 4a and region 4b, in which the drain drift region from the more heavily doped drain contact region is present. As a result, dopant atoms dominate. Typically, this out-diffusion extends from 1 μm to 1.5 μm above the junction 4c. The second trench portion 10b preferably extends to a depth just above the transition region.

The field plate 24 is spaced apart from the bottom and sidewalls of the second trench portion 10b by an insulating material layer 26b having a thickness t1. The gate 8 is spaced apart from the semiconductor body and the field plate by a layer of insulating material having a thickness t2. For example, the thickness t2 may be about 38 nm, and the thickness t1 may be about 0.4 μm. Especially in the case of doping at a higher level in the drain drift region 4a, by placing a relatively thick layer (ie t1) under the field plate, it is possible to withstand the high electric field generated at the corners of the trench. desirable.

FIG. 7 illustrates a cross-sectional view taken along line A-A in the device shown in FIG. 6. This figure shows an example of a method of forming a connection from the outside of the semiconductor body 20 to the field plate 24, regardless of the gate and source electrodes.

The doped polycrystalline silicon contact layer 39 is provided at one end of the first trench portion 10a and is electrically connected to the field plate 24. This layer extends from the field plate to the upper main surface 20a of the device semiconductor body 20 and is connected by the field plate contact electrode 41. The gate 8 is electrically connected to the gate contact electrode 40 at the other end of the first trench portion 10a.

In the following, the subsequent manufacturing steps of the transistor cell shown in FIG. 6 will be described with reference to FIGS. 1 to 6.

First, a thin layer 30 of silicon dioxide is grown on the upper major surface 20a of the semiconductor body 20 (FIG. 1). A mask 32 is provided thereon, which may be formed in a standard manner using photolithography and etching. For example, the mask may be formed of photoresist and define a window 32a.

Next, an etching process is performed in the window 32a of the mask 32 to form the first groove 28a as shown in FIG. Next, a uniform silicon nitride layer is deposited (for example), and anisotropic etching is performed to leave the spacer 34 in a portion adjacent to the sidewall of the first groove 28a (see FIG. 3). Next, a window 34a is defined between the spacers 34 for the subsequent etching process to form a second groove 28b extending downward from the bottom of the first groove 28a into the semiconductor body.

Next, as shown in FIG. 4, an oxidation process is performed to form an oxide layer 26b on the bottom and sidewalls of the second groove 28b. Preferably, thermal oxidation is performed. This consumes silicon at the surface of the silicon and the resulting layer extends approximately the same distance from the side of the original silicon surface. For example, the oxide can be grown by 0.2 μm in each direction to form a 0.4 μm thick layer. The boundary portion between the field plate insulating layer 26b and the semiconductor body 20 defines the second trench portion 10b of the finished device, while the first groove 28a defines the first, wider trench portion ( 10a). After the doped polycrystalline silicon is deposited in a known manner, the field plate 24 is formed by etching back, leaving the material only in a space surrounded by three surfaces by the insulating layer 26b. The end point of this etching step is clearly defined, where it is defined as the point where the insulating layer 26b is exposed as the polycrystalline silicon is etched back to the bottom level of the first trench portion. For example, refractive index monitoring can be used to detect the top surface exposure of the insulating layer 26b.

Although the first trench portion 10a is wider than the second trench portion 10b in the embodiment shown in FIG. 4, the process described is substantially the same width as the first and second portions 10a and 10b. It will be appreciated that this may be done in a way that makes

Next, the spacer 34 is removed using, for example, a spray etch process. A thin gate insulating layer 26a is deposited substantially on the sidewalls and bottom of the first trench portion 10a and also on the exposed top surface of the field plate 24. A second sequential deposition and etch back of the doped polycrystalline silicon is then performed to form the gate 8 in the first trench portion 10a as shown in FIG.

Additional processes are carried out in a known manner in order to implant the source region 2 and the channel-receiving region 6, the insulating cap 38 over the gate 8, the top of the semiconductor body and By forming the source and drain electrodes 18 and 22 respectively on the bottom major surfaces 20a and 20b, the structure shown in FIG. 6 is formed.

As mentioned in US-A-5998833 and EP-A-1170803, it is advantageous for device performance to include trenched field plates connected to the source region in the trench-gate device. In addition, the present invention applies a bias potential greater than the gate potential to the field plate and close to the bulk breakdown voltage of the drain drift region allows for further performance improvement. In particular, the bias potential is preferably about 60 to 100% of the bulk breakdown voltage in the drain drift region. More specifically, the bias potential is preferably about 80% of the bulk breakdown voltage of the drain drift region, which causes drain drift regions and drain contacts that can cause variations in doping levels in the drain drift region around the bottom of the trench. This is because a certain degree of tolerance can be tolerated for the variation of the width of the transition region between the regions.

8 is an internal plan view of a package of a discrete device according to an embodiment of the present invention. MOSFET die 40 includes a gate bond pad 42 connected to its gate contact electrode and a source bond connected to its source contact electrode to apply independent bias voltages for each; A pad 48 and a field plate bond pad 44 connected to the field plate contact electrode thereof. The MOSFET is mounted on the drain pad 46, and the drain pad 46 is electrically connected to the drain electrode 22 on the bottom major surface of the MOSFET die. Bond wires 50 connect the bond pads 42, 44, 48 to respective terminals or pins 52, 54, 58. The drain pads 46 are directly connected to the respective pins 56. The packaging process can be completed in a known manner.

In a preferred embodiment of the present invention, a semiconductor device as described above is included in a module with its field plate (s) connected to the level of an internal voltage line or module. As an example of this, Figure 9 shows an internal plan view of a package of a module 60 comprising two semiconductor devices having field plates biased in the form described above. Such a module is a DC-DC converter and is used, for example, as a VRM in a PC motherboard. Known DC-DC converter circuits and their operation are disclosed in U.S. Patent Application No. US-B-6175225 by Agent Applicant No. PHB34370, the contents of which are incorporated herein by reference. . The configuration shown in FIG. 9 is a modified embodiment of the circuit shown in FIG. 3 of US-13-6175225.

The module shown in FIG. 9 includes a control MOSFET 62, a “sync” MOSFET 64, and a drive IC 66. The MOSFETs correspond to the first and second switches 5, 6 shown in FIG. 3 of US-B-6175225, respectively. They are connected in series between the DC input terminal (V _DD ) and ground (V _SS ). The switches are alternately closed in response to the switching signal PWM _IN input to the driver IC 66. Additional operation for this type of circuit is disclosed in US-B-6175225.

According to the present invention, each MOSFET 62, 64 includes a field plate bond pad 68 connected to respective field plate contact electrodes of each MOSFET. The field plate bond pads of the sink MOSFET 64 are connected to a power supply voltage (V _CC ) (eg, typically 5V or 12V) via the drive IC. In the circuit shown in FIG. 3 of US-B-6175225, the gate drive is connected to the control MOSFET ("first switch 5" via a boost or storage capacitor 37 connected between boost terminal 33 and Vout. ) "). In this case, the field plate bond pads of the control MOSFET 62 will be connected to the boost terminal 33.

In the example where V _CC is 12V, the silicon selected for the MOSFETs 62, 64 may have a bulk breakdown voltage of, for example, approximately 15V or more.

It will be appreciated that other potentials can be provided within the module, for example, by using the external pins of the module for connection to the field plate bond pads of the MOSFET or by including additional circuitry within the module.

The lightly doped drain drift region 4a is typically grown as an epitaxial layer of the first conductivity type. The doping concentration of the drift region may be substantially uniform over its depth direction. Nevertheless, it may be desirable to vary the concentration over the drift region. In particular, providing a doping profile in which the concentration is reduced (eg linearly) in the direction from the drain contact region 4b towards the channel-receiving region 6 can reduce the on-resistance of the device.

The process described above with reference to FIGS. 1-6 may be modified in another embodiment of the present invention. In particular, after the growth of the field plate insulating layer 26b described in connection with FIG. 4 as described above, the spacer 34 is removed and the electrode material is deposited as shown in FIG. 10 to deposit the first and second trenches. The gate insulating layer 26a ′ may be deposited (or thermally grown) on the sidewalls and bottom of the first trench portion 10a prior to filling both portions 10a and 10b. The electrode material is at a planarized level with the silicon dioxide layer 30 on the upper major surface 20a of the semiconductor body 20. Thus, in this embodiment, the field plate 24 is integrated with the gate 8. Providing a field plate with a gate potential that extends into the drain drift region improves the breakdown characteristics of the device.

Next, on the gate 8 and the source region 2 and the channel-receiving region 6 implanted by performing other processes in a known manner, in the same manner as the embodiment described in FIGS. By forming the insulating caps 38 and the source and drain electrodes 18 and 22, respectively, on the upper and bottom major surfaces 20a and 20b of the semiconductor body, thereby forming the structure shown in FIG.

It is apparent that various changes and modifications can be made within the scope of the present invention. The specific example described above is an n-channel device, where the source and drain regions 2, 4 have an n-type conductivity type, the channel-receiving body region 6 has a p-type conductivity type, and the gate 8 Is induced in region 6 by electron inversion channel 16. By using dopants with opposite conductivity types, p-channel devices can be fabricated. In this case, regions 2 and 4 are p-type, region 6 is n-type, and a hole inversion channel is induced in region 6 by gate 8.

In addition, such a device can be manufactured in p-channel type according to the invention and have p-type source and drain regions 2 and 4 and p-type channel-receiving region 6. In addition, an n-type deep localized region may exist in each cell. N-type polycrystalline silicon may be used for the gate 8. In operation, a hole accumulation channel 16 is induced in the region 6 by the gate 8 in the on state. The p-type region 6 lightly doped by the isolation gate 8 and the depletion layers in the deep n-type region may be entirely depleted in the off state.

The vertical discrete device is shown with reference to FIGS. 1 to 7, wherein the drain electrode 22 of the vertical discrete device is connected to the area 4b at the back surface 20b of the body 20. However, in accordance with the present invention an integrated device would be possible. In this case, region 4b may be a doped buried layer between the device substrate and the lightly doped epitaxial drain region 4a. This buried layer region 4b is formed by an electrode at the front major surface 20a via a doped peripheral contact region extending from the front major surface 20a in the depth direction of the buried layer. Can be connected.

For the device according to the invention, for example, a semiconductor material other than silicon, such as silicon carbide, can be used.

Since the present invention can be applied quite differently from known cell shapes, it does not present a plan view of the cell layout shape for the longitudinal device in the figures. Thus, for example, such a cell may have a rectangular shape, a dense hexagon shape, or an elongated stripe shape. In each case, trench 10 (along with its gate 8) extends around the periphery of each cell. 1 to 7 show only two cells, but typically such a device includes hundreds of such parallel cells between the electrodes 18, 22. Similarly, only one cell is shown in FIG. 6 for illustration.

The active cellular area of the device may be defined around the periphery of the body 20 by various known peripheral termination schemes (not shown). This technique generally involves the formation of a thick field-oxide layer in the peripheral area of the body surface 20a prior to the transistor cell fabrication step. Several known circuits (such as gate-control circuits) Can be integrated with the device within the area of the body 20 between the active cell area and the peripheral termination design. Typically, the circuit elements can be fabricated in their own layout within these circuit areas using some of the same fabrication and doping steps used in transistor cells.

Those skilled in the art will appreciate other variations and modifications by reading the present disclosure. Such variations and modifications may include equivalents or other features that are already known in the art and that may be used in addition to or in addition to the features set forth herein.

In the present patent claims are formed with a combination of specific features, the scope of the disclosure of the present invention, whether or not related to the same invention as currently claimed in any claim, is also the same technical problem as solved in the present invention. It is to be understood that, regardless of whether some or all of the above may be resolved, any new feature or combination of any new features, explicitly or implicitly described herein, may be included or a generalized form thereof may be included. will be.

The Applicant noted that new features may be formed by these and / or combinations of these features during the execution of this patent or any other patent derived from this patent.

Claims (10)

A method of manufacturing a trench-gate semiconductor device, The trench-gate semiconductor device includes a first portion 10a of a trench having an insulated gate 8 therein and a second portion 10b of the trench extending from the bottom of the first trench portion 10a. Includes a semiconductor body 20, The semiconductor body comprises a source region 2 and a drain region 4 of a first conductivity type isolated by a channel-accommodating region 6 adjacent to the first trench portion 10a. , The drain region 4 includes a drain contact region 4b and a drain drift region 4a, wherein the drain drift region 4a is between the channel-receiving region 6 and the drain contact region 4b. Wherein the drain drift region is more lightly doped than the drain contact region, The trench-gate semiconductor device further comprises a field plate 24 in the second portion 10b of the trench between the gate 8 and the drain contact region 4b, The method, (a) etching a first groove 28a into the semiconductor body 20, (b) forming a spacer 34 adjacent a sidewall of the first groove 28a, the window 34a being defined between the spacers 34, (c) etching a second groove 28b into the semiconductor body 20 through the window 34a between the spacers 34, wherein the second groove 28b is formed of the first groove. Extends from the bottom toward the drain contact region 4b and is narrower in width than the first groove 28a; (d) oxidizing the bottom and sidewalls of the second groove 28b to form a field plate insulating layer 26b. The trench-gate semiconductor device manufacturing method comprising a. The method of claim 1, (e) Filling the first and second grooves 28a, 28b with electrode material and etching back until the field plate insulating layer is exposed, thereby leaving the field plates in the second groove 28b. Providing the field plate 24 on the insulating layer 26b; (f) removing the spacer 34; (g) forming a gate insulating layer 26a on the field plate 24 and on the bottom and sidewalls of the first groove 28a; (h) providing the gate 8 on the gate insulating layer The trench-gate semiconductor device manufacturing method comprising a. The method of claim 1, (i) removing the spacer 34; (j) forming a gate insulating layer 26a on the bottom and sidewalls of the first groove 28a; (k) filling the first and second grooves 28a, 28b with electrode material to form the gate 8 and field plate 24; The trench-gate semiconductor device manufacturing method comprising a. A trench-gate semiconductor device manufactured according to the method of any one of claims 1 to 3, wherein A trench-gate semiconductor device in which the width of the first trench portion (10a) is wider than the width of the second trench portion (10b). A trench-gate semiconductor device manufactured according to the method of claim 2, The field plate (24) is connected to the source region (2) in a trench-gate semiconductor device. A trench-gate semiconductor device manufactured according to the method of claim 2, The field plate (24) is greater than the gate potential and is connected to a bias potential approaching the bulk breakdown voltage of the drain drift region (4a). A module 60 comprising the device of claim 6, The field plate (24) is connected to the internal voltage line of the module. In the device according to claim 6 or the module according to claim 7, Device or module providing an additional external terminal (54) electrically connected to the field plate (24). In the device according to claim 6 or 7, or the module according to claim 7 or 8, The bias potential is approximately 60 to 100% of the bulk breakdown voltage of the drain drift region (4a). The method of claim 9, The bias potential is approximately 80% of the bulk breakdown voltage of the drain drift region (4a).