CN111261702A - Trench type power device and forming method thereof - Google Patents

Trench type power device and forming method thereof Download PDF

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Publication number
CN111261702A
CN111261702A CN201811467502.XA CN201811467502A CN111261702A CN 111261702 A CN111261702 A CN 111261702A CN 201811467502 A CN201811467502 A CN 201811467502A CN 111261702 A CN111261702 A CN 111261702A
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Prior art keywords
layer
trench
cell
metal
insulating
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肖婷
史波
曾丹
廖勇波
敖利波
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Gree Electric Appliances Inc of Zhuhai
Zhuhai Zero Boundary Integrated Circuit Co Ltd
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Gree Electric Appliances Inc of Zhuhai
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Priority to CN201811467502.XA priority Critical patent/CN111261702A/en
Priority to PCT/CN2019/110318 priority patent/WO2020114072A1/en
Publication of CN111261702A publication Critical patent/CN111261702A/en
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    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
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Abstract

The invention discloses a groove type power device and a forming method thereof, wherein the device comprises a plurality of unit cells, and each unit cell comprises: the structure comprises a cellular trench, a polycrystalline silicon layer formed on the side wall of the cellular trench and a filling metal layer filled in the cellular trench; the filling metal layer, the polycrystalline silicon layer and the inner wall of the cellular groove are arranged in an insulating mode respectively. The polycrystalline silicon (grid) is formed on the side wall of the cellular groove, and a polycrystalline silicon-filled metal layer-polycrystalline silicon composite structure is formed, so that Cgc reverse capacitance in the using process of the device is improved, the switching characteristic of a chip is improved, and meanwhile, the switching loss can be reduced.

Description

Trench type power device and forming method thereof
Technical Field
The invention relates to the field of semiconductors, in particular to a trench type power device and a forming method thereof.
Background
As known to those skilled in the art, the trench power device has the characteristics of high integration level, low on-resistance, fast switching speed and low switching loss, and is widely applied to various power management and switching conversion circuits. With the increasing emphasis on energy conservation and emission reduction in China, the requirements on the loss and the conversion efficiency of power devices are higher and higher. The conduction loss is mainly influenced by the conduction resistance, and the smaller the characteristic conduction resistance is, the smaller the conduction loss is; the switching losses are mainly affected by the gate charge, and the smaller the gate charge, the smaller the switching losses. Therefore, reducing the on-resistance and the gate charge are two effective ways to reduce the power consumption of the power device, and the energy can be used more efficiently by reducing the power consumption of the power device.
In the preparation process of a semiconductor power device, there are two methods for reducing the characteristic on-resistance: one is to increase the total effective width of the unit cell by increasing the unit cell density. However, after the unit cell density is increased, the corresponding gate charge is increased, and the on-resistance and the gate charge cannot be reduced; and secondly, the doping concentration of the epitaxial wafer is improved, the thickness of the epitaxial layer is reduced, and the breakdown voltage between the source electrode and the drain electrode is reduced.
Disclosure of Invention
The invention aims to provide a trench type power device and a forming method thereof, so as to reduce switching loss.
To this end, the present invention provides a slot type power device, which includes a plurality of unit cells, each of the unit cells includes: the structure comprises a cellular trench, a polycrystalline silicon layer formed on the side wall of the cellular trench and a filling metal layer filled in the cellular trench; the filling metal layer, the polycrystalline silicon layer and the inner wall of the cellular groove are arranged in an insulating mode respectively.
Preferably, the cell comprises an insulating gate oxide layer formed between the polysilicon layer and the cell trench sidewall; and an insulating oxide layer formed between the polysilicon layer and the filling metal layer.
Preferably, the filling metal layer is in direct contact with the source metal layer or the drain metal layer.
Preferably, the unit cell is arranged in a semiconductor substrate, the unit cell comprises a doped region which has the same and/or different conductivity type with the semiconductor substrate, and the doped region is connected with a source metal layer or a drain metal layer through a metal material layer.
Preferably, the layer of metallic material is insulatively spaced from the layer of filler metal.
Preferably, the metal material layer and the filling metal layer are arranged in an insulating mode through an insulating gate oxide layer.
Preferably, the metal material layer and the filling metal layer are made of the same material.
Preferably, the unit cell is disposed in a semiconductor substrate, a well region is formed between the bottom of the unit cell trench and the semiconductor substrate, and the filling metal layer is disposed in an insulating manner with respect to the well region.
Meanwhile, the invention also provides a method for forming the trench type power device, wherein the device comprises a plurality of unit cells, and the method for forming the unit cells comprises the following steps:
etching to form a cellular groove;
growing an insulating gate oxide layer on the inner wall of the cellular trench;
forming a polycrystalline silicon layer on the side wall of the cellular trench on the insulating gate oxide layer;
forming an insulating oxide layer covering the polycrystalline silicon layer on the polycrystalline silicon layer;
and forming a filling metal layer on the insulating oxide layer to fill the cell groove.
Preferably, in the step of forming the unit cell, before growing the insulating gate oxide layer, ion implantation is further performed on the bottom wall of the trench of the unit cell to form a well region.
By applying the groove type power device and the forming method thereof, the polycrystalline silicon (grid) is formed on the side wall of the cell groove, and the polycrystalline silicon-filled metal layer-polycrystalline silicon composite structure is formed, so that the Cgc reverse capacitance in the using process of the device is improved, the switching characteristic of a chip is improved, and the switching loss can be reduced.
In addition, the well region is formed at the lower part of the cell unit, so that the field plate structure is formed by the filling metal layer, the oxidation layer and the well region filled in the cell groove, the electric field aggregation at the bottom of the cell groove can be effectively improved, the electric field at the bottom can be effectively suppressed, and the reliability of the device can be improved.
Drawings
Fig. 1 is a cross-sectional view of a trench-type power device according to the prior art;
fig. 2 is a cross-sectional view of a trench power device according to the present invention;
fig. 3 is a diagram illustrating a capacitance distribution around a cell trench in a trench type power device according to the present invention;
fig. 4 is a cross-sectional view of another trench power device in accordance with the present invention;
fig. 5 is a diagram of an electric field distribution around a cell trench in a trench type power device according to the present invention;
FIG. 6 is a flow chart of the preparation of a trench type power device according to the present invention
Fig. 7-15 are cross-sectional views of various steps of a trench power device according to the present invention.
Detailed Description
The present invention will be described in further detail with reference to the following examples, which are not intended to limit the invention thereto.
As shown in fig. 1, fig. 1 is a cross-sectional view of a trench type power device according to the prior art, in the trench type power device shown in fig. 1, a plurality of cells are included, each of the cells includes: a cell trench and a polysilicon layer 33' completely filled in the cell trench; each cell further comprises a body region 40 'and a doped region 51' located at the periphery of the cell trench; wherein the polysilicon layer 33 'is covered with an insulating oxide layer 34', and a metal electrode layer 70 'is formed over the insulating oxide layer 34'. In the trench type power device shown in fig. 1, large reverse capacitances are formed between the polysilicon layer 33 'located inside the cell trench and the semiconductor substrate 30', the body region 40 ', and the doped region 51' located at the periphery, and the existence of these reverse capacitances will limit the switching characteristics to a certain extent.
Based on the existence of such a current situation, in the first embodiment of the invention, there is provided a trench type power device, as shown in fig. 2, which includes a first metal electrode layer 10, a first semiconductor type substrate 20, a second semiconductor type substrate 30, a second semiconductor type buffer layer 30a existing between the first semiconductor type substrate 20 and the second semiconductor type substrate 30; a plurality of unit cells whose structures are repeated are formed in a substrate 30 of a second semiconductor type as a semiconductor substrate; wherein each of the cells comprises: the cell structure comprises a cell trench 31, a polysilicon layer 33 formed on the side wall of the cell trench, and a filling metal layer 35 filled in the cell trench; the filling metal layer 35, the polysilicon layer 33, and the inner wall of the cell trench 31 are insulated from each other.
In the trench type power device, Cies, Coes and Cres affect the turn-on and turn-off time and turn-on and turn-off delay time of the IGBT device, so that the switching loss of the IGBT is affected, and the calculation formulas of the Cies, Coes and Cres are as follows:
Cies＝Cge+Cgc
Coes＝Cce+Cgc
Cres＝Cgc
as shown in fig. 3, fig. 3 is a diagram illustrating a capacitance distribution around a cell trench of a trench type power device according to the present invention. As can be seen from fig. 3, Cgc (gate-collector capacitance, also called miller capacitance) is effectively reduced; also, in the same area, the cci (collector-emitter capacitance) is relatively reduced. This can be inferred that the cis (input capacitance), the Coes (output capacitance), and the Cres (miller capacitance) are all reduced, the parasitic capacitance is reduced, and the switching loss can be effectively reduced. In addition, as can be seen from fig. 3, the capacitance Cgc at the bottom of the cell trench in the trench power device of the present invention is not present, the total Cgc is reduced, and the switching loss is reduced; meanwhile, in the same area, the trench structure is wider than the conventional trench structure due to the limitation of process conditions, and compared with the Cce capacitor, the width of the trench structure is reduced.
As shown in fig. 2, the cell further includes an insulating gate oxide layer 32 formed between the polysilicon layer 33 and the sidewall of the cell trench 31; and an insulating oxide layer 34 formed between the polysilicon layer 33 and the filling metal layer 35; the insulating gate oxide layer 32 and the insulating oxide layer 34 may be made of conventional materials used for trench power devices, as long as the inner walls of the filling metal layer 35, the polysilicon layer 33, and the cell trench 31 are respectively insulated from each other.
According to the trench type power device, the thickness of the single side of the polysilicon layer 33 formed on the side wall of the cell trench can be reasonably set according to the size of a single cell; preferably, the polysilicon layer 33 has a single-sided thickness of 0.3 μm to 1.5 μm. Wherein the thickness of the polysilicon layer 33 is a thickness perpendicular to the sidewall direction of the cell trench 31.
According to the trench power device of the present invention, the object of the present invention can be achieved to a certain extent by filling the filling metal layer 35 in the cell trench 31, and preferably, the thickness ratio of the filling metal layer 35 to the single-sided polysilicon layer 33 in the direction perpendicular to the sidewall of the cell trench 31 is 10:1-1: 1.
As shown in fig. 2, in each cell includes a body region 40 formed in a substrate 30 of a second semiconductor type, the body region 40 having a different conductivity type from the substrate 30 of the second semiconductor type; also included in each cell is a doped region 51, 52 (also referred to as an implanted region) of the first semiconductor type and/or the second semiconductor type formed in body region 40; wherein a part of the surface of the doped regions 51, 52 of the first and/or second semiconductor type is exposed forming an exposed surface of the cell. Wherein the doped regions 51, 52 of the first and/or second semiconductor type partially overlap when the doped regions 51, 52 of the first and/or second semiconductor type are present in the body region 40 at the same time. Wherein the doped region 52 of the second semiconductor type is disposed near the sidewall of the cell trench 31, and more preferably, a part of the surface of the doped region 52 of the second semiconductor type is used as the sidewall of the cell trench 31.
As shown in fig. 2, a metal material layer 60 is further formed on the surface of the second semiconductor type substrate 30 on which the plurality of unit cells are formed, and the doped regions 51 and 52 of the first semiconductor type and/or the second semiconductor type in each unit cell are in direct contact with the metal material layer 60. Preferably, the metal material layer 60 and the filling metal layer 35 are arranged in an insulating manner; preferably, the metal material layer 60 is insulated and separated from the filling metal layer 35 by the insulating gate oxide layer 32. The metal material layer 60 and the filling metal layer 35 in the present invention are made of the same material or different materials; preferably, the metal material layer 60 and the metal filling layer 35 are made of the same material, and both are made of metal tungsten.
As shown in fig. 2, a second metal electrode layer 70 is formed on the metal material layer 60, wherein the metal filling layer 35 is in direct contact with the second metal electrode layer 70.
In the above embodiment, the first metal electrode layer 10 and the second metal electrode layer 70 are a source metal layer and a drain metal layer each other; the first semiconductor type and the second semiconductor type are an N-type semiconductor and a P-type semiconductor; wherein trench type power devices may be used for the first metal electrode layer 10 and the second metal electrode layer 70, and the first semiconductor type material and the second semiconductor type material.
In the second embodiment of the present invention, a trench type power device is provided, as shown in fig. 4, which has a similar structure to the trench type power device provided in the first embodiment, and the main difference therebetween is that in this second embodiment, in addition to forming a polysilicon layer 33 on the side wall of a cell trench 31, forming a filling metal layer 35 inside the cell trench 31, a well region 36 is formed between the bottom of the cell trench 31 and the semiconductor substrate (substrate 30 of the second semiconductor type), and the filling metal layer 35 is disposed in an insulated manner from the well region 36.
As shown in fig. 5, fig. 5 shows an electric field distribution pattern around a cell trench in a trench type power device according to a second embodiment of the present invention. As shown in fig. 5, in the present invention, a polysilicon gate is formed only on the sidewall of the trench, and then a metal filling layer (for example, metal tungsten) is formed inside the cell trench, thereby forming a metal field plate of a tungsten plug filling structure; therefore, even if a wide groove design structure is adopted, the surface electric field at the bottom of the cell groove can be reduced; and also. The effect of the electric field is further reduced by forming a well region below the trench.
In the above trench type power device, the electric field can be reduced to some extent as long as the well region 36 is formed between the bottom of the cell trench 31 and the semiconductor substrate (the second semiconductor type substrate 30), and it is preferable in the present invention that the well region has a thickness of not more than 10 μm, where the thickness of the well region is a thickness perpendicular to the bottom direction of the cell trench. The ion implantation rate of the well region 36 located at the bottom of the cell trench 31 can be selected according to the surface electric field at the bottom of the cell trench, and preferably, the ion implantation rate of the well region 36 located at the bottom of the cell trench 31 is 1.0E13-3.5E 17.
In a third embodiment of the present invention, a method for forming a trench type power device is provided, as shown in fig. 6, the device includes a plurality of unit cells, and the forming of the unit cells includes the following steps:
s1, etching to form a cell groove;
s2, growing an insulating gate oxide layer on the inner wall of the cellular trench;
s3, forming a polysilicon layer on the side wall of the cellular trench on the insulation gate oxide layer;
s4, forming an insulating oxide layer wrapping the polycrystalline silicon layer on the polycrystalline silicon layer;
and S5, forming a filling metal layer on the insulating oxide layer to fill the cell groove.
Preferably, in the step of forming the unit cell, before growing the insulating gate oxide layer, ion implantation is further performed on the bottom wall of the trench of the unit cell to form a well region.
Next, referring to fig. 7 to 15, a method for forming a trench power device according to the present invention is described in detail by taking an N-channel as an example, and includes the steps of:
(1) selecting a silicon substrate wafer including a first semiconductor type substrate 20, a second semiconductor type buffer sheet 30a, and a second semiconductor type substrate 30 to form a structure as shown in fig. 7; processing the silicon substrate wafer through a photoetching process to form a graph of a cellular groove structure of each cellular; then, a reactive plasma etching process is adopted to etch a cell groove 31 on the silicon wafer with the cell groove pattern, so as to form the structure shown in FIG. 8;
2) growing an insulating gate oxide layer 32 on the silicon substrate wafer on which the cell trenches 31 are formed by using a thermal oxidation process to form a structure as shown in fig. 9;
4) depositing a layer of polycrystalline silicon film on the surface of the insulating gate oxide layer 32 by adopting a chemical vapor deposition process to be used as a gate of the IGBT device, and forming a structure shown in figure 10;
5) etching the polysilicon film by using a reactive plasma etching process to form a polysilicon layer, also called polysilicon sidewall gate, on the sidewall of the cell trench 31, thereby forming the structure shown in fig. 11;
6) injecting ions into the bottom wall of the cell groove 31 by adopting an ion injection process and a thermal diffusion process to form a P-type well region; injecting ions at the periphery of the side wall of the cellular trench 31 to form a P-type body region; implanting ions into the P-type body region to form an N + doped region and a P + doped region, thereby forming the structure shown in fig. 12;
7) depositing an oxide insulating layer 34 on the surface of the prepared structure by chemical vapor deposition as an electrical isolation layer, and then performing contact hole pattern lithography and contact hole oxide layer etching by reactive plasma etching to form the structure shown in fig. 13;
8) and depositing a layer of metal tungsten film on the surface of the prepared structural body by adopting a chemical vapor deposition process, and filling the metal tungsten film into the contact hole and the trench gate structure. Then, etching the redundant metal tungsten on the surface by using an etching process to form a metal material layer 60 and a filling metal layer 35, thereby forming a contact hole tungsten plug structure and a trench gate tungsten plug field plate structure to form the structure shown in fig. 14;
9) depositing a layer of thick metal aluminum on the surface by adopting a magnetron sputtering process, and forming a grid electrode and an emitting electrode lead-out metal of the IGBT device by adopting photoetching and etching processes to form a structure shown in figure 15;
10) and carrying out back thinning and a standard FS-IGBT back process.
In the trench type power device for forming the P channel, the process is basically the same as that of the trench type power device for forming the N channel, and mainly the selection of materials and the selection of implanted ions are different, and the differences can be obtained by referring to the conventional selection in the industry.
Of course, the above is a preferred embodiment of the present invention. It should be noted that, for a person skilled in the art, several modifications and refinements can be made without departing from the basic principle of the invention, and these modifications and refinements are also considered to be within the protective scope of the invention.

Claims (10)

1. A trench type power device is characterized by comprising a plurality of unit cells, wherein each unit cell comprises: the structure comprises a cellular trench, a polycrystalline silicon layer formed on the side wall of the cellular trench and a filling metal layer filled in the cellular trench; the filling metal layer, the polycrystalline silicon layer and the inner wall of the cellular groove are arranged in an insulating mode respectively.
2. The device of claim 1, wherein the cell comprises an insulating gate oxide layer formed between the polysilicon layer and the cell trench sidewalls; and an insulating oxide layer formed between the polysilicon layer and the filling metal layer.
3. The device of claim 1, wherein the fill metal layer is in direct contact with a source metal layer or a drain metal layer.
4. The device of claim 3, wherein the unit cell is disposed within a semiconductor substrate, the unit cell comprising a doped region of the same and/or different conductivity type as the semiconductor substrate, the doped region being connected to a source metal layer or a drain metal layer by a layer of metal material.
5. The device of claim 3, wherein the layer of metallic material is insulatively spaced from the layer of fill metal.
6. The device of claim 3, wherein the metal material layer and the fill metal layer are disposed in an insulating manner through an insulating gate oxide layer.
7. The device of claim 2, wherein the metal material layer and the metal filling layer are made of the same material and are both metal tungsten.
8. The device of claim 1, wherein the cell is disposed in a semiconductor substrate, a well region is formed between a bottom of the cell trench and the semiconductor substrate, and the fill metal layer is disposed in an insulating manner from the well region.
9. A method for forming a trench type power device, the device comprising a plurality of unit cells, the method comprising the steps of:
etching to form a cellular groove;
growing an insulating gate oxide layer on the inner wall of the cellular trench;
forming a polycrystalline silicon layer on the side wall of the cellular trench on the insulating gate oxide layer;
forming an insulating oxide layer covering the polycrystalline silicon layer on the polycrystalline silicon layer;
and forming a filling metal layer on the insulating oxide layer to fill the cell groove.
10. The method of claim 9 wherein the step of forming the unit cells further comprises ion implanting a bottom wall of a trench of the unit cells to form a well region prior to growing the insulating gate oxide layer.
CN201811467502.XA 2018-12-03 2018-12-03 Trench type power device and forming method thereof Pending CN111261702A (en)

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