CN108831832B - Manufacturing method of groove step gate IGBT chip - Google Patents
Manufacturing method of groove step gate IGBT chip Download PDFInfo
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- 238000007254 oxidation reaction Methods 0.000 claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 36
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 15
- 238000002347 injection Methods 0.000 claims description 12
- 239000007924 injection Substances 0.000 claims description 12
- 238000004151 rapid thermal annealing Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
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- 229910052796 boron Inorganic materials 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 239000007787 solid Substances 0.000 description 4
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/42312—Gate electrodes for field effect devices
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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Abstract
The invention discloses a manufacturing method of a groove step gate IGBT chip, which comprises the following steps: forming a first oxide layer on the upper surface of the wafer substrate; injecting N-type impurities into the wafer substrate, and diffusing the N-type impurities into a first junction depth to form an N well; injecting P-type impurities into the N well, and diffusing the P-type impurities to a second junction depth to form a P well; etching a first preset position on the first oxidation layer, a P well and an N well which correspond to the lower part of the first preset position, and a wafer substrate below the N well to form a groove; removing the remaining first oxide layer, and forming a second oxide layer with a first thickness on the upper surface of the P well and the inner surface of the groove; etching the second oxide layer on the upper surface of the P well and the inner surface of the upper part of the preset groove in the groove, and forming a third oxide layer with a second thickness at the corresponding position; and filling polycrystalline silicon in the groove to form a groove grid with a step shape. The IGBT chip current density is improved, and meanwhile, the electrical performance and reliability of the chip are optimized.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a manufacturing method of a trench step gate IGBT chip.
Background
An Insulated Gate Bipolar Transistor (IGBT) is a composite fully-controlled voltage-driven power semiconductor device composed of a bipolar transistor (BJT) and an insulated gate field effect transistor (MOSFET), and is widely applied to the fields of rail transit, a smart grid, industrial frequency conversion, new energy development and the like due to the characteristics of low on-state voltage, high current density, high input impedance, high response speed and the like.
In the existing trench gate IGBT chip technology, the channel is converted from the transverse direction to the longitudinal direction, so that the JFET effect in a planar gate channel is effectively eliminated, the channel density is not limited by the surface area of the chip any more, the cell density is improved, the current density of the chip is greatly improved, and the planar gate technology is gradually replaced in the field of medium-low voltage application. In order to further improve the power density of the trench gate IGBT chip, IGBT chip manufacturers push out a fine trench design, and through an advanced photolithography technique and a process, the trench width is reduced, and the trench pitch is reduced, so that the MOS channel density is increased, and the chip current density is improved.
However, for medium-high voltage devices, too high channel density may result in too high power density per unit area of the chip and too high heat loss, thereby affecting normal use of the IGBT chip. Meanwhile, the existing IGBT chip design needs to consider the voltage withstanding capability of the bottom of the groove, so that a thicker grid oxide layer is required, and the current capability of the chip is limited to a certain extent.
Therefore, for a medium-high voltage IGBT chip, a new design is needed to improve the current density of the IGBT chip without using a fine trench.
Disclosure of Invention
In order to solve the technical problem, the invention provides a manufacturing method of a trench step gate IGBT chip, which comprises the following steps:
forming a first oxide layer on the upper surface of the wafer substrate;
injecting N-type impurities into the wafer substrate, and diffusing the N-type impurities into a first junction depth to form an N well;
injecting P-type impurities into the N well, and diffusing the P-type impurities to a second junction depth to form a P well;
etching a first preset position on the first oxidation layer, the P well and the N well which correspond to the lower part of the first preset position, and the wafer substrate which corresponds to the lower part of the N well to form a groove;
removing the residual first oxidation layer, and forming a second oxidation layer with a first thickness on the upper surface of the P well and the inner surface of the groove;
etching the upper surface of the P well and the second oxide layer on the inner surface of the upper part of the preset groove in the groove, and forming a third oxide layer with a second thickness at the corresponding position;
and filling polysilicon in all the grooves to form a grid.
Preferably, the first junction depth is greater than the second junction depth.
Preferably, the first thickness is greater than the second thickness.
Preferably, the upper portion of the predetermined trench includes at least a portion of the predetermined trench corresponding to the P-well.
Preferably, the method further comprises the following steps:
etching a second preset position of the third oxidation layer to expose a source electrode injection window surrounding a groove opening of a preset groove in the preset groove; injecting N-type impurities into the source electrode injection window, and forming an N + region with a third junction depth by a rapid thermal annealing technology;
forming a fourth oxide layer on all the grooves, the exposed third oxide layer and the source electrode injection window in a deposition mode;
etching a third preset position on the fourth oxide layer and the N + region corresponding to the position below the third preset position to expose the P well at the corresponding position;
and injecting a P-type impurity into the exposed P well and forming a P + region by a rapid thermal annealing technology, wherein one end of the P + region is in contact connection with the N + region.
Preferably, the P-type impurity concentration in the P-well is less than the P-type impurity concentration in the P + region, and the N-type impurity concentration in the N-well is less than the N-type impurity concentration in the N + region.
Preferably, the second junction depth is greater than the third junction depth.
Preferably, after the P + region is formed, the method further includes the steps of:
and depositing a metal layer on the P + region and the fourth oxide layer to form a source electrode.
Preferably, the second oxide layer, the third oxide layer and the fourth oxide layer are all silicon dioxide.
Preferably, the method further comprises forming a back structure on the lower surface of the wafer substrate, wherein the back structure is a punch-through type, a non-punch-through type or a soft punch-through type.
Compared with the prior art, one or more embodiments in the above scheme can have the following advantages or beneficial effects:
by applying the manufacturing method of the trench step gate IGBT chip provided by the embodiment of the invention, in the trench gate chip, the gate oxide layer structure with the step morphology is realized through the same integration process, so that the trench gate adopts the thin gate oxide layer in the MOS channel region (namely the upper part of the trench gate) to fully exert the current processing capacity of the MOS channel, the current density of the chip is improved, the conduction consumption is reduced, and the control capacity of the gate to a switch is enhanced; meanwhile, the thickness of a gate oxide layer at the lower part of the trench gate is increased so as to enhance the voltage resistance of the trench and reduce the output capacitance and the switching loss; the current density of the IGBT chip is improved, and meanwhile, the electrical performance and reliability of the chip are optimized.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
fig. 1 is a flowchart of a method for manufacturing a trench step gate IGBT chip according to an embodiment of the invention;
fig. 2 is a schematic structural diagram of a manufacturing method and a manufacturing process of a trench step gate IGBT chip according to an embodiment of the invention;
fig. 3 is a schematic structural diagram of an IGBT chip manufactured by the method for manufacturing a trench step gate IGBT chip according to the second embodiment of the present invention;
fig. 4 is a schematic structural diagram of an IGBT chip manufactured by the method for manufacturing a trench step gate IGBT chip in the third embodiment of the present invention;
fig. 5 is a schematic structural diagram of an IGBT chip manufactured by the method for manufacturing a trench step gate IGBT chip in the third embodiment of the present invention.
Detailed Description
The following detailed description of the embodiments of the present invention will be provided with reference to the drawings and examples, so that how to apply the technical means to solve the technical problems and achieve the technical effects can be fully understood and implemented. It should be noted that, as long as there is no conflict, the embodiments and the features of the embodiments of the present invention may be combined with each other, and the technical solutions formed are within the scope of the present invention.
Example one
In order to solve the technical problems in the prior art, the embodiment of the invention provides a manufacturing method of a trench step gate IGBT chip.
Fig. 1 is a flowchart of a method for manufacturing a trench step gate IGBT chip according to an embodiment of the invention; fig. 2 is a schematic structural diagram of a manufacturing method and a manufacturing process of a trench step gate IGBT chip according to an embodiment of the present invention.
Referring to fig. 1 and 2, the method for manufacturing the IGBT chip with the trench step gate of the present embodiment includes the following steps.
In step S101, a first oxide layer 1 is formed on a wafer substrate 2.
Specifically, the wafer substrate 2 may be a float-zone silicon wafer, the first oxidation layer 1 may be silicon dioxide, a layer of uniform silicon dioxide is formed on the float-zone silicon wafer in a deposition manner or directly formed on the upper surface of the float-zone silicon wafer in a thermal oxidation manner, and the thickness of the silicon dioxide is within the range of the thickness of the silicon dioxide
In the meantime.
It should be noted that in other embodiments of the present invention, the first oxide layer 1 may be formed on the wafer substrate 2 in other reasonable manners, and the present invention is not limited to the above method.
Step S102, an N-type impurity is implanted into the wafer substrate 2 and diffused to a first junction depth to form an N-well 3.
Specifically, an N-type impurity is implanted into the upper surface of the wafer substrate 2 and diffused to a first junction depth to form the N-well 3. preferably, the N-type impurity is phosphorus, and the dose range of the implanted phosphorus is 5 × 1013cm-2To 5 × 1014cm-2The first junction depth is 2-4 μm.
It should be noted that the diffusion process of all impurities in this application includes not only longitudinal diffusion but also lateral diffusion.
In step S103, P-type impurities are implanted into the N-well 3 and diffused to a second junction depth to form the P-well 4.
Specifically, P-type impurity is implanted into the upper surface of the N-well 3 and diffused to a second junction depth of the wafer substrate to form the P-well 4, wherein the second junction depth of the P-type impurity diffusion is smaller than the first junction depth of the N-type impurity diffusion, preferably, the P-type impurity is boron, and the dosage range of the implanted boron is 1 × 1014cm-2To 5 × 1014cm-2And the second junction depth is 1.5-2.5 μm.
Note that the dose of P-type impurities in the conventional IGBT chip fabrication method is generally 7 × 1013cm-2To 1 × 1014cm-2Compared with the prior art, the dosage of the P-type impurities is adaptively increased, so that the density of the P-type impurities in the formed P-well is higher than that of the existing chip, the starting voltage of the P-well and the existing chip is kept at the same level, and meanwhile, the resistance of a hole channel is reduced by the P-well due to the higher density of the P-type impurities, and the anti-latching capacity of the device is enhanced.
Meanwhile, it should be noted that, since the P-well 4 is formed by diffusion on the basis of the N-well 3, the portion where the original N-well 3 and the P-well 4 are overlapped is the P-well 4; meanwhile, when the P-type impurities forming the P-well 4 are diffused, the N-type impurities in the N-well 3 are diffused again, so that the junction depth of the finally formed N-well 3 is larger than the first junction depth, and the diffused N-well 3 is always below the P-well 4 no matter how the diffused N-well 3 is, because the second junction depth of the P-well 4 is smaller than the first junction depth of the N-well 3.
Step S104, etching the first preset position on the first oxide layer 1, the P-well 4 and the N-well 3 corresponding to the lower part of the first preset position, and the wafer substrate below the N-well 3 to form the trench 5.
Specifically, a position on the first oxide layer 1 corresponding to a position on the wafer substrate 2 where the trench gate is to be formed is set as a first preset position, the first preset position on the first oxide layer 1 is etched, and the P-well 4 corresponding to the lower side of the first preset position is exposed, that is, a trench window is formed on the first oxide layer 1. And further etching the P well 4 and the N well 3 corresponding to the groove window to expose the wafer substrate below the N well corresponding to the groove window, and then performing incomplete etching on the wafer substrate to form a groove. Preferably, the trench depth is between 3-7 μm and the trench width of the trench 3 is between 1.0-2.2 μm.
It should be noted that the first preset position includes not only a specific position, but also a plurality of trenches 5 are formed by etching a plurality of positions on the wafer substrate 2 in the step of forming the trenches 5 because the IGBT chip includes a plurality of cells on the wafer substrate 2, and each cell of the IGBT chip formed in this embodiment has a trench gate, so that the first preset position includes positions corresponding to all positions on the wafer substrate where trenches are to be formed. Similarly, the subsequent second preset position and the third preset position do not represent a specific position.
Step S105, removing the remaining first oxide layer 1, and forming a second oxide layer 6 with a first thickness on the upper surface of the P-well and all the inner surfaces of the trench.
Specifically, the first oxide layer 1 remaining on the upper surface of the P-well 4 is removed by etching, and simultaneously, a second oxide layer 6 with a first thickness is formed on the upper surface of the P-well 4 and the inner surfaces of all the trenches 5 formed, wherein the thickness of the second oxide layer 6 is greater than that of the first oxide layer 6
In the meantime. Furthermore, the second oxide layer 6 on the upper surface of the P well 4 and the inner surface of the trench 5 can be formed by thermal oxidationAnd (4) obtaining. Preferably, the second oxide layer 6 material is also silicon dioxide.
Note that, after the P-type impurity is implanted into the N-well 3 in step S103, the P-well may not be formed by diffusion, and the P-type impurity may be simultaneously diffused to form the P-well 4 having the second junction depth when the second oxide layer is formed by thermal oxidation in this step.
Step S106, etching away the second oxide layer 6 on the upper surface of the P-well 4 and the inner surface of the upper portion of the predetermined trench in the trench 5, and forming a third oxide layer 7 with a second thickness at the corresponding position.
The trench gate includes a real gate and a dummy gate, and in this embodiment, one cell includes three trench gates, the trench gate in the middle is set as a real gate, and the trench gates on the two sides are set as dummy gates. Specifically, the trench located in the middle of the cell is set as a preset trench, that is, the trench to be formed into a solid gate is set as a preset trench. And etching the second oxide layer 6 on the upper surface of the P well 4 and the inner surface of the upper part of the preset groove, and forming a third oxide layer 7 with a second thickness at the position where the second oxide layer 6 is etched. Wherein the first thickness is different from the second thickness, that is, the thickness of the second oxide layer is different from the thickness of the third oxide layer; in an actual implementation process, in order to avoid further diffusion of the P well 4 in subsequent steps, and to make the final depth of the P well 4 greater than the depth of the upper portion of the preset trench, thereby affecting functions such as threshold voltage, current density and the like when the IGBT chip works, the depth of the upper portion of the preset trench is generally configured such that the P well 4 always corresponds to only the upper portion of the preset trench; and meanwhile, in order to avoid the N-well impurity from diffusing beyond the lower end of the groove in other forming steps, the first deep junction depth of the N-well is set to be the diffusion depth of the N-well impurity which does not exceed the lower end of the groove all the time.
Preferably, when the third oxide layer is formed, the third oxide layer may be formed by oxidation, and the thickness of the second oxide layer is increased when the third oxide layer is formed.
It should be noted that, in order to improve the current handling capability of the MOS channel, increase the current density of the chip and reduce the current consumption, a third step is requiredThe thickness of the oxide layer 7 is thinner than that of the existing trench gate oxide layer, and meanwhile, in order to enhance the pressure resistance of the trench, the thickness of the gate oxide layer at the lower part of the trench gate, namely the thickness of the second oxide layer 6, is thicker than that of the existing trench gate oxide layer; the thickness of the conventional trench oxide gate is generally
That is, the thickness of the third oxide layer 7 is set to be thinner than the thickness of the second oxide layer 6. Preferably, the third oxide layer has a thickness of
In the meantime.
In step S107, polysilicon 8 is filled in all trenches 5 to form gates.
Specifically, polysilicon 8 is filled in all the formed trenches 5, and a plurality of real gates and a plurality of dummy gates are formed. During operation, the formed virtual grid is suspended or connected to the emitter.
Step S108, etching a second preset position of the third oxidation layer 7 to expose a source injection window surrounding a groove opening of a preset groove in the preset groove; an N-type impurity is implanted into the source implantation window and an N + region 9 of a third junction depth is formed by a rapid thermal annealing technique.
Specifically, a groove needing to form a solid gate in a cell is set as a preset groove, the position of a second oxidation layer corresponding to the position needing to form a source electrode injection window is set as a second preset position, the source electrode window surrounds a groove opening of the preset groove, the second preset position of a third oxidation layer 7 is etched to form a source electrode injection window, the source electrode injection window is used for injecting N-type impurities, the N-type impurities form an N + region 9 through a rapid thermal annealing technology, preferably, the N-type impurities are phosphorus or arsenic, and the injection metering range is 8 × 1014cm-2To 8 × 1015cm-2The third junction depth may be 0.2 to 1.0 μm. The annealing temperature is 900-1000 ℃, and the annealing time is 30-120 s. The N-type impurity concentration of the N + region 9 is greater than that of the N-type impurity concentration of the N well 3, and the third junction depth is smaller than the second junction depth.
Since the N + region 9 is formed on the basis of the P well 4 as above, the portion where the original P well 4 and the newly formed N + region 9 overlap is the N + region 9.
In step S109, a fourth oxide layer is formed on the trench openings of all trenches, the exposed third oxide layer, and the source implantation window by deposition.
Specifically, a fourth oxide layer is formed on the groove openings of all the grooves and the source injection window in a deposition mode. The thickness of the fourth oxide layer is 0.5-1.0 μm.
Step S110, etching the third preset position on the fourth oxide layer and the N + region 9 corresponding to the lower side of the third preset position to expose the P-well 4 at the corresponding position.
Specifically, the part of the fourth oxide layer corresponding to the position where the P + region 10 needs to be formed is set as a third preset position, and the third preset position on the fourth oxide layer and the N + region 9 corresponding to the lower side of the third preset position are etched to expose the P well 4 at the corresponding position. The portion of the P-well 4 adjacent to the etched N + region 9 is also etched.
It should be noted that the P + region 10 not only corresponds to the N + region 9, but also corresponds to the P well 4 adjacent to the N + region 9, and portions of the P + region 10 corresponding to the N + region 9 and the P well 4, above the corresponding portions of the fourth oxide layer and the P + region 10, are set as a third predetermined position, and the P well and the N + region 9 corresponding to the lower portions of the two regions are etched.
Step S111, injecting P-type impurities into the exposed P well 4 and forming a P + region 10 by a rapid thermal annealing technology, wherein one end of the P + region 10 is in contact connection with the N + region 9.
Specifically, a P-type impurity is implanted into the exposed P-well 4 and a P + region 10 is formed by a rapid thermal annealing technique, the P-type impurity is diffused to one end to contact the N + region 9, preferably, the P-type impurity is still boron, and the dose range of boron implantation is 1 × 1015cm-2To 5 × 1015cm-2. Wherein, the concentration of the P-type impurity in the P well 4 is less than that of the P + region 10.
Note that, in step S108, after the N-type impurity is implanted into the source implantation window, the N + region 9 may not be formed by the rapid thermal annealing technique, and after the P-type impurity is implanted into the exposed P well 4 in this step, the N + region 9 and the P + region 10 may be simultaneously formed by the rapid thermal annealing technique.
It should be further noted that when the impurity is no longer diffused, the formed N well 3, P well 4, N + region 9, and P + region 10 are the N well 3, P well 4, N + region 9, and P + region 10 of the final IGBT chip.
In step S112, a metal layer 11 is deposited on the P + region 10 and the fourth oxide layer to form a source.
Specifically, a metal layer 11 is deposited on all the P + regions 10 and the fourth oxide layer to form the source electrode. Preferably, the metal layer 11 is made of aluminum. The thickness range of the deposited aluminum is 3-7 μm.
It should be noted that, the method for manufacturing the IGBT chip with the composite gate according to this embodiment further includes forming a back structure on the lower surface of the wafer substrate, where the back structure of the chip may be a punch-through type, a non-punch-through type, or a soft punch-through type, and a back process of the chip is consistent with a process of an existing chip, and therefore is omitted.
By applying the manufacturing method of the trench step gate IGBT chip provided by the embodiment of the invention, in the trench gate chip, the gate oxide layer structure with the step morphology is realized through the same integration process, so that the trench gate adopts the thin gate oxide layer in the MOS channel region (namely the upper part of the trench gate) to fully exert the current processing capacity of the MOS channel, the current density of the chip is improved, the conduction consumption is reduced, and the control capacity of the gate to a switch is enhanced; meanwhile, the thickness of a gate oxide layer at the lower part of the trench gate is increased so as to enhance the voltage resistance of the trench and reduce the output capacitance and the switching loss; the current density of the IGBT chip is improved, and meanwhile, the electrical performance and reliability of the chip are optimized.
Example two
In order to solve the technical problems in the prior art, the embodiment of the invention also provides another manufacturing method of the trench step gate IGBT chip.
Fig. 3 shows a schematic structural diagram of an IGBT chip manufactured by the method for manufacturing a trench step gate IGBT chip in the second embodiment of the invention.
This embodiment is based on the first embodiment, and the step S106 is modified appropriately.
In this embodiment, step S106 is specifically:
step S106, etching the upper surface of the P well and the second oxide layer 6 on the inner surface of the upper part of the preset trench in all the trenches, and forming a third oxide layer 7 with a second thickness at the corresponding position.
The trench gate includes a real gate and a dummy gate, and in this embodiment, three trench gates are arranged in one cell, where the trench gate in the middle is the real gate, and the trench gates on both sides are arranged as the dummy gate. Specifically, three trenches in the cell are set as the preset trenches, and all trenches to be formed are set as the preset trenches. And etching the second oxide layer 6 on the upper surface of the P well 4 and the inner surface of the upper part of the preset groove, and forming a third oxide layer 7 with a second thickness at the position where the second oxide layer 6 is etched. Therefore, the gate oxide layers of the real gate and the virtual gate in the embodiment have step shapes.
Other steps are the same as those in the first embodiment, and are not described herein.
By applying the manufacturing method of the trench step gate IGBT chip provided by the embodiment of the invention, in the trench gate chip, the gate oxide layer structure with the step morphology is realized through the same integration process, so that the trench gate adopts the thin gate oxide layer in the MOS channel region (namely the upper part of the trench gate) to fully exert the current processing capacity of the MOS channel, the current density of the chip is improved, the conduction consumption is reduced, and the control capacity of the gate to a switch is enhanced; meanwhile, the thickness of a gate oxide layer at the lower part of the trench gate is increased so as to enhance the voltage resistance of the trench and reduce the output capacitance and the switching loss; the current density of the IGBT chip is improved, and meanwhile, the electrical performance and reliability of the chip are optimized.
EXAMPLE III
In order to solve the technical problems in the prior art, the embodiment of the invention also provides another manufacturing method of the trench step gate IGBT chip.
Fig. 4 shows a schematic structural diagram of an IGBT chip manufactured by the method for manufacturing a trench step gate IGBT chip in the third embodiment of the invention.
The present embodiment also makes appropriate modifications to step S106 based on the first embodiment.
Specifically, step S106 in this embodiment is:
step S106, etching away the second oxide layer 6 on the upper surface of the P-well 4 and the inner surface of the upper portion of the predetermined trench in the trench 5, and forming a third oxide layer 7 with a second thickness at the corresponding position.
In the embodiment, three trench gates are arranged in one cell, and all three trenches in the cell are arranged as solid gates. Therefore, three trenches in the cell are set as the preset trenches, and all trenches to be formed are set as the preset trenches. And etching the second oxide layer 6 on the upper surface of the P well 4 and the inner surface of the upper part of the preset groove, and forming a third oxide layer 7 with a second thickness at the position where the second oxide layer 6 is etched. So that all trench gates in this embodiment have a step profile.
Other steps are the same as those in the first embodiment, and are not described herein.
By applying the manufacturing method of the trench step gate IGBT chip provided by the embodiment of the invention, in the trench gate chip, the gate oxide layer structure with the step morphology is realized through the same integration process, so that the trench gate adopts the thin gate oxide layer in the MOS channel region (namely the upper part of the trench gate) to fully exert the current processing capacity of the MOS channel, the current density of the chip is improved, the conduction consumption is reduced, and the control capacity of the gate to a switch is enhanced; meanwhile, the thickness of a gate oxide layer at the lower part of the trench gate is increased so as to enhance the voltage resistance of the trench and reduce the output capacitance and the switching loss; the current density of the IGBT chip is improved, and meanwhile, the electrical performance and reliability of the chip are optimized.
Example four
In order to solve the technical problems in the prior art, the embodiment of the invention also provides another manufacturing method of the trench step gate IGBT chip.
Fig. 5 shows a schematic structural diagram of an IGBT chip manufactured by the method for manufacturing a trench step gate IGBT chip in the third embodiment of the invention.
The present embodiment also makes appropriate modifications to step S106 based on the first embodiment.
Specifically, step S106 in this embodiment is:
step S106, etching away the second oxide layer 6 on the upper surface of the P-well 4 and the inner surface of the upper portion of the predetermined trench in the trench 5, and forming a third oxide layer 7 with a second thickness at the corresponding position.
The trench gate includes a real gate and a dummy gate, and in this embodiment, five trench gates are arranged in one cell, where the trench gate in the middle is the real gate, and the trench gates on both sides are both configured as the dummy gate. Specifically, a trench set to be located in the middle of the cell is set as a preset trench, that is, a trench to be formed into a solid gate is set as a preset trench. And etching the second oxide layer 6 on the upper surface of the P well 4 and the inner surface of the upper part of the preset groove, and forming a third oxide layer 7 with a second thickness at the position where the second oxide layer 6 is etched. In this embodiment, the number of dummy gates in the cell is increased.
Other steps are the same as those in the first embodiment, and are not described herein.
By applying the manufacturing method of the trench step gate IGBT chip provided by the embodiment of the invention, in the trench gate chip, the gate oxide layer structure with the step morphology is realized through the same integration process, so that the trench gate adopts the thin gate oxide layer in the MOS channel region (namely the upper part of the trench gate) to fully exert the current processing capacity of the MOS channel, the current density of the chip is improved, the conduction consumption is reduced, and the control capacity of the gate to a switch is enhanced; meanwhile, the thickness of a gate oxide layer at the lower part of the trench gate is increased so as to enhance the voltage resistance of the trench and reduce the output capacitance and the switching loss; the current density of the IGBT chip is improved, and meanwhile, the electrical performance and reliability of the chip are optimized.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (9)
1. A manufacturing method of a trench step gate IGBT chip is characterized by comprising the following steps:
forming a first oxide layer on the upper surface of the wafer substrate;
injecting N-type impurities into the wafer substrate, and diffusing the N-type impurities into a first junction depth to form an N well;
injecting P-type impurities into the N well, and diffusing the P-type impurities to a second junction depth to form a P well;
etching a first preset position on the first oxidation layer, the P well and the N well which correspond to the lower part of the first preset position, and the wafer substrate below the N well to form a groove;
removing the residual first oxidation layer, and forming a second oxidation layer with a first thickness on the upper surface of the P well and the inner surface of the groove;
etching the upper surface of the P well and the second oxide layer on the inner surface of the upper part of the preset groove in the groove, and forming a third oxide layer with a second thickness at the corresponding position;
filling polycrystalline silicon in all the grooves to form a grid;
further comprising:
etching a second preset position of the third oxidation layer to expose a source electrode injection window surrounding a groove opening of a preset groove in the preset groove; injecting N-type impurities into the source electrode injection window, and forming an N + region with a third junction depth by a rapid thermal annealing technology;
forming a fourth oxide layer on all the grooves, the exposed third oxide layer and the source electrode injection window in a deposition mode;
etching a third preset position on the fourth oxide layer and the N + region corresponding to the position below the third preset position to expose the P well at the corresponding position;
and injecting a P-type impurity into the exposed P well and forming a P + region by a rapid thermal annealing technology, wherein one end of the P + region is in contact connection with the N + region.
2. The method of claim 1, wherein the first junction depth is greater than the second junction depth.
3. The method of manufacturing of claim 1, wherein the first thickness is greater than the second thickness.
4. The method of claim 1, wherein the upper portion of the pre-trench comprises at least a portion of the pre-trench corresponding to the P-well.
5. The method of claim 1, wherein a P-type impurity concentration in the P-well is less than a P-type impurity concentration in the P + region, and an N-type impurity concentration in the N-well is less than an N-type impurity concentration in the N + region.
6. The method of claim 1, wherein said second junction depth is greater than said third junction depth.
7. The method of claim 1, further comprising, after forming the P + region, the steps of:
and depositing a metal layer on the P + region and the fourth oxide layer to form a source electrode.
8. The method according to claim 1, wherein the second oxide layer, the third oxide layer and the fourth oxide layer are all silicon dioxide.
9. The method of any one of claims 1-8, further comprising forming a backside structure on a lower surface of the wafer substrate, the backside structure being a punch-through, a non-punch-through, or a soft punch-through.
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