CN102270663A - Planar power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with super junction structure and manufacturing method of planar power MOSFET device - Google Patents
Planar power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with super junction structure and manufacturing method of planar power MOSFET device Download PDFInfo
- Publication number
- CN102270663A CN102270663A CN 201110210968 CN201110210968A CN102270663A CN 102270663 A CN102270663 A CN 102270663A CN 201110210968 CN201110210968 CN 201110210968 CN 201110210968 A CN201110210968 A CN 201110210968A CN 102270663 A CN102270663 A CN 102270663A
- Authority
- CN
- China
- Prior art keywords
- layer
- district
- gate oxide
- conduction type
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
The invention relates to a planar power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with a super junction structure and a manufacturing method of the planar power MOSFET device. The super junction structure is formed in a semiconductor substrate, second conduction type layers are arranged in a unit cell, and adjacent second conduction type layers are isolated by virtue of a first conduction type drift layer, each second conduction type layer is internally provided with a first conduction type injection region; a second gate oxide layer region is arranged between the adjacent second conduction type layers, the width of the second gate oxide layer region is not more than a horizontal distance of the adjacent second conduction type layers; first gate oxide layers are arranged at two sides of the second gate oxide layer region, the thickness of the second gate oxide layer region is less than that of the first gate oxide layer region; the first gate oxide layer region is partially overlapped and contacted with the second conduction type layer and the injection region part of the first conduction type injection region; and the horizontal distance of the first conduction type injection regions in the second conduction type layers, coated by the second conduction type layers, is less than the width of the first gate oxide layer region. The planar power MOSFET device provided by the invention has low miller capacitor, high switching speed, low switching loss, simple process and low cost.
Description
Technical field
The present invention relates to a kind of planar power MOSFET device and manufacture method thereof, especially a kind of planar power MOSFET device and manufacture method thereof with super-junction structure belongs to the semi-conductive technical field of super-junction structure.
Background technology
The MOSFET device is a kind of majority carrier device, and it has the not available input impedance height of bipolar device, fast characteristics and the advantage of switching speed.Because MOSFET does not have the problem of minority carrier storage, therefore, its switching delay characteristic mainly is because the charging and the discharge of parasitic capacitance.
Generally speaking, the parasitic capacitance of assessment power MOSFET device generally includes: input capacitance (Ciss), output capacitance (Coss), feedback capacity (Crss).Input capacitance is grid source parasitic capacitance (Cgs) and grid leak parasitic capacitance (Cgd) sum, i.e. Ciss=Cgs+Cgd; Output capacitance is drain-source parasitic capacitance (Cds) and grid leak parasitic capacitance sum, i.e. Coss=Cds+Cgd; Feedback capacity is also referred to as miller capacitance, Crss=Cgd.Power MOSFET is the voltage driven type device, its gate drive voltage can be understood as the process that its endobiosis electric capacity charges by the process that 0V rises to given voltage (as 12V), parasitic capacitance is big more, its required charging charge Qg is many more, it is also just slow more to open speed accordingly, simultaneously, also can bring turn-on consumption to become big adverse effect; In like manner, turn-off speed during shutoff and turn-off power loss also are that discharge process by parasitic capacitance is determined.In whole switching process, miller capacitance Crss and pairing grid leak electric charge (Qgd) thereof will play leading role, therefore, if can reduce Cgd, just can improve switching speed, reduce switching loss.
With planar power MOSFET is example, the parasitic capacitance of its single cellular such as accompanying drawing 15, wherein Cox is the gate oxide parasitic capacitance, Cgd1 is the parasitic capacitance of the depletion layer that produces in the drift layer under the grid, by among the figure as can be known, Cgd is that Cox and Cgd1 are in series, i.e. 1/Cgd=1/Cox+1/Cgd1.Cgd is the function of drain-source voltage Vds, when applying a higher Vds on the device, and does not have gate source voltage Vgs on the device this moment, and the depletion layer that is positioned at so gate oxide under makes that Cgd1 is very little, and the size of Cgd is mainly determined by Cgd1 at this moment; Apply a Vgs on device, and the value of Vgs meets or exceeds the threshold voltage vt h of device, device begins conducting, and this moment, Vds can drop to 0V, and the depletion layer gate oxide under disappears, and Cgd1 increases greatly, and the size of Cgd is mainly determined by Cox at this moment.Cox is determined by gate oxide thickness that mainly gate oxide is thick more, and Cox is more little, and the Cgd when break-over of device is also more little so.Yet, if the increase gate oxide thickness, the Vth(Vth that then can directly have influence on device increases) and mutual conductance Gfs(Gfs reduce), especially for some linear circuits, mutual conductance reduces to reduce the control ability of grid voltage to drain-source current greatly, reduces the performance of device.
Summary of the invention
The objective of the invention is to overcome the deficiencies in the prior art, a kind of planar power MOSFET device and manufacture method thereof with super-junction structure is provided, its miller capacitance is low, switching speed is fast, switching loss is low, technology simply reaches with low cost.
According to technical scheme provided by the invention, described planar power MOSFET device with super-junction structure, on the top plan view of described MOSFET device, comprise the cellular region and the terminal protection district that are positioned at semiconductor substrate, described terminal protection district is positioned at the outer ring of cellular region, and the terminal protection district is around surrounding cellular region; Comprise in the described cellular region that several rules is arranged and the cellular of connection parallel with one another; On the cross section of described MOSFET device, semiconductor substrate has corresponding first interarea and second interarea, comprises the first conduction type drift layer between described first interarea and second interarea; In the first conduction type drift layer of semiconductor substrate, comprise some to first post with first conduction type and second post with second conduction type; Described first post and second post extend in the first conduction type drift layer of semiconductor substrate along the current flowing direction; On the direction of vertical current circulation, many PN post alternately is connected setting by what described first post and second post constituted, in semiconductor substrate, form super-junction structure; Its innovation is:
On the cross section of described MOSFET device, comprise second conductive type layer that is positioned at the first conduction type drift layer in the described cellular region, described second conductive type layer is connected with second conduction type, second post of described second conductive type layer below, the second adjacent conduction type interlayer is isolated by the first conduction type drift layer, is provided with the first conduction type injection region in second conductive type layer; First corresponding directly over the first conduction type drift layer between described adjacent second conductive type layer interarea is provided with the second gate oxide district, and the width in the described second gate oxide district is not more than the horizontal range between adjacent second conductive type layer in the first conduction type drift layer; The both sides in the second gate oxide district are provided with first grid oxide layer district, and the thickness in the described second gate oxide district is greater than the thickness in first grid oxide layer district; The first conduction type injection region part in first grid oxide layer district and corresponding second conductive type layer and described second conductive type layer overlaps and contacts; On first interarea of semiconductor substrate, near the second gate oxide district, one side, second conductive type layer coats the width of the horizontal range of the first conduction type injection region in second conductive type layer less than first grid oxide layer district;
All be coated with conductive polycrystalline silicon in the described first grid oxide layer district and the second gate oxide district, described conductive polycrystalline silicon is provided with insulating medium layer, and described insulating medium layer is covered on the corresponding conductive polycrystalline silicon and coats corresponding first grid oxide layer district, second gate oxide district and the conductive polycrystalline silicon; On first interarea of semiconductor substrate, adjacent dielectric interlayer is provided with the source lead hole, described source lead is filled with source metal in the hole, isolate by insulating medium layer between described source metal and conductive polycrystalline silicon, and described source metal while and the first conduction type injection region and the second conductive type layer ohmic contact.
On the cross section of described MOSFET device, super-junction structure is present in cellular region and the terminal protection district; The right width and the degree of depth of PN post is all identical arbitrarily in the cellular region.
The material of described semiconductor substrate comprises silicon, and semiconductor substrate comprises the first conduction type drift layer and be positioned at first conductivity type substrate of described first conduction type drift layer below that the described first conduction type drift layer is in abutting connection with first conductivity type substrate; Corresponding first interarea that forms in the surface of the first conduction type drift layer, corresponding second interarea that forms in the surface of first conductivity type substrate.
A kind of manufacture method with planar power MOSFET device of super-junction structure, the manufacture method of described power MOSFET device comprises the steps:
A, provide the semiconductor substrate with two relative interareas, described semiconductor substrate to comprise first conductivity type substrate and be positioned at the first conduction type drift layer of described first conductivity type substrate top; Described two relative interareas comprise first interarea and second interarea;
B, on first interarea of above-mentioned semiconductor substrate the deposit hard mask layer;
C, optionally shelter and the etching hard mask layer, form the hard mask open of a plurality of etching grooves,, utilize the anisotropic lithographic method in the first conduction type drift layer, to form a plurality of grooves by described hard mask open;
D, on first interarea of above-mentioned semiconductor substrate deposit second conductive type epitaxial layer, described second conductive type epitaxial layer is filled in the groove, and is covered on first interarea of semiconductor substrate;
E, second conductive type epitaxial layer that covers the first conduction type drift layer surface is polished and planarization, in the first conduction type drift layer, form second post with second conduction type;
F, the gate oxide of on first interarea of above-mentioned semiconductor substrate, growing, described gate oxide is covered in first interarea of semiconductor substrate;
G, utilize photoresist as masking layer, above-mentioned gate oxide is carried out photoetching and etching, obtaining the second gate oxide district and be positioned at the 3rd gate oxide district of both sides, the described second gate oxide district on first interarea of semiconductor substrate, the thickness in described the 3rd gate oxide district is less than the thickness in the second gate oxide district;
H, remove the photoresist on above-mentioned semiconductor substrate first interarea, and on first interarea of above-mentioned semiconductor substrate the deposit conductive polycrystalline silicon floor, described conductive polycrystalline silicon floor is covered on the 3rd gate oxide and second gate oxide;
I, optionally shelter and the above-mentioned conductive polycrystalline silicon floor of etching, and corresponding the 3rd gate oxide district, etching described conductive polycrystalline silicon floor below, to obtain the first grid oxide layer district and the second gate oxide district on first interarea of semiconductor substrate, the thickness in described first grid oxide layer district is consistent with the thickness in the 3rd gate oxide district; All cover conductive polycrystalline silicon in the first grid oxide layer district and the second gate oxide district;
J, with above-mentioned conductive polycrystalline silicon as injecting masking layer, the second conductive type impurity ion is injected in autoregistration on first interarea of semiconductor substrate, and in the first conduction type drift layer of semiconductor substrate, forming second conductive type layer that adjacent rule is arranged by elevated temperature heat process knot, the horizontal range between described adjacent second conductive type layer is not less than the width in the described second gate oxide district;
K, carry out the source region photoetching on first interarea of above-mentioned semiconductor substrate, and inject the first conductive type impurity ion, form the first conduction type injection region by elevated temperature heat process knot, the described first conduction type injection region is positioned at second conductive type layer;
L, on first interarea of above-mentioned semiconductor substrate the deposit insulating medium layer, described insulating medium layer is covered in first interarea of semiconductor substrate, and is covered on the conductive polycrystalline silicon;
M, on above-mentioned insulating medium layer, carry out hole photoetching and etching, obtain the source lead hole, described source lead hole is positioned at the adjacent conductive inter polysilicon, and the source lead hole extends on first interarea of semiconductor substrate from the surface of insulating medium layer;
N, on first interarea of above-mentioned semiconductor substrate deposited metal, described metal level is filled in the source lead hole and is covered on the insulating medium layer, by metal level photoetching and etching being obtained source metal, the described source metal and the first conduction type injection region and the second conductive type layer ohmic contact.
Described insulating medium layer is silex glass (USG), boron-phosphorosilicate glass (BPSG) or phosphorosilicate glass (PSG).
Described metal level is aluminium, copper or tungsten.
Described hard mask layer is that LPTEOS, thermal oxidation silicon dioxide add chemical vapour deposition (CVD) silicon dioxide or thermal silicon dioxide adds silicon nitride.
The material of described semiconductor substrate comprises silicon.
The thickness in the described second gate oxide district is 2000 à ~ 5000 à.The thickness in described first grid oxide layer district is 500 à ~ 1500 à.
Described " first conduction type " and " second conduction type " are among both, and for N type MOSFET device, first conduction type refers to the N type, and second conduction type is the P type; For P type MOSFET device, first conduction type is just in time opposite with the type and the N type semiconductor device of the second conduction type indication.
Advantage of the present invention:
1, in cellular region, adopt the gate oxide of two kinds of thickness, first grid oxide layer district is with second conductive type layer of its below, the channel region that the first conduction type injection region has formed described MOSFET device, because the thickness in first grid oxide layer district is thinner, therefore, grid is compared with common MOSFET for the control of drain-source current significant change, and performances such as the mutual conductance of device, threshold voltage obviously do not change.
2, in cellular region, influence can not brought to mutual conductance, threshold voltage owing to do not form the raceway groove of device in below, the second gate oxide district therefore; Simultaneously, the thicker parasitic grid oxygen capacitor C ox that can reduce device greatly of the thickness in the second gate oxide district, thus reduce miller capacitance, make the switching speed of device accelerate, switching loss reduces.
3, structural manufacturing process flow process of the present invention is simple, the thickness in first grid oxide layer district and the thickness in the second gate oxide district can be provided with according to intended target is convenient, simultaneously, the width in the second gate oxide district also can be provided with by the design size of corresponding level is convenient, is convenient to extend to big production.
4, structure of the present invention is applied widely, and is all feasible for the power MOSFET that uses planar technique to make, as the common DMOS of plane, and the super knot of plane (Super Junction) MOSFET, the IGBT of plane.
Description of drawings
Fig. 1 is a structural representation of the present invention.
Fig. 2 ~ Figure 14 is the concrete implementing process step of a power MOSFET device of the present invention cutaway view, wherein:
Fig. 2 is the cutaway view of semiconductor substrate.
Fig. 3 is the cutaway view after the hard mask open of formation.
Fig. 4 is the cutaway view behind the formation groove.
Fig. 5 is the cutaway view behind deposit second conductive type epitaxial layer.
Fig. 6 is the cutaway view behind grinding second conductive type epitaxial layer.
Fig. 7 is the cutaway view behind the growth gate oxide.
Fig. 8 is for forming the cutaway view in the second gate oxide district.
Fig. 9 is the cutaway view behind the deposit conductive polycrystalline silicon floor.
Figure 10 is the cutaway view behind the formation first grid oxide layer district.
Figure 11 is the cutaway view after formation second conductive type layer.
Figure 12 is the cutaway view behind the formation first conduction type injection region.
Figure 13 is the cutaway view behind the formation insulating medium layer.
Figure 14 is the cutaway view behind the formation source metal.
Figure 15 is the cellular parasitic capacitance schematic diagram of existing plane double diffusion power MOSFET device.
Embodiment
The invention will be further described below in conjunction with concrete drawings and Examples.
As Fig. 1 ~ shown in Figure 14: with N type power MOSFET device is example, the present invention includes N type drift layer 1, N+ substrate 2, N post 3, P post 4, N+ source region 5, P well region 6, first grid oxide layer district 7, the second gate oxide district 8, conductive polycrystalline silicon 9, insulating medium layer 10, source metal 11, first interarea 12, second interarea 13, hard mask layer 14, hard mask layer opening 15, groove 16, P type epitaxial loayer 17, gate oxide 18, the 3rd gate oxide district 19 and conductive polycrystalline silicon material layer 20.
As Fig. 1 and shown in Figure 14: as described on the top plan view of power MOSFET device; comprise the cellular region that is positioned at the semiconductor substrate center and be positioned at the terminal protection district of described cellular region outer ring; described terminal protection district surrounds around cellular region, comprises in the described cellular region that several rules is arranged and the cellular of connection parallel with one another.On the cross section of described power MOSFET device, described semiconductor substrate comprises N type drift layer 1 and is positioned at the N+ substrate 2 of described N type drift layer 1 below, and described N+ substrate 2 is in abutting connection with N type drift layer 1, and the concentration of N+ substrate 2 is greater than the concentration of N type drift layer 1.Comprise in the described N type drift layer 1 that many promptly N post 3 forms first post to first post with N type conduction type and second post with P-type conduction type, P post 4 forms second post.Described N post 3 and P post 4 are arranged alternately in N type drift layer 1, form super-junction structure; Described N post 3 extends in the N of semiconductor substrate type drift layer 1 along the direction of current flowing with P post 4, and promptly P post 4 extends to the direction near N+ substrate 2 in N type drift layer 1; On the direction perpendicular to current flowing, N post 3 alternately is connected with P post 4 the formation super-junction structure is set, and described super-junction structure is arranged in device cellular region and the terminal protection district.
On described semiconductor device cross-section, it is right to be provided with many PN posts to alternately adjacency setting in the described N type drift layer 1, and every pair of PN post is to the formation that links to each other with a P post 4 by a N post 3.Described P post 4 extends along direction direction to N+ substrate 2 in N type drift layer 1 of current flowing, and the distance of extension is less than the thickness of N type drift layer 1; The right width and the degree of depth of PN post is all identical arbitrarily in the element area.N type drift layer 1 is being divided into the adjacent N post 3 of a plurality of and corresponding P post 4 by a plurality of P posts 4 on the direction of current flowing.Under P post 4, can also be provided with P type injection region, described P type injection region is surrounded by the P post 4 of its top and N type drift layer 1 on every side, the width of P type injection region and the width basically identical of P post 4, P type injection region corresponding to P-type conduction type dopant concentration greater than P post 4 corresponding P-type conduction type dopant concentration.
On the cross section of described power MOSFET device, separate P well region 6 is formed at the top of super-junction structure in the cellular region of described power MOSFET device, described adjacent P well region 6 is isolated by corresponding N post 3, P well region 6 is connected with the P post 4 of described P well region 6 belows, after described P well region 6 utilizes N post 3 to isolate, can guarantee the passage of current flowing in the MOSFET structure.In the top of P well region 6, be provided with separate N+ source region 5; N post that the N+ source region 5, P well region 6 of part be poor with the horizontal junction depth in N+ source region 5, isolate P well region 63 is covered by gate oxide.Described gate oxide comprises the first grid oxide layer district 7 and the second gate oxide district 8, the described second gate oxide district 8 be positioned at the N post 3 of isolating adjacent P well region 6 directly over, and the width in the second gate oxide district 8 is not more than the distance of 6 of adjacent P well regions.First grid oxide layer 7 is positioned at the both sides in the second gate oxide district 8, and the thickness in first grid oxide layer district 7 is less than the thickness in the second gate oxide district 8, thus the stair-stepping structure of shape.First grid oxide layer district 7 overlaps with N+ source region 5 parts in corresponding P well region 6 and the described P well region 6 and contacts.On first interarea 12 of semiconductor substrate, in the close second gate oxide district 8 one sides, P well region 6 coats the width of the horizontal range in the N+ source regions 5 in it less than first grid oxide layer district 7.
On the cross section of described power MOSFET device, be deposited with conductive polycrystalline silicon 9 in the first grid oxide layer district 7 and the second gate oxide district 8, the shape of described conductive polycrystalline silicon 9 is consistent with the shape in the first grid oxide layer district 7 and the second gate oxide district 9.Described conductive polycrystalline silicon 9 is provided with insulating medium layer 10, described insulating medium layer 10 is covered on the conductive polycrystalline silicon 9, and coat the described first grid oxide layer district 7 and the second gate oxide district 8, promptly first grid oxide layer district 7, the second gate oxide district 8 and conductive polycrystalline silicon 9 all are positioned at insulating medium layer 10.10 of described adjacent insulating medium layers are provided with the source lead hole, described source lead is filled with source metal 11 in the hole, described source metal 11 also is covered on the insulating medium layer 10,9 of described source metal 11 and conductive polycrystalline silicons pass through insulating medium layer 10 isolates, and source metal 11 while and P well region 6 and N+ source region 5 ohmic contact.
The power MOSFET device of said structure, realize by following processing step:
A, provide the semiconductor substrate with two relative interareas, described semiconductor substrate to comprise N+ substrate 2 and be positioned at the N type drift layer 1 of described N+ substrate 2 tops; Described two relative interareas comprise first interarea 12 and second interarea 13;
As shown in Figure 2: the surface of described N type drift layer 1 correspondence forms first interarea 12, and the surface of N+ substrate 2 correspondences forms second interarea 13; Described N+ substrate 2 is in abutting connection with N type drift layer 1; The material of semiconductor substrate comprises silicon;
B, on first interarea 12 of above-mentioned semiconductor substrate deposit hard mask layer 14;
C, optionally shelter and etching hard mask layer 14, form the hard mask open 15 of a plurality of etching grooves,, utilize the anisotropic lithographic method in N type drift layer 1, to form a plurality of grooves 16 by described hard mask open 15;
As shown in Figure 3 and Figure 4: described hard mask layer 14 can adopt LPTEOS(low-pressure chemical vapor deposition tetraethyl orthosilicate), thermal oxidation silicon dioxide adds chemical vapour deposition (CVD) silicon dioxide or thermal silicon dioxide adds silicon nitride, forms hard mask by photoetching and anisotropic etching thereafter; Described groove 16 extends distance to a declared goal downwards by N type drift layer 1 surface in N type drift layer 1, the degree of depth that groove 16 extends in N type drift layer 1 is less than the thickness of N type drift layer 1, and N type drift layer 1 is divided into a plurality of N posts 3, the degree of depth of described N post 3 is consistent with the degree of depth of groove 16;
D, on first interarea 12 of above-mentioned semiconductor substrate deposit P type epitaxial loayer 17, described P type epitaxial loayer 17 is filled in the groove 16, and is covered on first interarea 12 of semiconductor substrate;
As shown in Figure 5: need to remove the hard mask layer 14 on first interarea 12 before the deposit P type epitaxial loayer 17; After injecting P type epitaxial loayer 17 in the groove 15, P type epitaxial loayer 17 forms P post 4 in N type drift layer 1, thereby forms N post 3 and the P post 4 that is arranged alternately in N type drift layer 1, forms super-junction structure;
E, the N type epitaxial loayer 17 that covers N type drift layer 1 surface is polished and planarization, in N type drift layer 1, form P post 4 with P-type conduction type; As shown in Figure 6;
In certain embodiments, also can not remove this P type epitaxial loayer of part, promptly keep the P type epitaxial loayer of suitable thickness at device surface;
F, the gate oxide 18 of on first interarea 12 of above-mentioned semiconductor substrate, growing, described gate oxide 18 is covered in first interarea 12 of semiconductor substrate;
As shown in Figure 7: the thickness of described gate oxide 18 is consistent with the thickness in the second gate oxide district 8, and the thickness of gate oxide 18 is 2000 à ~ 5000 à;
G, utilize photoresist as masking layer, above-mentioned gate oxide 18 is carried out photoetching and etching, obtaining the second gate oxide district 8 and be positioned at the 3rd gate oxide district 19 of 8 both sides, the described second gate oxide district on first interarea 12 of semiconductor substrate, the thickness in described the 3rd gate oxide district 19 is less than the thickness in second gate oxide, 18 districts;
As shown in Figure 8: by photoresist during as masking layer, gate oxide 18 on can etched portions first interarea 12, the gate oxide 18 that is not etched can form second gate oxide 8, and the 3rd gate oxide district 19 that obtains after the etching is consistent with first grid oxide layer district 7 thickness that need obtain; The thickness in first grid oxide layer district 7 and the 3rd gate oxide district 19 is 500 à ~ 1500 à;
H, remove the photoresist on above-mentioned semiconductor substrate first interarea 12, and on first interarea 12 of above-mentioned semiconductor substrate deposit conductive polycrystalline silicon floor 20, described conductive polycrystalline silicon floor 20 is covered on the 3rd gate oxide 19 and second gate oxide 8;
As shown in Figure 9: behind deposit conductive polycrystalline silicon floor 20, can form conductive polycrystalline silicon 9; Described conductive polycrystalline silicon floor 20 covers in the 3rd gate oxide districts 19 and the second gate oxide district 8, and the 3rd gate oxide district 19 by etching conductive polysilicon layer 20 and corresponding conductive polycrystalline silicon floor 20 belows can access first grid oxide layer district 7;
I, optionally shelter and the above-mentioned conductive polycrystalline silicon floor 20 of etching, and corresponding the 3rd gate oxide district 19, the described conductive polycrystalline silicon floor of etching 20 belows, to obtain the first grid oxide layer district 7 and the second gate oxide district 8 on first interarea 12 of semiconductor substrate, the thickness in described first grid oxide layer district 7 is consistent with the thickness in the 3rd gate oxide district 19; All cover conductive polycrystalline silicon 9 in the first grid oxide layer district 7 and the second gate oxide district 8;
As shown in figure 10: during etching conductive polysilicon layer 20, corresponding the 3rd gate oxide district 19 of while etching, and reserve part the 3rd gate oxide district 19, the 3rd gate oxide district 19 of reservation forms first grid oxide layer district 7, and can access the conductive polycrystalline silicon 9 in the first grid oxide layer district 7;
J, with above-mentioned conductive polycrystalline silicon 9 as injecting masking layer, the p type impurity ion is injected in autoregistration on first interarea 12 of semiconductor substrate, and in the N of semiconductor substrate type drift layer 1, forming the P well region 6 that adjacent rule is arranged by elevated temperature heat process knot, the horizontal range between the described adjacent P well region 6 is not less than the width in the described second gate oxide district 8;
As shown in figure 11: described p type impurity ion can be the B ion, and behind the formation P well region 6, adjacent P well region 6 is isolated by the N post 3 that N type drift region 1 forms;
K, carry out the source region photoetching on first interarea 12 of above-mentioned semiconductor substrate, and inject N type foreign ion, form N+ source region 5 by elevated temperature heat process knot, described N+ source region 5 is positioned at P well region 6;
As shown in figure 12: described N type foreign ion can be the As ion, and the N+ source region 5 in the general P well region 6 is two; Described N+ source region 5 and corresponding P well region 6 contact with first grid oxide layer district 7;
L, on first interarea 12 of above-mentioned semiconductor substrate deposit insulating medium layer 10, described insulating medium layer 10 is covered in first interarea 12 of semiconductor substrate, and is covered on the conductive polycrystalline silicon 9;
Described insulating medium layer 10 can be silex glass (USG), boron-phosphorosilicate glass (BPSG) or phosphorosilicate glass (PSG).
M, on above-mentioned insulating medium layer 10, carry out hole photoetching and etching, obtain the source lead hole, described source lead hole is positioned at 9 of adjacent conductive polysilicons, and the source lead hole extends on first interarea 12 of semiconductor substrate from the surface of insulating medium layer 10;
As shown in figure 13: N+ source region 5 and P well region 6 can be exposed at the bottom of the hole in described source lead hole, after filling source metal 11, source metal 11 can with N+ source region 5 and P well region 6 ohmic contact;
N, on first interarea 12 of above-mentioned semiconductor substrate deposited metal, described metal level is filled in the source lead hole and is covered on the insulating medium layer 10, by metal level photoetching and etching being obtained source metal 11, described source metal 11 and N+ source region 5 and P well region 6 ohmic contact; Described metal level can be aluminium, copper or tungsten, to form the source terminal of power MOSFET device.
The working mechanism of MOSFET device of the present invention is: the MOS structure (Metal-oxide-semicondutor) that P well region 6 below conductive polycrystalline silicon 9, first grid oxide layer district 7 and the first grid oxide layer district 7 and N+ source region 5 have constituted a plane.Because the first grid oxidated layer thickness in first grid oxide layer district 7 and the gate oxide thickness basically identical of common plane type power MOSFET, thickness all is about 500 à ~ 1500 à, therefore, the threshold voltage of the threshold voltage vt h of MOSFET of the present invention and common planar type power MOSFET is basically identical also, in addition, also basically identical of the two mutual conductance Gfs.
The described second gate oxide district 8 is following owing to there is not P well region 6, therefore below conductive polycrystalline silicon 9, the second gate oxide district 8 and the second gate oxide district 8 N type drift layer 1 can't form the MOS structure, therefore, the grid oxygen in the second gate oxide district 8 can not exert an influence substantially to the threshold voltage and the mutual conductance of whole M OSFET device; Because second gate oxide thickness in the second gate oxide district 8 far is thicker than the first grid oxidated layer thickness in first grid oxide layer district 7, therefore the parasitic grid oxygen capacitor C ox Cox will be more common, that have the planar power MOSFET of first grid oxide layer 7 thickness of MOSFET device of the present invention reduces greatly, the Cox reduction can make the miller capacitance Crss of device also reduce, so just can improve the switching speed of device preferably, be reduced in the switching loss of device in switching process.
Gate oxide structure with two kinds of thickness provided by the invention, its technical process is comparatively simple, utilize existing ripe common process to realize, and, the thickness in the first grid oxide layer district 7 and the second gate oxide district 8 can be set according to the needs of device performance parameter are convenient, is suitable for very much big in batches production.Planar power MOSFET device architecture of the present invention and manufacture method also are applicable to the IGBT of plane, and be applied widely; Rein in that electric capacity is low, switching speed is fast, switching loss is low, technology simply reaches with low cost.
Claims (10)
1. planar power MOSFET device with super-junction structure, on the top plan view of described MOSFET device, comprise the cellular region and the terminal protection district that are positioned at semiconductor substrate, described terminal protection district is positioned at the outer ring of cellular region, and the terminal protection district is around surrounding cellular region; Comprise in the described cellular region that several rules is arranged and the cellular of connection parallel with one another; On the cross section of described MOSFET device, semiconductor substrate has corresponding first interarea and second interarea, comprises the first conduction type drift layer between described first interarea and second interarea; In the first conduction type drift layer of semiconductor substrate, comprise some to first post with first conduction type and second post with second conduction type; Described first post and second post extend in the first conduction type drift layer of semiconductor substrate along the current flowing direction; On the direction of vertical current circulation, many PN post alternately is connected setting by what described first post and second post constituted, in semiconductor substrate, form super-junction structure; It is characterized in that:
On the cross section of described MOSFET device, comprise second conductive type layer that is positioned at the first conduction type drift layer in the described cellular region, described second conductive type layer is connected with second conduction type, second post of described second conductive type layer below, the second adjacent conduction type interlayer is isolated by the first conduction type drift layer, is provided with the first conduction type injection region in second conductive type layer; First corresponding directly over the first conduction type drift layer between described adjacent second conductive type layer interarea is provided with the second gate oxide district, and the width in the described second gate oxide district is not more than the horizontal range between adjacent second conductive type layer in the first conduction type drift layer; The both sides in the second gate oxide district are provided with first grid oxide layer district, and the thickness in the described second gate oxide district is greater than the thickness in first grid oxide layer district; The first conduction type injection region part in first grid oxide layer district and corresponding second conductive type layer and described second conductive type layer overlaps and contacts; On first interarea of semiconductor substrate, near the second gate oxide district, one side, second conductive type layer coats the width of the horizontal range of the first conduction type injection region in second conductive type layer less than first grid oxide layer district;
All be coated with conductive polycrystalline silicon in the described first grid oxide layer district and the second gate oxide district, described conductive polycrystalline silicon is provided with insulating medium layer, and described insulating medium layer is covered on the corresponding conductive polycrystalline silicon and coats corresponding first grid oxide layer district, second gate oxide district and the conductive polycrystalline silicon; On first interarea of semiconductor substrate, adjacent dielectric interlayer is provided with the source lead hole, described source lead is filled with source metal in the hole, isolate by insulating medium layer between described source metal and conductive polycrystalline silicon, and described source metal while and the first conduction type injection region and the second conductive type layer ohmic contact.
2. according to the described planar power MOSFET device with super-junction structure of claim 1, it is characterized in that: on the cross section of described MOSFET device, super-junction structure is present in cellular region and the terminal protection district; The right width and the degree of depth of PN post is all identical arbitrarily in the cellular region.
3. according to the described planar power MOSFET device of claim 1 with super-junction structure, it is characterized in that: the material of described semiconductor substrate comprises silicon, semiconductor substrate comprises the first conduction type drift layer and is positioned at first conductivity type substrate of described first conduction type drift layer below that the described first conduction type drift layer is in abutting connection with first conductivity type substrate; Corresponding first interarea that forms in the surface of the first conduction type drift layer, corresponding second interarea that forms in the surface of first conductivity type substrate.
4. the manufacture method with planar power MOSFET device of super-junction structure is characterized in that the manufacture method of described power MOSFET device comprises the steps:
(a), provide the semiconductor substrate with two relative interareas, described semiconductor substrate to comprise first conductivity type substrate and be positioned at the first conduction type drift layer of described first conductivity type substrate top; Described two relative interareas comprise first interarea and second interarea;
(b), deposit hard mask layer on first interarea of above-mentioned semiconductor substrate;
(c), optionally shelter and the etching hard mask layer, form the hard mask open of a plurality of etching grooves,, utilize the anisotropic lithographic method in the first conduction type drift layer, to form a plurality of grooves by described hard mask open;
(d), on first interarea of above-mentioned semiconductor substrate deposit second conductive type epitaxial layer, described second conductive type epitaxial layer is filled in the groove, and is covered on first interarea of semiconductor substrate;
(e), second conductive type epitaxial layer that covers the first conduction type drift layer surface is polished and planarization, in the first conduction type drift layer, form second post with second conduction type;
(f), the gate oxide of on first interarea of above-mentioned semiconductor substrate, growing, described gate oxide is covered in first interarea of semiconductor substrate;
(g), utilize photoresist as masking layer, above-mentioned gate oxide is carried out photoetching and etching, obtaining the second gate oxide district and be positioned at the 3rd gate oxide district of both sides, the described second gate oxide district on first interarea of semiconductor substrate, the thickness in described the 3rd gate oxide district is less than the thickness in the second gate oxide district;
(h), remove the photoresist on above-mentioned semiconductor substrate first interarea, and on first interarea of above-mentioned semiconductor substrate the deposit conductive polycrystalline silicon floor, described conductive polycrystalline silicon floor is covered on the 3rd gate oxide and second gate oxide;
(i), optionally shelter and the above-mentioned conductive polycrystalline silicon floor of etching, and corresponding the 3rd gate oxide district, etching described conductive polycrystalline silicon floor below, to obtain the first grid oxide layer district and the second gate oxide district on first interarea of semiconductor substrate, the thickness in described first grid oxide layer district is consistent with the thickness in the 3rd gate oxide district; All cover conductive polycrystalline silicon in the first grid oxide layer district and the second gate oxide district;
(j), with above-mentioned conductive polycrystalline silicon as injecting masking layer, the second conductive type impurity ion is injected in autoregistration on first interarea of semiconductor substrate, and in the first conduction type drift layer of semiconductor substrate, forming second conductive type layer that adjacent rule is arranged by elevated temperature heat process knot, the horizontal range between described adjacent second conductive type layer is not less than the width in the described second gate oxide district;
(k), on first interarea of above-mentioned semiconductor substrate, carry out the source region photoetching, and inject the first conductive type impurity ion, form the first conduction type injection region by elevated temperature heat process knot, the described first conduction type injection region is positioned at second conductive type layer;
(l), on first interarea of above-mentioned semiconductor substrate the deposit insulating medium layer, described insulating medium layer is covered in first interarea of semiconductor substrate, and is covered on the conductive polycrystalline silicon;
(m), on above-mentioned insulating medium layer, carry out hole photoetching and etching, obtain the source lead hole, described source lead hole is positioned at the adjacent conductive inter polysilicon, and the source lead hole extends on first interarea of semiconductor substrate from the surface of insulating medium layer;
(n), deposited metal on first interarea of above-mentioned semiconductor substrate, described metal level is filled in the source lead hole and is covered on the insulating medium layer, by metal level photoetching and etching being obtained source metal, the described source metal and the first conduction type injection region and the second conductive type layer ohmic contact.
5. according to the described manufacture method with planar power MOSFET device of super-junction structure of claim 4, it is characterized in that: described insulating medium layer is silex glass (USG), boron-phosphorosilicate glass (BPSG) or phosphorosilicate glass (PSG).
6. according to the described manufacture method with planar power MOSFET device of super-junction structure of claim 4, it is characterized in that: described metal level is aluminium, copper or tungsten.
7. according to the described manufacture method with planar power MOSFET device of super-junction structure of claim 4, it is characterized in that: described hard mask layer is that LPTEOS, thermal oxidation silicon dioxide add chemical vapour deposition (CVD) silicon dioxide or thermal silicon dioxide adds silicon nitride.
8. according to the described manufacture method with planar power MOSFET device of super-junction structure of claim 4, it is characterized in that: the material of described semiconductor substrate comprises silicon.
9. according to the described manufacture method with planar power MOSFET device of super-junction structure of claim 4, it is characterized in that: the thickness in the described second gate oxide district is 2000 à ~ 5000 à.
10. according to the described manufacture method with planar power MOSFET device of super-junction structure of claim 4, it is characterized in that: the thickness in described first grid oxide layer district is 500 à ~ 1500 à.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110210968 CN102270663B (en) | 2011-07-26 | 2011-07-26 | Planar power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with super junction structure and manufacturing method of planar power MOSFET device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110210968 CN102270663B (en) | 2011-07-26 | 2011-07-26 | Planar power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with super junction structure and manufacturing method of planar power MOSFET device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102270663A true CN102270663A (en) | 2011-12-07 |
| CN102270663B CN102270663B (en) | 2013-01-23 |
Family
ID=45052890
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201110210968 Active CN102270663B (en) | 2011-07-26 | 2011-07-26 | Planar power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with super junction structure and manufacturing method of planar power MOSFET device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102270663B (en) |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102760647A (en) * | 2012-07-26 | 2012-10-31 | 上海宏力半导体制造有限公司 | Superstructure power device manufacturing method and semiconductor device manufacturing method |
| CN102931090A (en) * | 2012-08-17 | 2013-02-13 | 西安龙腾新能源科技发展有限公司 | Manufacturing method for super junction metal oxide semiconductor field effect transistor (MOSFET) |
| CN103325681A (en) * | 2012-03-20 | 2013-09-25 | 宁波敏泰光电科技有限公司 | Super-junction MOSFET with ions injected in self-aligned mode and manufacturing method thereof |
| CN103367157A (en) * | 2012-04-06 | 2013-10-23 | 北大方正集团有限公司 | Preparation method of super junction MOSFET |
| CN103579003A (en) * | 2012-08-09 | 2014-02-12 | 北大方正集团有限公司 | Method for manufacturing super joint MOSFET |
| CN104795445A (en) * | 2015-04-01 | 2015-07-22 | 苏州东微半导体有限公司 | Low-loss super-junction power device and manufacturing method thereof |
| CN104952928A (en) * | 2015-04-30 | 2015-09-30 | 苏州东微半导体有限公司 | Gate-drain capacitance slow change super-junction power device and manufacturing method thereof |
| CN106229343A (en) * | 2016-08-12 | 2016-12-14 | 上海鼎阳通半导体科技有限公司 | Superjunction devices |
| CN106298480A (en) * | 2015-05-22 | 2017-01-04 | 北大方正集团有限公司 | Superjunction devices manufacture method and superjunction devices |
| CN106340458A (en) * | 2016-10-11 | 2017-01-18 | 无锡同方微电子有限公司 | Manufacturing method for reducing manufacturing cost of deep-groove type super junction MOSFET |
| CN109166925A (en) * | 2018-08-29 | 2019-01-08 | 电子科技大学 | A kind of vertical-type power semiconductor devices and its manufacturing method |
| CN110600534A (en) * | 2019-09-05 | 2019-12-20 | 曾爱平 | Power device with super junction structure and manufacturing method thereof |
| CN112635549A (en) * | 2020-12-29 | 2021-04-09 | 江苏捷捷微电子股份有限公司 | Super-junction MOSFET device structure and manufacturing method |
| WO2021103092A1 (en) * | 2019-11-27 | 2021-06-03 | 苏州东微半导体有限公司 | Semiconductor super-junction power device |
| CN113690317A (en) * | 2021-08-19 | 2021-11-23 | 福建晋润半导体技术有限公司 | Planar power MOSFET device with super junction structure and manufacturing method thereof |
| CN114093866A (en) * | 2021-11-19 | 2022-02-25 | 陕西亚成微电子股份有限公司 | MOSFET structure of integrated starting device and manufacturing method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1405897A (en) * | 2001-06-11 | 2003-03-26 | 株式会社东芝 | Power semiconducter device with RESURF layer |
| US7042046B2 (en) * | 2000-02-09 | 2006-05-09 | Fuji Electric Device Technology Co., Ltd. | Super-junction semiconductor device and method of manufacturing the same |
| CN1812129A (en) * | 2004-12-28 | 2006-08-02 | 株式会社东芝 | Semiconductor device and method of manufacturing the same |
| US7402863B2 (en) * | 2004-06-21 | 2008-07-22 | International Rectifier Corporation | Trench FET with reduced mesa width and source contact inside active trench |
| CN202205755U (en) * | 2011-07-26 | 2012-04-25 | 无锡新洁能功率半导体有限公司 | Plane power MOSFET device having super junction structure |
-
2011
- 2011-07-26 CN CN 201110210968 patent/CN102270663B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7042046B2 (en) * | 2000-02-09 | 2006-05-09 | Fuji Electric Device Technology Co., Ltd. | Super-junction semiconductor device and method of manufacturing the same |
| CN1405897A (en) * | 2001-06-11 | 2003-03-26 | 株式会社东芝 | Power semiconducter device with RESURF layer |
| US7402863B2 (en) * | 2004-06-21 | 2008-07-22 | International Rectifier Corporation | Trench FET with reduced mesa width and source contact inside active trench |
| CN1812129A (en) * | 2004-12-28 | 2006-08-02 | 株式会社东芝 | Semiconductor device and method of manufacturing the same |
| CN202205755U (en) * | 2011-07-26 | 2012-04-25 | 无锡新洁能功率半导体有限公司 | Plane power MOSFET device having super junction structure |
Cited By (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103325681A (en) * | 2012-03-20 | 2013-09-25 | 宁波敏泰光电科技有限公司 | Super-junction MOSFET with ions injected in self-aligned mode and manufacturing method thereof |
| CN103325681B (en) * | 2012-03-20 | 2016-04-20 | 宁波敏泰光电科技有限公司 | The super node MOSFET that a kind of ion autoregistration is injected and manufacture method thereof |
| CN103367157B (en) * | 2012-04-06 | 2015-12-09 | 北大方正集团有限公司 | A kind of preparation method of super node MOSFET |
| CN103367157A (en) * | 2012-04-06 | 2013-10-23 | 北大方正集团有限公司 | Preparation method of super junction MOSFET |
| CN102760647A (en) * | 2012-07-26 | 2012-10-31 | 上海宏力半导体制造有限公司 | Superstructure power device manufacturing method and semiconductor device manufacturing method |
| CN102760647B (en) * | 2012-07-26 | 2016-08-31 | 上海华虹宏力半导体制造有限公司 | Super junction power device manufacture method and method, semi-conductor device manufacturing method |
| CN103579003B (en) * | 2012-08-09 | 2016-02-03 | 北大方正集团有限公司 | A kind of method making super node MOSFET |
| CN103579003A (en) * | 2012-08-09 | 2014-02-12 | 北大方正集团有限公司 | Method for manufacturing super joint MOSFET |
| CN102931090B (en) * | 2012-08-17 | 2015-06-03 | 西安龙腾新能源科技发展有限公司 | Manufacturing method for super junction metal oxide semiconductor field effect transistor (MOSFET) |
| CN102931090A (en) * | 2012-08-17 | 2013-02-13 | 西安龙腾新能源科技发展有限公司 | Manufacturing method for super junction metal oxide semiconductor field effect transistor (MOSFET) |
| CN104795445A (en) * | 2015-04-01 | 2015-07-22 | 苏州东微半导体有限公司 | Low-loss super-junction power device and manufacturing method thereof |
| CN104952928A (en) * | 2015-04-30 | 2015-09-30 | 苏州东微半导体有限公司 | Gate-drain capacitance slow change super-junction power device and manufacturing method thereof |
| CN106298480A (en) * | 2015-05-22 | 2017-01-04 | 北大方正集团有限公司 | Superjunction devices manufacture method and superjunction devices |
| CN106229343A (en) * | 2016-08-12 | 2016-12-14 | 上海鼎阳通半导体科技有限公司 | Superjunction devices |
| CN106229343B (en) * | 2016-08-12 | 2019-05-03 | 上海鼎阳通半导体科技有限公司 | Superjunction devices |
| CN106340458A (en) * | 2016-10-11 | 2017-01-18 | 无锡同方微电子有限公司 | Manufacturing method for reducing manufacturing cost of deep-groove type super junction MOSFET |
| CN109166925A (en) * | 2018-08-29 | 2019-01-08 | 电子科技大学 | A kind of vertical-type power semiconductor devices and its manufacturing method |
| CN110600534A (en) * | 2019-09-05 | 2019-12-20 | 曾爱平 | Power device with super junction structure and manufacturing method thereof |
| WO2021103092A1 (en) * | 2019-11-27 | 2021-06-03 | 苏州东微半导体有限公司 | Semiconductor super-junction power device |
| JP2022522476A (en) * | 2019-11-27 | 2022-04-19 | 蘇州東微半導体股▲ふん▼有限公司 | Semiconductor superjunction power device |
| JP7177551B2 (en) | 2019-11-27 | 2022-11-24 | 蘇州東微半導体股▲ふん▼有限公司 | Semiconductor super junction power device |
| US11908889B2 (en) | 2019-11-27 | 2024-02-20 | Suzhou Oriental Semiconductor Co., Ltd. | Semiconductor super-junction power device |
| CN112635549A (en) * | 2020-12-29 | 2021-04-09 | 江苏捷捷微电子股份有限公司 | Super-junction MOSFET device structure and manufacturing method |
| CN113690317A (en) * | 2021-08-19 | 2021-11-23 | 福建晋润半导体技术有限公司 | Planar power MOSFET device with super junction structure and manufacturing method thereof |
| CN114093866A (en) * | 2021-11-19 | 2022-02-25 | 陕西亚成微电子股份有限公司 | MOSFET structure of integrated starting device and manufacturing method |
| CN114093866B (en) * | 2021-11-19 | 2023-03-14 | 陕西亚成微电子股份有限公司 | MOSFET structure of integrated starting device and manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102270663B (en) | 2013-01-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102270663B (en) | Planar power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with super junction structure and manufacturing method of planar power MOSFET device | |
| US7368785B2 (en) | MOS transistor device structure combining Si-trench and field plate structures for high voltage device | |
| CN101536163B (en) | Charge balance field effect transistor | |
| CN101290936B (en) | Semiconductor device and method for manufactruing of the same | |
| CN107204372A (en) | A kind of channel-type semiconductor device and manufacture method for optimizing terminal structure | |
| US8445958B2 (en) | Power semiconductor device with trench bottom polysilicon and fabrication method thereof | |
| CN101916779B (en) | SOI super junction LDMOS structure capable of completely eliminating substrate-assisted depletion effect | |
| KR20180135035A (en) | Super-junction power transistor and manufacturing method thereof | |
| CN104779166B (en) | A kind of plough groove type divides grid power device and its manufacture method | |
| TW202006956A (en) | Power MOSFET with an integrated pseudo-Schottky diode in source contact trench | |
| CN107464837B (en) | Super junction power device | |
| CN104377244A (en) | Device structure lowering LDMOS on resistance | |
| KR100656239B1 (en) | Trench-Gated Power Device Having Trench Walls Formed By Selective Epitaxial Growth | |
| CN102456738A (en) | VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) transistor | |
| CN105027290B (en) | The MOSFET technologies of adaptive charge balance | |
| CN202205755U (en) | Plane power MOSFET device having super junction structure | |
| US8575688B2 (en) | Trench device structure and fabrication | |
| CN105826360A (en) | Trench-type semi super junction power device and manufacturing method thereof | |
| CN103681817B (en) | IGBT device and preparation method thereof | |
| CN106887451B (en) | Super junction device and manufacturing method thereof | |
| US7233043B2 (en) | Triple-diffused trench MOSFET | |
| CN107546274B (en) | LDMOS device with step-shaped groove | |
| TWI601295B (en) | Split-gate mosfet | |
| CN103117309A (en) | Horizontal power device structure and preparation method thereof | |
| CN106876450B (en) | Vertical field effect transistor with low gate-drain capacitance and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: WUXI NCE POWER CO., LTD. Free format text: FORMER OWNER: NCE POWER SEMICONDUCTOR CO., LTD. Effective date: 20130311 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20130311 Address after: 214131, Jiangsu, Wuxi Province Lake High East Road No. 999 (and Huaqing Road intersection), Wuxi (Binhu) national information sensing center -B1 building on the east side of the second floor Patentee after: Wuxi NCE Power Co., Ltd. Address before: 214131, Jiangsu, Wuxi Province Lake High East Road, No. 999, Wuxi (Binhu) National sensing information center set sail building, 8 floor Patentee before: NCE Power Semiconductor Co., Ltd. |