CN103325681A - Super-junction MOSFET with ions injected in self-aligned mode and manufacturing method thereof - Google Patents
Super-junction MOSFET with ions injected in self-aligned mode and manufacturing method thereof Download PDFInfo
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- CN103325681A CN103325681A CN2012100740435A CN201210074043A CN103325681A CN 103325681 A CN103325681 A CN 103325681A CN 2012100740435 A CN2012100740435 A CN 2012100740435A CN 201210074043 A CN201210074043 A CN 201210074043A CN 103325681 A CN103325681 A CN 103325681A
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Abstract
The invention discloses a super-junction MOSFET with ions injected in a self-aligned mode and a manufacturing method of the super-junction MOSFET. In the technology of manufacturing MOS pipes, when an oxide layer rather than a photo-etching layer is used as a blocking layer, the ions injecting effect of the oxide layer is better, and the feature size of the super-junction MOSFET after the super-junction MOSFET is etched cannot be influenced by a side wall. Meanwhile, the processing steps of photo-etching when the ions are injected are reduced, therefore, production cost can be reduced, depreciation speed of a photo-etching machine is retarded, time of the whole technology process can be also reduced, and good economic benefits are brought to enterprises.
Description
Technical field
The present invention relates to a kind of structure and manufacture method of semiconductor device, relate in particular to super node MOSFET and manufacture method that a kind of ion autoregistration is injected.
Background technology
Metal-oxide-semiconductor field effect transistor (MOSFET) is current transistor types the most commonly used, in fact, all large scale integrated circuits (microprocessor, memory, digital electronics system etc.) all are to be based upon on the basis that utilizes the MOS technology.The technique of making metal-oxide-semiconductor is very complicated, most of semiconductor process flows mainly occur in several microns of silicon chip top layer, so silicon top material all is the part of the required hierarchy of each device on the interconnect die, in order to increase multiple layer metal and insulating barrier, technological process requires silicon chip to circulate in the different process step.
The MOSFET technological process of a routine comprises following making step at least (referring to the teaching material of relevant silicon integrated technique aspect, such as Michael Quirk, Julian Serda work, Han Qiusheng etc. translate, " semiconductor fabrication " that the Electronic Industry Press publishes): (1), oxidation (support the field); (2), photoresist gluing; (3), mask plate-silicon chip is aimed at and exposure; (4), photoresist developing; (5), silica etching; (6), photoresist is removed; (7), oxidation (gate oxidation silicon); (8), polysilicon deposit; (9), polysilicon photoetching and etching; (10), Implantation; (11), active area; (12), silicon nitride deposition; (13), contact etching; (14), metal deposit and etching.The Implantation in above-mentioned the tenth step is the transistorized source-drain area of definition; each transistor will be through twice injection; it once is the shallow injection that lightly doped drain (LDD) injects; the source/leakage that is subsequently medium or high dose is injected; its step is that the photoresist on silicon chip applies, and mask plate is aimed at and exposure, develops; in the zone of not protected by photoresist, ion is selected to enter.Wherein, photoetching process is one of of paramount importance processing step during semiconductor is made, mainly be with the graph copying on the mask plate to silicon chip, for next step etching or ion injecting process ready, the cost of photoetching is about 1/3rd of whole silicon chip manufacturing process, and elapsed time accounts for 40% ~ 60% of whole silicon chip technique.And the mask aligner that uses in the photoetching process then is board the most expensive on the production line, and general 5 ~ 1,500 ten thousand dollars, its depreciation speed is very fast, about 3 ~ 90,000 RMB every days.
" semiconductor optoelectronic " December in 2008 the 6th phase of the 29th volume discloses one piece of " photoresist slope on Implantation after the impact of pattern character size " by name literary composition, this article is pointed out, in the photoetching process of CCD, the steepness of photoresist from exposure region to the non-exposed area transition is not 90 desirable degree, at this moment caused by the type impact of exposure wavelength and light source dosage, photoresist, and such side wall all may impact the dimension of picture after Implantation, the etching.
Summary of the invention
The present invention is in order to overcome the deficiencies in the prior art, and super node MOSFET and manufacture method that a kind of ion autoregistration that provides is injected, in making metal-oxide-semiconductor technique, when utilizing oxide skin(coating) to compare with photoresist as the barrier layer as the barrier layer, its Implantation is effective, and the characteristic size after the etching can not be affected because of side wall; Simultaneously, the processing step of photoetching when having reduced Implantation, it can not only reduce production costs, and slows down the depreciation speed of mask aligner, time that can also less whole technical process, thus bring good economic benefit to enterprise.
To achieve these goals, the present invention is by the following technical solutions:
A kind of manufacture method of super node MOSFET of autoregistration Implantation may further comprise the steps:
(1). a semiconductor is provided, and described semiconductor comprises Semiconductor substrate and at the first conduction epitaxial loayer that the semiconductor substrate surface deposit forms, forms a plurality of grooves with lithographic method on the first conduction epitaxial loayer;
(2). at semi-conductive first type surface deposit the second conduction epitaxial loayer, described the second conduction epitaxial loayer is filled in the groove, forms the second conduction extension post;
(3). utilize chemical mechanical polishing method to remove the conduction of second on semiconductor first type surface epitaxial loayer;
(4). even growth regulation one deck oxide on semi-conductive first type surface, utilize photoresist as masking layer, this ground floor oxide is carried out photoetching and etching, keep the ground floor oxide of the second conduction extension post top;
(5). photoetching, etching, inject first kind foreign ion and form well region;
(6). remove the photoresist on the above-mentioned semiconductor first type surface, and at the semi-conductive first type surface gate oxide of growing, described gate oxide covers above-mentioned ground floor oxide;
(7). depositing polysilicon on above-mentioned semi-conductive first type surface, described polysilicon covers above-mentioned gate oxide;
(8). utilize photoresist to make masking layer, optionally the above-mentioned polysilicon of etching forms the gate oxide district;
(9). inject masking layer with above-mentioned the first oxide layer district and gate oxide region as the Equations of The Second Kind foreign ion, in not capped zone, the second foreign ion penetrates the upper surface of the first conduction epitaxial loayer and the second conduction epitaxial loayer, to define source-drain area, described Equations of The Second Kind foreign ion is positioned at well region;
(10). remove the first oxide layer on the above-mentioned semiconductor first type surface and be positioned at gate oxide and polysilicon on the first oxide layer, deposit insulating medium layer on the semiconductor first type surface then, described insulating medium layer covers polysilicon;
(11). carry out contact hole photoetching and etching at above-mentioned insulating medium layer, obtain the source lead hole;
(12). deposited metal on above-mentioned semi-conductive first type surface, described metal level is covered on the insulating medium layer, by metal level being carried out photoetching and etching obtains source metal.
Barrier layer when the gate oxide district that second ground floor oxide and (6), (7), (8) step of conducting electricity extension post upper end that the present invention utilized for (4) step formed forms is Implantation, so that the ion autoregistration is injected, reduced lithography step required when the traditional handicraft intermediate ion injects.
As preferably, described Semiconductor substrate is heavily doped monocrystalline substrate, and described the first conduction epitaxial loayer is monocrystalline silicon layer.Monocrystalline silicon is the monocrystal of silicon, is a kind of good semi-conducting material, is usually used in making semiconductor device.
As preferably, described Semiconductor substrate is the heavily doped monocrystalline silicon of N-shaped, and described the first conduction epitaxial loayer is N-shaped monocrystalline silicon, and described the second conduction epitaxial loayer is p-type monocrystalline silicon.
As preferably, the thickness of described ground floor oxide is 4000 ~ 6000 dusts.
The super node MOSFET that a kind of ion autoregistration is injected, the source-drain area that comprises Semiconductor substrate, the first conduction epitaxial loayer, well region and form in well region is successively in abutting connection with the semiconductor substrate that forms, and a plurality of gate oxides district on semiconductor substrate and a plurality of source electrode contact hole, it is characterized in that: be etched with a plurality of grooves in described the first conduction epitaxial loayer, be filled with the second conduction epitaxial loayer in the described groove, form the post district; Conduction epitaxial loayer in the described post district second forms super-junction structure with described first conduction epitaxial loayer formation is many that the PN post alternately is connected setting in semiconductor substrate.
As preferably, described post sector width is identical, uniformly-spaced arranges between the post district, and described well region is positioned at the upper end in post district.
As preferably, described gate oxide district contacts with well region and source region.
As preferably, right width and the degree of depth of described any PN post is all identical.
As preferably, be formed with insulating medium layer at above-mentioned MOSFET, and the first layer metal that on insulating medium layer, once forms interconnection, second layer metal interconnection and three layer metal interconnect.The number of metal level is along with the difference of tube core complexity changes to some extent.
As preferably, the metal interconnecting layer on the insulating medium layer of described MOSFET comprises tungsten and titanium nitride.Doing local interconnecting metal with tungsten is that secondly, tungsten has good grinding and polishing characteristic because tungsten can form tungsten plug (Plug) without filler opening spatially, and titanium nitride serves as the diffusion impervious layer of tungsten.
Compared with prior art, the present invention has following beneficial effect: (1) as the Implantation barrier layer, the ion autoregistration is injected with oxide layer, and the characteristic size of oxide layer is controlled well than the characteristic size of photoresist; (2) in this processing step of Implantation, reduced the step of a photoetching.
Description of drawings
Fig. 1 is structural representation of the present invention.
Fig. 2 ~ Figure 14 is implementation process flow steps figure of the present invention:
Fig. 2 is semi-conductive cutaway view.
Fig. 3 is the cutaway view after semiconductor etching forms groove.
Fig. 4 is the cutaway view of filling P type extension in semiconductor first type surface and the groove.
Fig. 5 is that the semiconductor first type surface is removed the cutaway view that unnecessary P type is delayed outward with chemical mechanical polishing method.
Fig. 6 is growth one deck SiO on the semiconductor first type surface
2Cutaway view behind the layer.
Fig. 7 utilizes the chemical wet etching method to keep the SiO of groove upper part
2The cutaway view of layer.Fig. 8 is the cutaway view behind the formation well region.
Fig. 9 is the cutaway view behind the growth gate oxide.
Figure 10 is the cutaway view of depositing polysilicon.
Figure 11 is the cutaway view that etching forms the gate oxide district.
Figure 12 is the cutaway view behind the Implantation well region.
Figure 13 is the cutaway view behind the formation insulating medium layer.
Figure 14 is the cutaway view behind the formation source metal.
Among the figure, 1-N+ substrate, 2-N-type epitaxial loayer, 3-groove, 4-P type epitaxial loayer, 5-P type post, 6-ground floor oxide, 7-P well region, 8-gate oxide, 9-polysilicon, 10-N+ source region, 11-insulating medium layer, 12-metal level.
Embodiment
The invention will be further described below in conjunction with the drawings and specific embodiments.
Shown in Fig. 2 ~ 14: the present invention is take N-type MOSFET device as example, and a kind of manufacture method of autoregistration Implantation super node MOSFET may further comprise the steps:
A., a semiconductor is provided, and described semiconductor comprises N+ substrate 1 and the N-type epitaxial loayer 2 that forms in the semiconductor substrate surface deposit, forms a plurality of grooves 3 with lithographic method on N-type epitaxial loayer 2;
B. at semi-conductive first type surface deposit P type epitaxial loayer 4, described P type epitaxial loayer 4 is filled in the groove 3, forms P type post 5;
C. utilize chemical mechanical polishing method to remove P type epitaxial loayer 4 on the semiconductor first type surface;
D. even growth regulation one deck oxide 6 on semi-conductive first type surface utilizes photoresist as masking layer, and this ground floor oxide is carried out photoetching and etching, keeps the ground floor oxide 6 of P type post 5 tops;
E. photoetching, etching are injected first kind foreign ion and are formed P well region 7;
F. remove the photoresist on the above-mentioned semiconductor first type surface, and at semi-conductive first type surface growth gate oxide 8, described gate oxide 8 covers above-mentioned ground floor oxide 6; The thickness of gate oxide is between 300 ~ 1000 dusts.
G. depositing polysilicon on above-mentioned semi-conductive first type surface, described polysilicon covers above-mentioned gate oxide;
H. utilize photoresist to make masking layer, optionally the above-mentioned polysilicon 9 of etching forms the gate oxide district;
I. inject masking layer with above-mentioned ground floor oxide 6 and gate oxide district as the Equations of The Second Kind foreign ion, in not capped zone, the upper surface of N+ ion penetration N-type epitaxial loayer 2 and P type epitaxial loayer 4, to define N+ source region 10, described N+ ion is positioned at P well region 7;
J. remove the ground floor oxide 6 on the above-mentioned semiconductor first type surface and be positioned at gate oxide 8 and polysilicon 9 on the ground floor oxide 6, deposit insulating medium layer 11 on the semiconductor first type surface then, described insulating medium layer 11 covers polysilicons 9;
K. carry out contact hole photoetching and etching at above-mentioned insulating medium layer 11, obtain the source lead hole;
L. deposited metal 12 on above-mentioned semi-conductive first type surface, described metal level 12 is covered on the insulating medium layer 11, by metal level 12 being carried out photoetching and etching obtains source metal.
The thickness of described ground floor oxide is 4000 ~ 6000 dusts, covers whole semiconductor.
Preferably, the present invention adopts thermal oxidation method growth regulation one deck oxide, and its thickness is 5000 dusts.
As shown in Figure 1: take N-type MOSFET device as example, the super node MOSFET that a kind of ion autoregistration is injected, the N+ source region 10 that comprises N+ substrate 1, N-type epitaxial loayer 2, P well region 7 and form in P well region 7 is successively in abutting connection with the semiconductor substrate that forms, and the gate oxide district on semiconductor substrate and source electrode contact hole, be etched with groove 3 in described the first conduction epitaxial loayer, be filled with P type epitaxial loayer 4 in the described groove 3, form P type post 5; P type epitaxial loayer 4 in the described P type post 5 consists of the PN post with described N-type epitaxial loayer 2 and alternately is connected setting, forms super-junction structure in semiconductor substrate.Described P type post 5 width are identical, uniformly-spaced arrange between the P type post 5, and described P well region 7 is positioned at the upper end of P type post 5; Described gate oxide district contacts with P well region 7 and N+ source region 10; Right width and the degree of depth of described any PN post is all identical; Be formed with insulating medium layer 11 at above-mentioned MOSFET, and the first layer metal that on insulating medium layer 11, once forms interconnection, second layer metal interconnection and three layer metal interconnect; Metal interconnecting layer on the insulating medium layer 11 of described MOSFET comprises tungsten and titanium nitride.
Preferably, the insulating medium layer among the present invention adopts the silicon oxide layer PSG(phosphorosilicate glass of mixing phosphorus), be the reflux temperature of reduction silicon dioxide, but the doped with boron element forms BPSG.
Backing material among the present invention is N+(100) crystal orientation, resistivity is the silicon polished of 0.001 ~ 0.002ohmm, the thickness of epitaxial loayer is 4 ~ 10um, and resistivity is between 0.1 ~ 10ohmm.The degree of depth of groove is between 1.0 ~ 1.5um, and the width of groove is between 0.5 ~ 1.0um.
The super node MOSFET that ion autoregistration of the present invention is injected is applicable in the Terminal Design, can be used as the part of cmos circuit, also can be used as the part of integrated circuit.
Claims (10)
1. the super node MOSFET manufacture method of an autoregistration Implantation is characterized in that following steps:
(1). a semiconductor is provided, and described semiconductor comprises Semiconductor substrate and at the first conduction epitaxial loayer that the semiconductor substrate surface deposit forms, forms a plurality of grooves with lithographic method on the first conduction epitaxial loayer;
(2). at semi-conductive first type surface deposit the second conduction epitaxial loayer, described the second conduction epitaxial loayer is filled in the groove, forms the second conduction extension post;
(3). utilize chemical mechanical polishing method to remove the conduction of second on semiconductor first type surface epitaxial loayer;
(4). even growth regulation one deck oxide on semi-conductive first type surface, utilize photoresist as masking layer, this ground floor oxide is carried out photoetching and etching, keep the ground floor oxide of the second conduction extension post top;
(5). photoetching, etching, inject first kind foreign ion and form well region;
(6). remove the photoresist on the above-mentioned semiconductor first type surface, and at the semi-conductive first type surface gate oxide of growing, described gate oxide covers above-mentioned ground floor oxide;
(7). depositing polysilicon on above-mentioned semi-conductive first type surface, described polysilicon covers above-mentioned gate oxide;
(8). utilize photoresist to make masking layer, optionally the above-mentioned polysilicon of etching forms the gate oxide district;
(9). inject masking layer with above-mentioned ground floor oxide region and gate oxide region as the Equations of The Second Kind foreign ion, in not capped zone, the second foreign ion penetrates the upper surface of the first conduction epitaxial loayer and the second conduction epitaxial loayer, to define source-drain area, described Equations of The Second Kind foreign ion is positioned at well region;
(10). remove the ground floor oxide on the above-mentioned semiconductor first type surface and be positioned at gate oxide and polysilicon on the ground floor oxide, deposit insulating medium layer on the semiconductor first type surface then, described insulating medium layer covers polysilicon;
(11). carry out contact hole photoetching and etching at above-mentioned insulating medium layer, obtain the source lead hole;
(12). deposited metal on above-mentioned semi-conductive first type surface, described metal level is covered on the insulating medium layer, by metal level being carried out photoetching and etching obtains source metal.
2. manufacture method according to claim 1, it is characterized in that: described Semiconductor substrate is heavily doped monocrystalline substrate, described the first conduction epitaxial loayer is monocrystalline silicon layer.
3. manufacture method according to claim 1 and 2, it is characterized in that: described Semiconductor substrate is the heavily doped monocrystalline silicon of N-shaped, and described the first conduction epitaxial loayer is N-shaped monocrystalline silicon, and described the second conduction epitaxial loayer is p-type monocrystalline silicon.
4. manufacture method according to claim 1, it is characterized in that: the thickness of described ground floor oxide is 4000 ~ 6000 dusts.
5. the super node MOSFET that injects of an ion autoregistration, the source-drain area that comprises Semiconductor substrate, the first conduction epitaxial loayer, well region and form in well region is successively in abutting connection with the semiconductor substrate that forms, and the gate oxide district on semiconductor substrate and source electrode contact hole, it is characterized in that: be etched with groove in described the first conduction epitaxial loayer, be filled with the second conduction epitaxial loayer in the described groove, form the post district; In the described post district second conduction epitaxial loayer consists of the PN post with described the first conduction epitaxial loayer and alternately is connected setting, forms super-junction structure in semiconductor substrate.
6. the super node MOSFET that injects of ion autoregistration according to claim 5, it is characterized in that: described post sector width is identical, uniformly-spaced arranges between the post district, and described well region is positioned at the upper end in post district.
7. the super node MOSFET that injects of ion autoregistration according to claim 5, it is characterized in that: described gate oxide district contacts with well region and source region.
8. the super node MOSFET that injects of ion autoregistration according to claim 5 is characterized in that: right width and the degree of depth of described any PN post is all identical.
9. the super node MOSFET that injects of ion autoregistration according to claim 5, it is characterized in that: be formed with insulating medium layer at above-mentioned MOSFET, and the first layer metal that on insulating medium layer, once forms interconnection, second layer metal interconnection and three layer metal interconnect.
10. according to claim 5 or the self aligned super node MOSFET of 9 described Implantations, it is characterized in that: the metal interconnecting layer on the insulating medium layer of described MOSFET comprises tungsten and titanium nitride.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108807517A (en) * | 2018-06-29 | 2018-11-13 | 上海华虹宏力半导体制造有限公司 | Groove grid super node device and its manufacturing method |
| WO2018223387A1 (en) * | 2017-06-09 | 2018-12-13 | 苏州晶湛半导体有限公司 | Reinforced switch device and method for manufacturing same |
| CN109671626A (en) * | 2018-12-12 | 2019-04-23 | 吉林华微电子股份有限公司 | IGBT device and production method with negative-feedback capacitor |
| WO2024001327A1 (en) * | 2022-11-14 | 2024-01-04 | 芯联越州集成电路制造（绍兴）有限公司 | Mosfet device and manufacturing method therefor |
| CN117637607A (en) * | 2024-01-24 | 2024-03-01 | 北京智芯微电子科技有限公司 | Method for forming self-aligned contact groove of super-junction semiconductor and super-junction semiconductor structure |
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| US20110284957A1 (en) * | 2010-05-20 | 2011-11-24 | Renesas Electronics Corporation | Semiconductor device and method for manufacturing the same |
| CN102270663A (en) * | 2011-07-26 | 2011-12-07 | 无锡新洁能功率半导体有限公司 | Planar power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with super junction structure and manufacturing method of planar power MOSFET device |
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| US20110284957A1 (en) * | 2010-05-20 | 2011-11-24 | Renesas Electronics Corporation | Semiconductor device and method for manufacturing the same |
| CN102270663A (en) * | 2011-07-26 | 2011-12-07 | 无锡新洁能功率半导体有限公司 | Planar power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with super junction structure and manufacturing method of planar power MOSFET device |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2018223387A1 (en) * | 2017-06-09 | 2018-12-13 | 苏州晶湛半导体有限公司 | Reinforced switch device and method for manufacturing same |
| CN110100313A (en) * | 2017-06-09 | 2019-08-06 | 苏州晶湛半导体有限公司 | A kind of enhanced switching device and its manufacturing method |
| US10998435B2 (en) | 2017-06-09 | 2021-05-04 | Enkris Semiconductor, Inc. | Enhancement-mode device and method for manufacturing the same |
| CN108807517A (en) * | 2018-06-29 | 2018-11-13 | 上海华虹宏力半导体制造有限公司 | Groove grid super node device and its manufacturing method |
| CN108807517B (en) * | 2018-06-29 | 2021-06-08 | 上海华虹宏力半导体制造有限公司 | Trench gate super junction device and manufacturing method thereof |
| CN109671626A (en) * | 2018-12-12 | 2019-04-23 | 吉林华微电子股份有限公司 | IGBT device and production method with negative-feedback capacitor |
| CN109671626B (en) * | 2018-12-12 | 2021-09-28 | 吉林华微电子股份有限公司 | IGBT device with negative feedback capacitor and manufacturing method |
| WO2024001327A1 (en) * | 2022-11-14 | 2024-01-04 | 芯联越州集成电路制造（绍兴）有限公司 | Mosfet device and manufacturing method therefor |
| CN117637607A (en) * | 2024-01-24 | 2024-03-01 | 北京智芯微电子科技有限公司 | Method for forming self-aligned contact groove of super-junction semiconductor and super-junction semiconductor structure |
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