KR100646561B1 - Cmos type semiconductor device and method of forming the same - Google Patents

Abstract

A CMOS semiconductor device is provided to block a leakage current without varying the density of well impurities, the width and depth of an isolation layer and a gate voltage by preventing a channel from being formed under the isolation layer. Impurities are implanted into a portion under an isolation layer(10) of a substrate to form a junction. A part of a gate pattern(150) crossing the isolation layer has a greater width than that of a part of the gate pattern crossing a well. At least a partial thickness of the lower part of the gate pattern crossing the isolation layer is undoped with impurities. The impurity-undoped layer has a thickness of 1/2 to 3/4 of the gate pattern.

Description

CMOS type semiconductor device and method of forming the same

1 and 2 form an isolation layer on a substrate to form a conventional CMOS type semiconductor device, form an N-type well and a P-type well based on the isolation layer, and then form a gate insulating layer on the substrate. Process cross section and plan view which show the state in which the gate pattern was formed from the polysilicon,

FIG. 3 is an explanatory diagram showing that the V voltage is applied to the lower layer of the gate pattern in the semiconductor device as shown in FIG. 1, and the potential is decreased from the top of the device isolation layer to apply the threshold voltage Vr below the bottom of the device isolation layer.

Figures 4 and 5 form a photoresist pattern on the part of the device isolation layer between the N well and the P well in the method of the present invention, and ion implantation is performed at the same dose as the conventional ion implantation energy and dose while the other part is exposed. Process cross-sectional view and plan view,

6 and 7 remove the photoresist pattern formed on the device isolation layer in the next step of FIGS. 4 and 5, form an ion implantation mask with a new photoresist pattern, and implant ion into the gate pattern portion on the device isolation layer. A cross-sectional view and a plan view showing a step of implementing the

FIG. 8 is an explanatory diagram showing that the V voltage is applied to the gate pattern middle layer in the semiconductor device as shown in FIG. 6 and the potential is decreased from the gate pattern middle layer to apply the threshold voltage Vr above the bottom of the device isolation layer.

* Explanation of symbols for the main parts of the drawings

10: device separator 20: N well

30: P-well 40: gate insulating film

50,150: gate pattern

110: photoresist pattern 120: ion implantation mask pattern

1511: upper layer 1513: lower layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS semiconductor device, and more particularly, to a CMOS semiconductor device having a structure capable of suppressing a leakage current through a device isolation film and a method of forming the same.

The trend of device integration and high-definition of semiconductor devices reduces the size of semiconductor devices formed on chips. As the device becomes more miniaturized, various problems can occur. As an example of the short channel effect, as the device size decreases, the channel length, which is a signal transmission region, decreases, thereby reducing the threshold voltage (Vt). Therefore, it is difficult to keep the operating voltage constant in the formed MOS transistor.

In addition, due to the high integration of the device, the width and depth of the device isolation layer that is the boundary between the device and the device are also limited by the difficulty in the process. As the width or depth of the device isolation layer that separates the devices decreases, there is a problem that a leakage current is generated under the device isolation layer even by a small voltage difference between the two wells. The device isolation layer may be formed using a LOCOS method and a trench trench method (STI), and these problems may occur in all of these cases, especially in the STI method which is widely applied to highly integrated semiconductor devices. have.

In order to prevent leakage current to the lower portion of the isolation layer, ion implantation may also be performed on the leakage current path at the lower end of the isolation layer to form a barrier by a junction.

1 and 2 illustrate a device isolation film 10 formed on a substrate 100 to form a conventional CMOS type semiconductor device, and an N-type well and a P-type well based on the device isolation film 10. A cross-sectional view and a plan view showing a state in which a gate insulating film and a gate pattern are formed of polysilicon on a substrate after forming a film. These well formation processes are formed by a conventional method through an exposure process and an ion implantation process. For example, the N well 20 region is covered with a photoresist pattern, P-type ion implantation is performed in the open region, the photoresist pattern is removed, and the P well 30 region is covered with a photoresist pattern, and the N-type ion implantation is performed. Will be implemented.

An active region well is formed based on the center of the device isolation layer when installing a well for forming a device of a semiconductor device. The ion implantation energy is controlled to reduce the leakage current flowing to the lower portion of the device isolation layer, and ion implantation is also performed below the device isolation layer 10. Can be done.

Impurity doping through ion implantation is performed as shown by the arrow of FIG. 1 to increase conductivity in the polysilicon forming the gate pattern 50. At this time, the ion implantation is performed so that all regions of the polysilicon layer can serve as conductors. For example, when the polysilicon layer has a thickness of 2000-3000A (angstrom), boron is implanted in the P-type impurity. In the case of dosing 4 * 10 ¹⁵ atoms / cm ² and N-type impurity implantation, ion implantation is performed with arsenic (As) and phosphorus (P) at about 60 to 70 KeV and 20 to 30 KeV, respectively.

However, when the width of the device isolation layer 10 is narrow and not deep, when the voltage V is applied to the gate pattern 50 as shown in FIG. 3 in the completed semiconductor device, the gate voltage is below the device isolation layer 10. Affects the junction between heterogeneous impurity wells. Therefore, a channel, such as a channel formed under the gate insulating layer of the MOS transistor, is formed under the device isolation layer 10, and there is a problem that leakage current flows according to the voltage applied state of each well and the gate.

In order to prevent leakage currents below the device isolation layer, a method of increasing the junction barrier or increasing the depth and width of the device isolation layer by adjusting the impurity concentration of each well may be considered. Is often not easily changed by other factors, and there is a limit to the range. Therefore, a separate method for preventing leakage current under the device isolation layer is required.

The present invention is to solve the problem of the leakage current flows down the device isolation layer in the conventional semiconductor device described above, the applied gate voltage affects below the device isolation layer without changing the existing device isolation depth or well impurity concentration. An object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which can prevent the phenomenon of forming a channel under the device isolation film.

In the CMOS semiconductor device of the present invention for achieving the above object, the width of the gate pattern is wider than that of other portions at portions passing through device isolation layers between different impurity wells, and only the upper layer portion of the gate patterns is formed at portions having an enlarged width. The impurities may be doped or may pass through the device isolation layer between different impurity wells so that only the upper portion of the gate pattern is doped with impurities and the impurity concentration of the upper portion is higher.

In the present invention, the doped thickness may be about 1/2 to 1/4 of the gate pattern thickness. If the undoped layer is less than 1/2 of the thickness of the gate pattern, it is difficult to sufficiently expect the effect of the applied potential drop at the bottom of the isolation layer according to the present invention, and the thickness of the undoped layer exceeds 3/4 in the thickness of the gate pattern. It is difficult to expect accuracy in the process, and even if the gate pattern width-expanded portion is slightly out of position, a voltage drop may be seriously formed while following the gate pattern by forming an obstacle of the conductive layer between the other gate pattern portions.

According to the present invention, a method of manufacturing a CMOS semiconductor device includes forming an isolation layer, forming an N-type well and a P-type well on both sides of a center of a portion of an isolation layer, and forming a gate insulating layer and a polysilicon gate layer. A method of producing a CMOS semiconductor device, comprising the steps of: forming, implanting an ion into a polysilicon gate layer, and patterning a polysilicon gate layer to form a gate pattern;

Prior to the ion implantation into the polysilicon gate layer, a step of forming an ion implantation prevention layer to cover the region in which the gate pattern crosses a predetermined portion of the device isolation layer first, and the ion implantation step It is characterized in that the made in the state where the ion implantation prevention film.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

4 and 5 show that the photoresist pattern 110 is formed on the portion of the device isolation film 10 between the N well 20 and the P well 30 in the method of the present invention, and the other portions are exposed in the conventional manner. Process sectional drawing and top view which show the step of performing an ion implantation with the same ion implantation energy and dose amount.

Referring to one embodiment of a process for forming such a semiconductor device, first, a trench type isolation layer 10 is formed on a substrate 100. The trench isolation layer 10 forms a trench on the substrate using photolithography, fills the trench with silicon oxide film by chemical vapor deposition on the entire surface of the substrate on which the trench is formed, and the oxide layer stacked around the trench is a CMP process or an etch back. The process of removing through the process can be formed as a basic step.

Subsequently, an N-type well WELL and a P-type well WELL are formed based on the device isolation layer 10. The well formation process is formed by a conventional method through an exposure process and an ion implantation process. For example, the N well 20 region is covered with a photoresist pattern, P-type ion implantation is performed in the open region, the photoresist pattern is removed, and the P well 30 region is covered with a photoresist pattern, and the N-type ion implantation is performed. Will be implemented.

A gate insulating film 40 is formed on the substrate on which the trench type isolation layer 10 and the well are formed, and a polysilicon layer is formed by full chemical vapor deposition. A polysilicon layer gate pattern 50 is formed in the patterning process through photolithography. At this time, as can be seen in FIG. 5, the gate pattern 50 has the gate pattern portion 151 passing over the device isolation layer 10 between the two wells wider than the gate pattern 50 passing through the two well regions. Form. Compared with the conventional art, the changed pattern may be formed by changing and patterning a photo mask in the polysilicon layer patterning process for forming the gate pattern 50.

As illustrated, ion implantation is performed on the gate pattern 50. In some cases, ion implantation is first performed on the gate layer itself, and a patterning operation for forming a gate pattern may be performed.

Ion implantation in the ion implantation step allows all regions of the polysilicon layer to serve as conductors evenly. In the case of P-type impurity implantation, when the polysilicon layer has a thickness of 2000-3000 A (angstrom), boron is implanted with 7-10 KeV of implant energy, 4 * 10 ¹⁵ atoms / cm ² , and N-type impurity implantation. In the above, ion implantation can be performed by using arsenic (As) or phosphorus (P) at about 60 to 70 KeV and 20 to 30 KeV, respectively.

However, ion implantation is not performed in the gate pattern portion 151 passing through the device isolation layer 10 between the two wells where the photoresist pattern 110 serves as the ion implantation prevention layer, or the photoresist pattern 110 is formed. Adjust the thickness of the ion implantation is made only in the upper part. On the other hand, although the ion implantation is shown in the well region, the N well 20 region, the P well 30 region or all the well regions are protected by the photoresist pattern 110 according to the nature of the ion implantation. Ion implantation may be performed while only the pattern 50 is exposed.

6 and 7 remove the photoresist pattern formed on the device isolation layer in the next step of FIGS. 4 and 5, form an ion implantation mask with a new photoresist pattern, and implant ion into the gate pattern portion on the device isolation layer. It is sectional drawing and top view which show the step of implementing.

In this step, an ion implantation mask (ion implantation prevention layer) pattern 120 is formed of a photoresist that newly exposes only the device isolation layer portion between the two wells through an exposure process. There is little change in dose, and only the ion implantation energy is weakened to perform ion implantation. For example, when impurity implantation is performed only in the upper half of the polysilicon layer on which the gate pattern 150 is to be formed, the ion implantation energy is about 1/2 compared with the step of FIG.

The polysilicon layer is similar to the insulating layer because the conductivity is significantly weakened where no impurity is injected. Therefore, when the upper portion of the isolation layer is crossed, the upper layer of the polysilicon gate pattern at the overlapping portion may simply be regarded as an insulator.

If the width of the gate pattern portion 151 across the device isolation layer is doubled, even though current may flow only in the upper layer 1511 in this portion, the area of the conductor portion is the same along the entire gate pattern, so that voltage is applied through the gate pattern. There is no bottleneck, and there is little problem of voltage drop.

As a result, it can be considered that the lower layer 1513 corresponding to 1/2 of the thickness of the gate pattern portion 151 in the portion crossing the device isolation layer is changed into an insulating layer, and an insulating layer below the gate pattern as compared with the conventional case. It can be seen that it has increased by half the thickness of the gate pattern. The same voltage V is applied to the conductor layer of the upper layer 1511 of the gate pattern, and the voltage applied corresponding to the non-conductor gradually decreases from the lower layer 1513 of the gate pattern to the lower side of the device isolation layer. If the threshold voltage at the impurity junction below the device isolation layer is Vr, the same V voltage is applied to both the upper and lower layers of the gate pattern 50 in the case of FIG. 3, and the potential decreases from the top of the device isolation layer 10. As a result, a threshold voltage Vr is applied below the bottom of the device isolation layer 10. Therefore, it can be seen that a voltage higher than the threshold voltage Vr is applied to the bottom of the device isolation layer. On the other hand, in the present embodiment, as shown in FIG. 8, all of the upper layers 1511 of the gate pattern 150 have the same voltage V applied thereto, and the potential is decreased from the middle of the thickness at which the lower layer 1513 of the gate pattern starts. (10) The part with threshold voltage Vr potential appears before reaching the bottom. Therefore, in this embodiment, a potential lower than the threshold voltage Vr is applied to the bottom of the device isolation layer so that the charge carriers cannot flow beyond the impurity junction. In other words, the leakage current cannot flow.

In FIG. 6, the photoresist ion implantation prevention layer is formed only on the device isolation layer between the two wells. However, the low energy ion implantation is performed without the ion implantation prevention layer being formed, and only the gate pattern is exposed by the ion implantation prevention layer. It is also possible to perform ion implantation in the state of making.

The above embodiment illustrates a case in which the width of the gate pattern is enlarged at a position crossing the device isolation layer. However, in some cases, instead of enlarging the width of the gate pattern, a relatively high dose (at a low energy ion implantation rate) may be obtained. It is also possible to use a method of compensating the gate pattern conductivity of the upper region of the device isolation layer by increasing the impurity concentration of the upper portion of the gate pattern by implanting ions in a dose).

According to the present invention, the problem of leakage current flowing in spite of impurity ion implantation under the element separator overlapping the gate pattern in the conventional CMOS type semiconductor device can be solved in a certain range.

According to the present invention, the applied gate voltage affects the bottom of the device isolation layer without changing the depth of the device isolation layer or the well impurity concentration, and does not change the voltage applied to the gate pattern, thereby forming a channel under the device isolation layer. Can be prevented. Therefore, in order to prevent leakage current, the leakage current may be blocked without changing the well impurity concentration in the existing semiconductor device design, changing the width and depth of forming the isolation layer, and changing the gate voltage.

Claims (7)

In a CMOS semiconductor device comprising a substrate formed device isolation film and a different impurity well formed between the device isolation film, and the different impurity well and one polysilicon gate pattern across the device isolation film, Impurities are implanted under the device isolation layer of the substrate to form a junction; The width of the portion across the device isolation layer of the gate pattern is wider than the width of the portion across the well, At least a part of the thickness of the lower portion of the portion of the gate pattern that crosses the device isolation layer is an impurity undoped layer. The method of claim 1, And the impurity undoped layer is formed to be 1/2 or more and 3/4 or less of the thickness of the gate pattern. Forming an isolation layer on the substrate, Forming N-type wells and P-type wells on both sides of the center line of a portion of the device isolation layer; Forming a gate insulating film and a polysilicon gate layer on the substrate on which the well is formed; Performing ion implantation into the polysilicon gate layer, A method of forming a CMOS semiconductor device, comprising forming a gate pattern by patterning the polysilicon gate layer. Before forming the ion implantation into the polysilicon gate layer, a step of forming an ion implantation prevention layer covering a region in which the gate pattern crosses a predetermined portion of the device isolation layer upward; And performing said ion implantation in a state where said ion implantation prevention film is present. The method of claim 3, wherein Removing the ion implantation prevention film after the ion implantation step; And performing low energy ion implantation into the polysilicon gate layer. The method of claim 4, wherein After removing the ion implantation prevention film, prior to performing the low energy ion implantation, forming a low energy ion implantation prevention film covering a region in which the gate pattern crosses a predetermined portion of the device isolation layer. A method for producing a CMOS semiconductor device, characterized in that. The method of claim 5, And in the low energy ion implantation step, ion implantation with a larger dose than the ion implantation dose in the ion implantation step. The method of claim 3, wherein The ion implantation of the polysilicon gate layer And forming a gate pattern by patterning the polysilicon gate layer.

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