CN112635549A - Super-junction MOSFET device structure and manufacturing method - Google Patents
Super-junction MOSFET device structure and manufacturing method Download PDFInfo
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Abstract
The invention relates to a super-junction MOSFET device structure and a manufacturing method, wherein a plurality of device cells with the cell size of W are arranged on a first main surface of a semiconductor substrate, a plurality of super-junction arrays arranged in an array manner are arranged in a first conductive type epitaxial layer, the widths of a first N-type column N1, a second N-type column N2, a first P-type column P1 and a second P-type column P2 in the super-junction arrays are all the same as d, the lengths of the first N-type column N1 and the first P-type column P1 are the same as L1, the lengths of the second N-type column N2 and the second P-type column P2 are the same as L2, L1 is greater than L2, L1+ L2 is equal to W, and 2d is less than or equal to W; according to the invention, through a multi-time epitaxial process method, the super-junction structure is changed, the contradiction between the size of the super-junction structure and the size of the surface MOS structure is broken, and the small size of the super-junction structure unit is completed on the premise of not increasing the difficulty of the existing process and the manufacturing cost, so that the voltage resistance of the device is improved, the on-resistance is reduced, and the on-loss of the super-junction device is further reduced.
Description
Technical Field
The invention relates to a super junction semiconductor device and a manufacturing method thereof, in particular to a super junction semiconductor device and a manufacturing method thereof, which can improve the voltage endurance and reduce the on-resistance.
Background
In the field of medium-high voltage power semiconductor devices, a Super Junction structure (Super Junction) is widely adopted, and compared with a traditional power MOSFET device, the Super Junction structure can obtain a more excellent compromise relationship between the withstand voltage and the on resistance of the device. As shown in fig. 1, a super junction structure is formed in a drift region of a semiconductor device, and the super junction structure includes N conductive type columns (N columns) and P conductive type columns (P columns), and a plurality of P-N column pairs formed by alternately adjoining N columns and P columns form the super junction structure. The N column has N conductive type impurities, the P column has P conductive type impurities, and the impurity amount of the N column is consistent with that of the P column. When the MOSFET device with the super junction structure is cut off, the N columns and the P columns in the super junction structure are respectively depleted, a depletion layer extends from a P-N junction interface between each N column and each P column, and the depletion layer extends and is almost completely depleted due to the fact that the impurity amount in the N columns is equal to the impurity amount in the P columns, and therefore the withstand voltage of the device can be improved; when the device is conducted, the same withstand voltage is kept, meanwhile, the impurity concentration of the super junction device drift region is higher, and further the resistivity is lower, so that the conduction resistance of the super junction device can be greatly reduced compared with that of a common device. Compared with a common VDMOS device, the characteristic on-resistance of the super junction MOSFET device can be reduced by about 70%.
The super junction device voltage resistance is mainly influenced by the following factors:
1) super junction structure depth (thickness);
2) the size (pitch) of a structural unit of a super junction structure in the super junction device;
3) and the impurity concentration of the drift region.
Although the withstand voltage can be provided due to the decrease in the impurity concentration of the drift region, the on-resistance of the device increases. Therefore, in order to increase the withstand voltage of the device and reduce the on-resistance of the device, the cell size is generally reduced or the depth of the super junction structure is increased;
by adopting a mode of improving the depth of the super junction structure, in an actual process, the depth-to-width ratio of the P column is increased by improving the depth of the super junction structure, the manufacturing difficulty and the manufacturing cost of a device are increased, and the depth of the super junction structure is difficult to greatly increase;
the method for reducing the cell size of the super junction structure is the most common mode in the actual products at present, and the cell size of the super junction structure refers to the sum of the width of an N column and the width of a P column. When the device is resistant to voltage, the curvature of a depletion layer at the bottom of the device can be reduced by reducing the unit size of the super junction structure, and the voltage resistance of the device is further improved. When the concentration of the drift region is increased, the device withstand voltage is reduced, but the reduction range of the device withstand voltage of a unit size with a smaller super junction structure is also smaller.
As shown in fig. 1, a structure diagram of an existing conventional MOS device with a super junction structure is shown, where an existing super junction unit is parallel to a cell unit direction of the device, an N-type column width in an existing super junction array is L1, a P-type column width is L2, a cell size of a cell unit of the MOS device is W, and W is L1+ L2, when a cell size of the super junction structure is reduced to a certain extent, a cell size of a surface MOS device also has to be sharply reduced along with a cell size of the super junction structure in a drift region; such a reduction may cause the following problems:
1. the JFET benefit between adjacent P-type body regions is increased, and the on-resistance (Rdson) of the device cannot be further reduced under the condition of the same voltage withstanding requirement;
2. the surface MOS structure is reduced due to the reduction of the size of the super junction structure unit, even the requirement of the process manufacturing can not be met, and the manufacturing difficulty and the manufacturing cost of the device are increased;
3. the actual product on-resistance (Rdson) will rise greatly because the P-pillar under the gate occupies the critical JFET area.
Based on the reasons, the super junction device structure can break through the contradiction between the size of the existing super junction structure and the size of the surface MOS structure, and is very necessary and suitable for the super-small super junction structure; meanwhile, a corresponding manufacturing method of the super junction device with the ultra-small super junction structure unit size is needed, and the super junction device with the ultra-small super junction structure unit size is manufactured on the premise of not increasing the difficulty and the manufacturing cost of the existing process.
Disclosure of Invention
The invention aims to overcome the defects in the existing super-junction MOSFET device technology, and provides a super-junction MOSFET device structure and a manufacturing method thereof.
In order to achieve the technical purpose, the technical scheme of the invention is as follows: a super junction MOSFET device structure comprises a semiconductor substrate, wherein the semiconductor substrate comprises a first conduction type substrate and a first conduction type epitaxial layer adjacent to the first conduction type substrate, the upper surface of the first conduction type epitaxial layer forms a first main surface of the semiconductor substrate, and the lower surface of the first conduction type substrate forms a second main surface of the semiconductor substrate; arranging a plurality of device cell units on a first main surface of a semiconductor substrate, wherein the size of each device cell unit is W; the method is characterized in that: arranging a plurality of super-junction arrays in the first conductive type epitaxial layer, wherein the super-junction arrays are formed by arranging first conductive type columns and second conductive type columns in an array manner, the peripheries of the first conductive type columns are adjacent to the second conductive type columns, the peripheries of the second conductive type columns are adjacent to the first conductive type columns, and the first conductive type columns and the second conductive type columns in the super-junction arrays extend from the first main surface to the second main surface in the first conductive type epitaxial layer along the direction from the first main surface; the first conductive type columns in the super junction array comprise a first conductive type column n1 and a second first conductive type column n2, the second conductive type columns comprise a first second conductive type column p1 and a second conductive type column p2, the first conductive type column n1, the second first conductive type column n2, the first second conductive type column p1 and the second conductive type column p2 are d in width, the first conductive type column n1 and the first second conductive type column p1 are L1 in length, the second first conductive type column n2 and the second conductive type column p2 are L2 in length, and L1> L2, L1+ L2 is W2 d ≦ W2.
The semiconductor device further comprises a second conduction type body region positioned in the first conduction type epitaxial layer, a first conduction type source region positioned in the second conduction type body region, a gate oxide layer positioned on the first main surface and gate conductive polycrystalline silicon positioned on the gate oxide layer;
the first conductive type column n1 and the first second conductive type column p1 in the super junction array are both located below the gate conductive polysilicon, the second first conductive type column n2 and the second conductive type column p2 are both located below the second conductive type body region, and each of the first second conductive type column p1 and the second conductive type column p2 is in contact with the second conductive type body region above the first conductive type column p1 and the second conductive type column p 2.
The semiconductor device further comprises a source metal positioned on the front surface of the device, a gate metal separated from the source metal, and a drain metal positioned on the back surface of the device, wherein the source metal is in ohmic contact with the second conductive type body region and the first conductive type source region respectively, the gate metal is in ohmic contact with the gate conductive polysilicon, and the drain metal is in ohmic contact with the second main surface of the semiconductor substrate; the source metal is isolated from the grid conductive polycrystal through an insulating medium layer.
In order to further achieve the technical purpose, the invention further provides a manufacturing method of the super junction MOSFET device structure, which is characterized by comprising the following steps:
(a) selecting a first conductive type silicon substrate as a first conductive type substrate, and growing a first conductive type epitaxial layer on the upper surface of the first conductive type substrate by adopting an epitaxial process;
(b) depositing a hard mask layer on the first conduction type epitaxial layer, and selectively masking and etching the hard mask layer to form a plurality of hard mask first windows and hard mask second windows for masking;
(c) implanting impurity ions of a second conduction type through shielding of the hard mask window, obtaining a first and second conduction type layer which is not diffused in the first conduction type epitaxial layer, and removing the hard mask window;
(d) continuously growing a second first conductive type epitaxial layer on the surface of the first conductive type epitaxial layer;
(e) implanting impurity ions of a second conduction type through the shielding of the hard mask window, obtaining a second non-diffused conduction type layer in the second first conduction type epitaxial layer, and removing the hard mask window;
(f) repeating the step (d) and the step (e) for three times, sequentially forming a third first conduction type epitaxial layer, a fourth first conduction type epitaxial layer and a fifth first conduction type epitaxial layer on the second first conduction type epitaxial layer, and finally growing a top first conduction type epitaxial layer to finish the manufacture of the first conduction type epitaxial layer;
simultaneously, a third second conduction type layer, a fourth second conduction type layer and a fifth second conduction type layer are respectively formed in the third first conduction type epitaxial layer, the fourth first conduction type epitaxial layer and the fifth first conduction type epitaxial layer;
(g) carrying out high-temperature annealing on the first conduction type epitaxial layer, and connecting the first second conduction type layer, the third second conduction type layer, the fourth second conduction type layer and the fifth second conduction type layer after diffusion, so that a super-junction array with first conduction type columns and second conduction type columns arranged in an array mode is formed in the first conduction type epitaxial layer, the peripheries of the first conduction type columns are adjacent to the second conduction type columns, the peripheries of the second conduction type columns are adjacent to the first conduction type columns, and the manufacture of the super-junction structure is completed;
(h) thermally growing an oxide layer on the first conductive type epitaxial layer, depositing conductive polycrystalline silicon on the oxide layer, and selectively etching the conductive polycrystalline silicon and the oxide layer in sequence to obtain a gate oxide layer and gate conductive polycrystalline silicon on the gate oxide layer;
(i) under the shielding of the grid conductive polycrystalline silicon, injecting second conductive type impurities in a self-alignment manner, annealing at high temperature, forming a second conductive type body region above the super junction array, and then selectively injecting first conductive type impurities to form a first conductive type source region in the second conductive type body region;
(j) depositing an insulating medium layer on the upper surface of the device, selectively etching the insulating medium layer, and forming a metal contact through hole;
(k) depositing metal in the metal contact through hole, and etching the metal to obtain source metal and grid metal, thereby completing the manufacture of the MOS device unit cell;
(l) And forming drain metal on the lower surface of the first conduction type substrate to finish the manufacture of the super junction MOSFET device structure.
Furthermore, the plurality of hard mask first windows and the plurality of hard mask second windows are distributed in a spaced array;
in step (b), the width of the hard mask first window is d, the length of the hard mask first window is L1, the width of the hard mask second window is d, the length of the hard mask second window is L2, L1> L2, L1+ L2 is W, and 2d is not more than W.
Further, in the step (g), the first conductive type pillars in the super junction array include a first conductive type pillar n1 and a second first conductive type pillar n2, the second conductive type pillars include a first second conductive type pillar P1 and a second conductive type pillar P2, the widths of the first conductive type pillar n1, the second first conductive type pillar n2, the first P-type pillar P1 and the second P-type pillar P2 are all the same as d, the lengths of the first conductive type pillar n1 and the first P-type pillar P1 are the same as L1, the lengths of the second first conductive type pillar n2 and the second P-type pillar P2 are the same as L2, and L1> L2, L1+ L2 is equal to W2 d or less.
Further, the first and second conductive type pillars p1 and p2 are implanted through hard mask first and second windows respectively.
Further, for a first conductivity type super junction MOSFET device, the first conductivity type is N-type conductivity, and the second conductivity type is P-type conductivity; for a P-type super junction MOSFET device, the first conductivity type is P-type conductivity and the second conductivity type is N-type conductivity.
Further, the super junction MOSFET device is a MOS device or an IGBT device.
As can be seen from the above description, the beneficial effects of the present invention are:
1) on the basis of the original super-junction cell unit (the original super-junction cell unit is parallel to the direction of the device cell unit, the sizes of the super-junction cell unit and the device cell unit are the same, and W is L1+ L2), a plurality of super-junction cell units smaller than the size of the device cell unit are added in the vertical direction of the device cell unit, so that the periphery of an N-type column is adjacent to a P-type column, the periphery of the P-type column is adjacent to the N-type column, the cell size (d + d) of the super-junction cell in the vertical direction of the device cell is smaller than the cell size W of the device cell (namely 2d is less than or equal to W), the problem that the cell size of the super-junction structure in the semiconductor device is limited by the cell size of the device cell is solved, the cell size of the super junction array can be greatly reduced on the premise of not changing the cell size of a device, the number of super junction units in a super junction structure is increased, and the withstand voltage is further improved;
2) the principle of the super junction device structure for improving withstand voltage is that the periphery of an N-type column is adjacent to a P-type column, the periphery of the P-type column is adjacent to the N-type column, the widths of the N-type column and the P-type column are the same and are d, meanwhile, the length of a first N-type column N1 and the length of a first P-type column P1 are the same and are L1, the length of a second N-type column N2 and the length of a second P-type column P2 are the same and are L2, and the impurity ion concentrations of the N-type column and the P-type column are the same, so that compared with the original structure, when the device is in withstand voltage, a super junction array in the whole N-type epitaxial layer can be gradually and completely exhausted, therefore, the withstand voltage capability of the device can be improved, under the same withstand voltage condition, the resistivity of the device epitaxial layer can be smaller, the on-resistance of the device can be further reduced;
3) according to the super junction MOSFET structure, under the condition that the size of a cell unit of a device is not reduced or even increased, the size of the super junction structure unit can be reduced, so that the JFET benefit between adjacent P-type body regions is weakened, and the on-resistance (Rdson) of the device is further reduced;
4) the process manufacturing method is compatible with the existing widely used semiconductor manufacturing technology, does not increase the manufacturing difficulty and the manufacturing cost, and is beneficial to popularization and batch production.
Drawings
Fig. 1 is a schematic diagram of a super junction MOSFET structure in the prior art.
Fig. 2 is a schematic diagram of a super junction MOSFET structure according to embodiment 1 of the present invention.
Fig. 3 is a schematic diagram of a super junction MOSFET structure according to embodiment 1 of the present invention.
Fig. 4 is a schematic structural view of an N-type substrate of embodiment 1 of the present invention.
Fig. 5 is a schematic structural view of a hard mask layer in embodiment 1 of the present invention.
Fig. 6 is a schematic structural view of forming a first N-type epitaxial layer and a first P-type layer in embodiment 1 of the present invention.
Fig. 7 is a schematic structural view of forming a second N-type epitaxial layer and a second P-type layer in embodiment 1 of the present invention.
Fig. 8 is a schematic structural view of forming a third N-type epitaxial layer and a third P-type layer in embodiment 1 of the present invention.
Fig. 9 is a schematic structural view of forming a fourth N-type epitaxial layer and a fourth P-type layer in embodiment 1 of the present invention.
Fig. 10 is a schematic structural view of forming a fifth N-type epitaxial layer and a fifth P-type layer in embodiment 1 of the present invention.
Fig. 11 is a schematic structural view of forming a top N-type epitaxial layer in embodiment 1 of the present invention.
Fig. 12 is a schematic top-view structural diagram of forming a super junction array according to embodiment 1 of the present invention.
FIG. 13 is a schematic sectional view showing A-A in FIG. 12 according to embodiment 1 of the present invention.
FIG. 14 is a schematic sectional view showing B-B in FIG. 12 according to embodiment 1 of the present invention.
Fig. 15 is a schematic structural view of a planar gate type MOS device cell formed in embodiment 1 of the present invention.
Description of reference numerals: 001 — first major face; 002 — second major face; 1-N type substrate; 2-N type epitaxial layer; 21-a first N-type epitaxial layer; 22-a second N-type epitaxial layer; 23-a third N-type epitaxial layer; 24-fourth N-type epitaxial layer; 25-fifth N type epitaxial layer; 26-top N-type epitaxial layer; 3-P-type body region; 4-N-type source region; 5-a gate oxide layer; 6-grid conductive polysilicon; 7-insulating medium layer; 8-source metal; 9-drain metal; 10-a hard mask layer; 101 — a hard mask first window; 102 — a hard mask second window; 11-gate metal; 12-the first P type layer, 13-the second P type layer, 14-the third P type layer, 15-the fourth P type layer, 16-the fifth P type layer.
Detailed Description
The invention is further illustrated by the following specific figures and examples.
For an N-type super junction semiconductor device, the first conductivity type is N-type conductivity, and the second conductivity type is P-type conductivity; for a P-type super junction semiconductor device, the first conductivity type is P-type conductivity and the second conductivity type is N-type conductivity.
Example 1: taking an N-type planar gate super junction MOSFET device as an example;
as shown in fig. 2 and fig. 3, a super junction MOSFET device structure comprises a semiconductor substrate, wherein the semiconductor substrate comprises an N-type substrate 1 and an N-type epitaxial layer 2 adjacent to the N-type substrate 1, the upper surface of the N-type epitaxial layer 2 forms a first main surface 001 of the semiconductor substrate, and the lower surface of the N-type substrate 1 forms a second main surface 002 of the semiconductor substrate; arranging a plurality of device cell units on a first main surface 001 of a semiconductor substrate, wherein the size of each device cell unit is W;
a plurality of super-junction arrays which are formed by arranging N-type columns and P-type columns in an array mode are arranged in the N-type epitaxial layer 2, the peripheries of the N-type columns are all adjacent to the P-type columns, the peripheries of the P-type columns are all adjacent to the N-type columns, and the N-type columns and the P-type columns in the super-junction arrays extend from the first main surface 001 to the second main surface 002 along the direction from the first main surface 001 in the N-type epitaxial layer; the N-type columns in the super junction array comprise a first N-type column N1 and a second N-type column N2, the P-type columns comprise a first P-type column P1 and a second P-type column P2, the widths of the first N-type column N1, the second N-type column N2, the first P-type column P1 and the second P-type column P2 are all the same and are d, the lengths of the first N-type column N1 and the first P-type column P1 are the same and are L1, the lengths of the second N-type column N2 and the second P-type column P2 are the same and are L2, L1> L2, L1+ L2 is W, and 2d is not more than W.
The N-type planar gate MOSFET device further comprises a P-type body region 3 positioned in the N-type epitaxial layer 2, an N-type source region 4 positioned in the P-type body region 3, a gate oxide layer 5 positioned on the first main surface 001, and gate conductive polycrystalline silicon 6 positioned on the gate oxide layer 5;
the semiconductor device further comprises a source metal 8 positioned on the front surface of the device, a gate metal 11 separated from the source metal 8, and a drain metal 9 positioned on the back surface of the device, wherein the source metal 8 is in ohmic contact with the P-type body region 3 and the N-type source region 4 respectively, the gate metal 11 is in ohmic contact with the gate conductive polysilicon 6, and the drain metal 9 is in ohmic contact with the N-type substrate 1; the source metal 8 is isolated from the gate conductive polysilicon 6 by an insulating dielectric layer 7, which is well known by those skilled in the art and is not described again;
a first N-type column N1 and a first P-type column P1 in the super junction array are both located below the gate conductive polysilicon 6, a second N-type column N2 and a second P-type column P2 are both located below the P-type body region 3, and each of the first P-type column P1 and the second P-type column P2 is in contact with the P-type body region 3 above the first P-type column P1 and the second P-type column P2;
The super junction MOSFET device structure of the embodiment 1 can be prepared by the following process steps, and specifically, the manufacturing method comprises the following steps:
as shown in fig. 4, (a), selecting an N-type silicon substrate as an N-type substrate 1, and growing a first N-type epitaxial layer 21 on the upper surface of the N-type substrate 1 by using an epitaxial process;
as shown in fig. 5, (b), depositing a hard mask layer 10 on the first N-type epitaxial layer 21, selectively masking and etching the hard mask layer 10 to form a plurality of hard mask first windows 101 and hard mask second windows 102 for masking, wherein the plurality of hard mask first windows 101 and the plurality of hard mask second windows 102 are distributed in a spaced array;
the hard mask first window 101 has a width d and a length L1, and the hard mask second window 102 has a width d and a length L2;
as shown in fig. 6, (c), under the shielding of the hard mask window (including the hard mask first window 101 and the hard mask second window 102), implanting P-type impurity ions to obtain the first P-type layer 12 without diffusion in the first N-type epitaxial layer 21, and removing the hard mask window;
as shown in fig. 7, (d), a second N-type epitaxial layer 22 continues to grow on the surface of the first N-type epitaxial layer 21;
(e) implanting P-type impurity ions through the shielding of the hard mask window to obtain a second P-type layer 13 which is not diffused in the second N-type epitaxial layer 22, and removing the hard mask window;
as shown in fig. 8 to 11, (f), repeating (d) and (e) three times, sequentially forming a third N-type epitaxial layer 23, a fourth N-type epitaxial layer 24 and a fifth N-type epitaxial layer 25 on the second N-type epitaxial layer 22, and finally, growing a top N-type epitaxial layer 26 again to complete the fabrication of the N-type epitaxial layer 2;
meanwhile, a third P-type layer 14, a fourth P-type layer 15 and a fifth P-type layer 16 are respectively formed in the third N-type epitaxial layer 23, the fourth N-type epitaxial layer 24 and the fifth N-type epitaxial layer 25;
as shown in fig. 12, (g) performing high-temperature annealing on the N-type epitaxial layer 2, and after the first P-type layer 12, the second P-type layer 13, the third P-type layer 14, the fourth P-type layer 15, and the fifth P-type layer 16 are diffused in the N-type epitaxial layer 2 and then connected together, forming a super-junction array in which N-type columns and P-type columns are arranged in an array, wherein the peripheries of the N-type columns are adjacent to the P-type columns, and the peripheries of the P-type columns are adjacent to the N-type columns, thereby completing the manufacture of the super-junction array;
as shown in fig. 13 and fig. 14, which are a sectional view a-a and a sectional view B-B of fig. 12, respectively, the N-type pillars in the superjunction array include a first N-type pillar N1 and a second N-type pillar N2, the P-type pillars include a first P-type pillar P1 and a second P-type pillar P2, the widths of the first N-type pillar N1, the second N-type pillar N2, the first P-type pillar P1 and the second P-type pillar P2 are all the same as d, the lengths of the first N-type pillar N1 and the first P-type pillar P1 are the same as L1, the lengths of the second N-type pillar N2 and the second P-type pillar P2 are the same as L2, and L1> L2, L1+ L2 is W, 2d ≦ W;
the first P-type pillar P1 is obtained by implantation through a first hard mask window 101 and high-temperature annealing, and the second P-type pillar P2 is obtained by implantation through a second hard mask window 102 and high-temperature annealing;
as shown in fig. 15, (h) thermally growing an oxide layer on the N-type epitaxial layer 2, depositing conductive polysilicon on the oxide layer, and selectively etching the conductive polysilicon and the oxide layer in sequence to obtain a gate oxide layer 5 and a gate conductive polysilicon 6 on the gate oxide layer 5;
(i) under the shielding of the gate conductive polysilicon 6, injecting P-type impurities in a self-aligned manner, annealing at a high temperature, forming a P-type body region 3 above the second N-type column N2 and the second P-type column P2, and then selectively injecting N-type impurities to form an N-type source region 4 in the P-type body region 3;
(j) depositing an insulating medium layer 7 on the upper surface of the device, selectively etching the insulating medium layer 7 to form a metal contact through hole;
as shown in fig. 2 and fig. 3, (k) depositing metal in the metal contact via, and etching the metal to obtain a source metal 9 and a gate metal 11, and forming a drain metal 9 on the lower surface of the N-type substrate 1 to complete the fabrication of the planar gate super junction MOSFET device;
fig. 2 is a planar gate super junction MOSFET corresponding to fig. 13, and fig. 3 is a planar gate super junction MOSFET corresponding to fig. 14.
The embodiment of the invention is not only suitable for a plane gate type super junction semiconductor device, but also suitable for a groove gate type super junction semiconductor device, and is not only suitable for an MOS device, but also suitable for an IGBT device.
The super-junction array is characterized in that on the basis of an original super-junction unit (the existing super-junction unit is parallel to a device cell unit direction, the width of an N-type column in the existing super-junction array is L1, the width of a P-type column is L2, the length of the P-type column is the same, the size of the device cell unit is W, and W is L1+ L2), a plurality of super-junction units are added in the vertical direction of the device cell, so that the periphery of the N-type column is adjacent to the P-type column, the periphery of the P-type column is adjacent to the N-type column, as shown in FIG. 12, the periphery of the first N-type column N1 is adjacent to a first P-type column P1 and a second P-type column P2 respectively, the periphery of the second N-type column N2 is adjacent to a first P-type column P1 and a second P-type column P2 respectively, the periphery of the first P-type column P1 is adjacent to a first N-type column N1 and a second N-type column N2 and a second P45 are adjacent to a second N-type column P8236, and the size of the super-type cell unit is smaller than the size of the device cell unit in the vertical direction (2 d) W is less than or equal to W), the problem that the unit size of the super junction structure in the semiconductor device is limited by the unit size of the device cell is solved, the unit size of the super junction array can be greatly reduced on the premise of not changing the device cell, the number of the super junction units in the super junction structure is increased, and the withstand voltage of the device is further improved;
because the periphery of the N-type column is adjacent to the P-type column, the periphery of the P-type column is adjacent to the N-type column, the first N-type column N1 and the first P-type column P1 are L1 in the same length, the second N-type column N2 and the second P-type column P2 are L2 in the same length, and the impurity ion concentrations of the N-type column and the P-type column are the same, compared with the original super junction device, when the device is voltage-resistant, the whole super junction array can be gradually and completely depleted, and the depletion is more thorough, so the voltage-resistant capability of the device is improved, the resistivity of an epitaxial layer of the device can be reduced, the on-resistance is reduced, the on-resistance loss of the device is reduced, and a powerful basis is provided for further miniaturization of the device;
the super junction structure can increase the number of super junction units in the super junction array without reducing MOS device cellular units, thereby weakening the JFET benefit between P type body regions 3 and further reducing the on-resistance and on-loss of the device on the basis of not reducing the voltage resistance of the device and even increasing the voltage resistance of the device.
The present invention and its embodiments have been described above, and the description is not intended to be limiting, and the drawings are only one embodiment of the present invention, and the actual configuration is not limited thereto. In summary, those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for carrying out the same purposes of the present invention without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A super junction MOSFET device structure comprises a semiconductor substrate, wherein the semiconductor substrate comprises a first conduction type substrate and a first conduction type epitaxial layer adjacent to the first conduction type substrate, the upper surface of the first conduction type epitaxial layer forms a first main surface of the semiconductor substrate, and the lower surface of the first conduction type substrate forms a second main surface of the semiconductor substrate; arranging a plurality of device cell units on a first main surface of a semiconductor substrate, wherein the size of each device cell unit is W; the method is characterized in that: arranging a plurality of super-junction arrays in the first conductive type epitaxial layer, wherein the super-junction arrays are formed by arranging first conductive type columns and second conductive type columns in an array manner, the peripheries of the first conductive type columns are adjacent to the second conductive type columns, the peripheries of the second conductive type columns are adjacent to the first conductive type columns, and the first conductive type columns and the second conductive type columns in the super-junction arrays extend from the first main surface to the second main surface in the first conductive type epitaxial layer along the direction from the first main surface; the first conductive type columns in the super junction array comprise a first conductive type column n1 and a second first conductive type column n2, the second conductive type columns comprise a first second conductive type column p1 and a second conductive type column p2, the first conductive type column n1, the second first conductive type column n2, the first second conductive type column p1 and the second conductive type column p2 are d in width, the first conductive type column n1 and the first second conductive type column p1 are L1 in length, the second first conductive type column n2 and the second conductive type column p2 are L2 in length, and L1> L2, L1+ L2 is W2 d ≦ W2.
2. The superjunction MOSFET device structure of claim 1, wherein: the gate oxide layer is positioned on the first main surface, and the gate conductive polysilicon is positioned on the gate oxide layer;
the first conductive type column n1 and the first second conductive type column p1 in the super junction array are both located below the gate conductive polysilicon, the second first conductive type column n2 and the second conductive type column p2 are both located below the second conductive type body region, and each of the first second conductive type column p1 and the second conductive type column p2 is in contact with the second conductive type body region above the first conductive type column p1 and the second conductive type column p 2.
3. The superjunction MOSFET device structure of claim 2, wherein: the semiconductor substrate further comprises a source metal positioned on the front surface of the device, a gate metal separated from the source metal, and a drain metal positioned on the back surface of the device, wherein the source metal is in ohmic contact with the second conductive type body region and the first conductive type source region respectively, the gate metal is in ohmic contact with the gate conductive polysilicon, and the drain metal is in ohmic contact with the second main surface of the semiconductor substrate; the source metal is isolated from the grid conductive polycrystal through an insulating medium layer.
4. A manufacturing method of a super junction MOSFET device structure is characterized by comprising the following steps:
(a) selecting a first conductive type silicon substrate as a first conductive type substrate, and growing a first conductive type epitaxial layer on the upper surface of the first conductive type substrate by adopting an epitaxial process;
(b) depositing a hard mask layer on the first conduction type epitaxial layer, and selectively masking and etching the hard mask layer to form a plurality of hard mask first windows and hard mask second windows for masking;
(c) implanting impurity ions of a second conduction type through shielding of the hard mask window, obtaining a first and second conduction type layer which is not diffused in the first conduction type epitaxial layer, and removing the hard mask window;
(d) continuously growing a second first conductive type epitaxial layer on the upper surface of the first conductive type epitaxial layer;
(e) implanting impurity ions of a second conduction type through the shielding of the hard mask window, obtaining a second non-diffused conduction type layer in the second first conduction type epitaxial layer, and removing the hard mask window;
(f) repeating the step (d) and the step (e) for three times, sequentially forming a third first conduction type epitaxial layer, a fourth first conduction type epitaxial layer and a fifth first conduction type epitaxial layer on the second first conduction type epitaxial layer, and finally growing a top first conduction type epitaxial layer to finish the manufacture of the first conduction type epitaxial layer;
simultaneously, a third second conduction type layer, a fourth second conduction type layer and a fifth second conduction type layer are respectively formed in the third first conduction type epitaxial layer, the fourth first conduction type epitaxial layer and the fifth first conduction type epitaxial layer;
(g) carrying out high-temperature annealing on the first conduction type epitaxial layer, and connecting the first second conduction type layer, the third second conduction type layer, the fourth second conduction type layer and the fifth second conduction type layer after diffusion, so that a super-junction array with first conduction type columns and second conduction type columns arranged in an array mode is formed in the first conduction type epitaxial layer, the peripheries of the first conduction type columns are adjacent to the second conduction type columns, the peripheries of the second conduction type columns are adjacent to the first conduction type columns, and the manufacture of the super-junction structure is completed;
(h) thermally growing an oxide layer on the first conductive type epitaxial layer, depositing conductive polycrystalline silicon on the oxide layer, and selectively etching the conductive polycrystalline silicon and the oxide layer in sequence to obtain a gate oxide layer and gate conductive polycrystalline silicon on the gate oxide layer;
(i) under the shielding of the grid conductive polycrystalline silicon, injecting second conductive type impurities in a self-alignment manner, annealing at high temperature, forming a second conductive type body region above the super junction array, and then selectively injecting first conductive type impurities to form a first conductive type source region in the second conductive type body region;
(j) depositing an insulating medium layer on the upper surface of the device, selectively etching the insulating medium layer, and forming a metal contact through hole;
(k) depositing metal in the metal contact through hole, and etching the metal to obtain source metal and grid metal, thereby completing the manufacture of the MOS device unit cell;
(l) And forming drain metal on the lower surface of the first conduction type substrate 2 to finish the manufacture of the super junction MOSFET device structure.
5. The method of claim 4, wherein in step (b), the width of the first window of the hard mask is d and the length of the first window of the hard mask is L1, the width of the second window of the hard mask is d and the length of the second window of the hard mask is L2, L1> L2, L1+ L2 is W, and 2d is less than or equal to W.
6. The method of claim 4, wherein in step (b), the plurality of first hard mask windows and the plurality of second hard mask windows are spaced in an array.
7. The method of claim 4, wherein in step (g), the first conductive type column in the super junction array comprises a first conductive type column n1 and a second first conductive type column n2, the second conductive type column comprises a first second conductive type column P1 and a second conductive type column P2, the first conductive type column n1, the second first conductive type column n2, the first P-type column P1 and the second P-type column P2 have the same width d, the first conductive type column n1 and the first P-type column P1 have the same length L1, the second first conductive type column n2 and the second conductive type column P2 have the same length L2, and L1> L2, L + 582, W2.
8. The method of claim 7, wherein the first second conductivity type pillar p1 is formed by a hard mask first window implant, and wherein the second conductivity type pillar p2 is formed by a hard mask second window implant.
9. The super junction MOSFET device structure and manufacturing method of claim 1 or 4, wherein: for a first conductivity type super junction MOSFET device, the first conductivity type is N-type conductivity and the second conductivity type is P-type conductivity; for a P-type super junction MOSFET device, the first conductivity type is P-type conductivity and the second conductivity type is N-type conductivity.
10. The super junction MOSFET device structure and manufacturing method of claim 1 or 4, wherein: the super junction MOSFET device is an MOS device or an IGBT device.
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| US20070132012A1 (en) * | 2005-11-30 | 2007-06-14 | Kabushiki Kaisha Toshiba | Semiconductor device |
| CN102270663A (en) * | 2011-07-26 | 2011-12-07 | 无锡新洁能功率半导体有限公司 | Planar power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with super junction structure and manufacturing method of planar power MOSFET device |
| CN105006484A (en) * | 2015-06-12 | 2015-10-28 | 无锡新洁能股份有限公司 | Super-junction semiconductor device and manufacture method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070132012A1 (en) * | 2005-11-30 | 2007-06-14 | Kabushiki Kaisha Toshiba | Semiconductor device |
| CN102270663A (en) * | 2011-07-26 | 2011-12-07 | 无锡新洁能功率半导体有限公司 | Planar power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with super junction structure and manufacturing method of planar power MOSFET device |
| CN105006484A (en) * | 2015-06-12 | 2015-10-28 | 无锡新洁能股份有限公司 | Super-junction semiconductor device and manufacture method thereof |
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