CN117497408B - HK-IGBT, preparation method thereof and chip - Google Patents
HK-IGBT, preparation method thereof and chip Download PDFInfo
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- CN117497408B CN117497408B CN202311833825.7A CN202311833825A CN117497408B CN 117497408 B CN117497408 B CN 117497408B CN 202311833825 A CN202311833825 A CN 202311833825A CN 117497408 B CN117497408 B CN 117497408B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 16
- 150000002500 ions Chemical class 0.000 claims description 62
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 46
- 229920005591 polysilicon Polymers 0.000 claims description 46
- 230000004888 barrier function Effects 0.000 claims description 30
- 239000002019 doping agent Substances 0.000 claims description 23
- 239000003989 dielectric material Substances 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 21
- 238000000151 deposition Methods 0.000 claims description 19
- 238000002513 implantation Methods 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 238000005468 ion implantation Methods 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims 7
- 239000000463 material Substances 0.000 description 18
- 229910052581 Si3N4 Inorganic materials 0.000 description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 230000005684 electric field Effects 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- 238000009826 distribution Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000013329 compounding Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The application belongs to the technical field of power devices, and provides an HK-IGBT, a preparation method thereof and a chip thereof.
Description
Technical Field
The application belongs to the technical field of power devices, and particularly relates to an HK-IGBT, a preparation method thereof and a chip.
Background
The insulated gate bipolar transistor (Insulate-Gate Bipolar Transistor, IGBT) is a device formed by compounding an insulated gate field effect transistor and a bipolar triode, has the characteristics of small driving power and high switching speed of a metal-oxide-Semiconductor Field-Effect Transistor (MOSFET), has the characteristic of high capacity due to reduced saturation voltage of the bipolar device, has the frequency characteristic between the MOSFET and a power transistor, can normally work in a frequency range of tens of kHz, is a main device of medium and small power electronic equipment, and is widely applied to the fields of frequency converters, lighting circuits, switching power supplies and the like.
However, since the IGBT is a bipolar device, electrons and holes are both involved in conduction during turn-on, in the current IGBT device, at turn-off instant, electrons can be quickly pumped away from the channel, and holes can be slowly cleared away only by recombination, thus causing an obvious tailing current, and there is a problem that turn-off loss of the IGBT is large.
Disclosure of Invention
In order to solve the technical problems, the embodiment of the application provides an HK-IGBT, a preparation method thereof and a chip, which can solve the problem of high turn-off loss of the traditional IGBT.
The first aspect of the embodiment of the application provides a preparation method of an HK-IGBT, which comprises the following steps:
injecting N-type doping ions into the front surface of the silicon substrate to form a potential cut-off layer;
epitaxially depositing a silicon layer on the potential cut-off layer, and forming an N-type drift layer, a hole barrier layer and a P-type well region through a plurality of ion implantation processes;
Injecting N-type doping ions and P-type doping ions into a first preset region and a second preset region on the P-type well region respectively to form a first P-type heavily doped region, a first N-type heavily doped region and a second N-type heavily doped region; the first P type heavily doped region is positioned between the first N type heavily doped region and the second N type heavily doped region;
Etching a third preset region and a fourth preset region on the P-type well region to form a first deep groove and a second deep groove, and depositing dielectric materials with high dielectric constants in the first deep groove and the second deep groove to form a first high-K dielectric layer and a second high-K dielectric layer; the first deep groove is in contact with the first N-type heavily doped region, and the second deep groove is in contact with the second N-type heavily doped region;
Forming a first grid dielectric layer on the inner wall of the first deep groove, and forming a second grid dielectric layer on the inner wall of the second deep groove;
Forming a first polysilicon layer in the first deep groove, forming a second polysilicon layer in the second deep groove, and continuing depositing a gate dielectric material, so that the first gate dielectric layer wraps the first polysilicon layer, and the second gate dielectric layer wraps the second polysilicon layer;
injecting P-type doping ions into the back of the silicon substrate to form a P-type collector region;
And forming an emitter electrode in contact with the first P-type heavily doped region, the first N-type heavily doped region and the second N-type heavily doped region, forming a collector electrode in contact with the P-type collector region, and forming a first grid electrode in contact with the first polysilicon layer and a second grid electrode in contact with the second polysilicon layer.
In one embodiment, the method of preparing further comprises:
Forming a first P-type shielding layer at the bottom of the first deep groove before depositing a dielectric material with a high dielectric constant in the first deep groove;
and before a dielectric material with high dielectric constant is deposited in the second deep groove, forming a second P-type shielding layer at the bottom of the second deep groove.
In one embodiment, the width of the first high-K dielectric layer increases gradually from the potential cut-off layer toward the hole barrier layer.
In one embodiment, the width of the second high-K dielectric layer increases gradually from the potential cut-off layer toward the hole barrier layer.
In one embodiment, the concentration of N-type dopant ions within the potential cut-off layer is greater than the concentration of N-type dopant ions within the N-type drift layer and less than the concentration of N-type dopant ions within the hole barrier layer.
In one embodiment, the first high-K dielectric layer and the second high-K dielectric layer are symmetrically disposed.
In one embodiment, the first P-type shielding layer and the second P-type shielding layer are concave structures, the first P-type shielding layer wraps the bottom of the first high-K dielectric, and the second P-type shielding layer wraps the bottom of the second high-K dielectric.
In one embodiment, the first high-K dielectric layer is in contact with the first polysilicon layer and the second high-K dielectric layer is in contact with the second polysilicon layer.
The second aspect of the embodiment of the application also provides an HK-IGBT, wherein the HK-IGBT is prepared by the preparation method of any one of the embodiments.
The third aspect of the embodiment of the application also provides a chip, which comprises the HK-IGBT prepared by the preparation method according to any one of the embodiments.
The embodiment of the application has the beneficial effects that: by forming the first high-K dielectric layer at the bottom of the first polysilicon layer and forming the second high-K dielectric layer at the bottom of the second polysilicon layer, the electric field distribution in the N-type drift layer can be regulated, the turn-off depletion speed of the device is improved, and the turn-off loss of the device is reduced.
Drawings
FIG. 1 is a schematic flow chart of a preparation method of an HK-IGBT provided by an embodiment of the application;
FIG. 2 is a schematic diagram of a potential cut-off layer, an N-type drift layer, a hole barrier layer, and a P-type well region according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a first P-type heavily doped region, a first N-type heavily doped region, and a second N-type heavily doped region according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a first deep trench and a second deep trench according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a first high-K dielectric layer and a second high-K dielectric layer formed according to an embodiment of the present application;
Fig. 6 is a schematic diagram of a first gate dielectric layer, a first polysilicon layer, a second gate dielectric layer, and a second polysilicon layer according to an embodiment of the present application;
Fig. 7 is a schematic diagram of a P-type collector, and emitter after forming according to an embodiment of the present application;
FIG. 8 is a schematic diagram of a HK-IGBT provided by an embodiment of the application;
110: a collector electrode; 120: an emitter; 131: a first polysilicon layer; 132: a second polysilicon layer; 210: a potential cut-off layer; 220: a P-type collector region; 240: hole barrier layer: 250: a P-type well region; 251: a first P-type floating column; 252: a second P-type floating column; 253: a third P-type floating column; 261: a first N-type heavily doped region; 271: a first P-type heavily doped region; 262: a second N-type heavily doped region; 310: an N-type drift layer; 321: first gate dielectric layer: 322: a second gate dielectric layer; 411: a first high-K dielectric layer; 412: a second high-K dielectric layer; 421: a P-type shielding layer; 422: a second P-type shielding layer; 301: a first deep groove; 302; and a second deep groove.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
It will be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are merely for convenience in describing and simplifying the description based on the orientation or positional relationship shown in the drawings, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus are not to be construed as limiting the application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is one or more than one unless specifically defined otherwise.
Because the IGBT is a bipolar device, electrons and holes are conductive when the IGBT is turned on, in the current IGBT device, at the turn-off moment, the electrons can be quickly pumped away from a channel, and the holes can only be slowly removed through recombination, so that obvious tailing current is caused, and the problem of larger turn-off loss of the IGBT exists.
In order to solve the above technical problems, the embodiment of the application provides a method for preparing HK-IGBT, referring to FIG. 1, the method for preparing HK-IGBT in the embodiment comprises steps S100 to S800.
In step S100, N-type dopant ions are implanted in the front surface of the silicon substrate to form the potential cut-off layer 210.
In this embodiment, as shown in fig. 2, a single crystal silicon material is selected as a silicon substrate, and N-type dopant ions are implanted into the front surface of the silicon substrate to form the potential cut-off layer 210.
In step S200, a silicon layer is epitaxially deposited on the potential cut-off layer 210, and an N-type drift layer 310, a hole barrier layer 240, and a P-type well region 250 are formed through a plurality of ion implantation processes.
In this embodiment, as shown in fig. 2, a silicon material is epitaxially grown on the potential cut-off layer 210, and N-type doped ions are implanted into the newly epitaxially grown silicon material to form an N-type drift layer 310, and N-type doped ions are implanted again into the front surface of the N-type drift layer 310 to form a hole barrier layer 240, wherein the implantation concentration of the second N-type doped ions is greater than the implantation concentration of the first N-type doped ions, so that the concentration of the N-type doped ions in the hole barrier layer 240 is greater than the concentration of the N-type doped ions in the N-type drift layer 310, and the implantation energy of the second N-type doped ions is smaller than the implantation energy of the first N-type doped ions, and at this time, the thickness of the hole barrier layer 240 is smaller than the thickness of the N-type drift layer 310.
In this embodiment, P-type doped ions are continuously injected on the hole barrier layer 240, a P-type well region 250 may be formed on the hole barrier layer 240, and a PN junction may be formed between the P-type well region 250 and the hole barrier layer 240, wherein the injection energy of the P-type doped ions injected on the hole barrier layer 240 is smaller than the injection energy of the second N-type doped ions, the concentration of the P-type doped ions injected on the hole barrier layer 240 is greater than the injection concentration of the second N-type doped ions, and the doping concentration of the P-type doped ions in the hole barrier layer 240 is at least 10 times the concentration of the N-type doped ions in the hole barrier layer 240.
In some embodiments, the concentration of N-type dopant ions within the hole barrier layer 240 is at least 10 times the concentration of N-type dopant ions within the N-type drift layer 310.
In this embodiment, by providing the hole barrier layer 240 between the N-type drift layer 310 and the P-type well region 250, holes can be collected below the hole barrier layer 240, which plays a role in enhancing the conductivity modulation.
In step S300, N-type doped ions and P-type doped ions are respectively implanted into the first preset region and the second preset region on the P-type well region 250 to form a first P-type heavily doped region 271, a first N-type heavily doped region 261 and a second N-type heavily doped region 262.
In this embodiment, the second preset region on the P-well 250 is located in the central region of the first preset region, as shown in fig. 3, N-type doped ions are implanted into the first preset region on the P-well 250, then P-type doped ions are implanted into the second preset region on the P-well 250 to form a first P-type heavily doped region 271, at this time, the region in which N-type doped ions are implanted is divided into two N-type doped regions, so as to form a first N-type heavily doped region 261 and a second N-type heavily doped region 262, and the first P-type heavily doped region 271 is located between the first N-type heavily doped region 261 and the second N-type heavily doped region 262.
In one embodiment, the doping concentration in the first and second N-type heavily doped regions 261, 262 is greater than the doping concentration in the N-type drift layer 310.
In one embodiment, the implantation concentration of the N-type dopant ions in the first preset region on the P-type well region 250 is smaller than the implantation concentration of the P-type dopant ions in the second preset region on the P-type well region 250, and the implantation energy of the N-type dopant ions in the first preset region on the P-type well region 250 is equal to the implantation energy of the P-type dopant ions in the second preset region on the P-type well region 250, so that the thicknesses of the first P-type heavily doped region 271, the first N-type heavily doped region 261 and the second N-type heavily doped region 262 are equal.
In this embodiment, a PN junction is formed between the first N-type heavily doped region 261 and the P-type well region 250, and a PN junction is formed between the second N-type heavily doped region 262 and the P-type well region 250.
In step S400, etching is performed in the third preset area and the fourth preset area on the P-type well region 250 to form a first deep trench 301 and a second deep trench 302, and a dielectric material with a high dielectric constant is deposited in the first deep trench 301 and the second deep trench 302 to form a first high-K dielectric layer 411 and a second high-K dielectric layer 412, as shown in fig. 5.
In this embodiment, as shown in fig. 4 and 5, the first deep trench 301 is in contact with the first N-type heavily doped region 261, the second deep trench 302 is in contact with the second N-type heavily doped region 262, the first deep trench 301 and the second deep trench 302 divide the P-type well region 250 into a plurality of P-type floating pillars, wherein the first P-type floating pillar 251 and the second P-type floating pillar 252 are located at two sides of the first deep trench 301, the second P-type floating pillar 252 and the third P-type floating pillar 253 are located at two sides of the second deep trench 302, and the first deep trench 301 and the second deep trench 302 extend deep into the N-type drift layer 310. A first high-K dielectric layer 411 may be formed at the bottom of the first deep trench 301 and a second high-K dielectric layer 412 may be formed at the bottom of the second deep trench 302 by depositing a high-K dielectric material and then etching the deposited dielectric material.
In some embodiments, the first deep trench 301 and the second deep trench 302 extend into the N-type drift layer 310 to a depth of at least one half the thickness of the N-type drift layer 310.
In some embodiments, the depth of the first and second deep grooves 301, 302 is the same.
In some embodiments, the widths of the first and second deep grooves 301 and 302 are the same.
In step S500, a first gate dielectric layer 321 is formed on the inner wall of the first deep trench 301, and a second gate dielectric layer 322 is formed on the inner wall of the second deep trench 302.
In this embodiment, the first gate dielectric layer 321 may be formed on the inner wall of the first deep trench 301 by a deposition or oxidation process, if the material of the first gate dielectric layer 321 is a silicon nitride material, the silicon nitride layer may be formed on the inner wall of the first deep trench 301 and above the first P-type floating pillar 251 by depositing the silicon nitride material as the first gate dielectric layer 321, and if the material of the first gate dielectric layer 321 is a silicon oxide material, the silicon oxide layer may be formed on the inner wall of the first deep trench 301 and above the first P-type floating pillar 251 directly by an oxidation process as the first gate dielectric layer 321.
In one embodiment, the inner wall of the first deep groove 301 may include a sidewall of the first deep groove 301 and a bottom thereof.
In this embodiment, the second gate dielectric layer 322 may be formed on the inner wall of the second deep trench 302 by deposition or oxidation, if the material of the second gate dielectric layer 322 is silicon nitride, the silicon nitride layer may be formed on the inner wall of the second deep trench 302 and above the third P-type floating pillar 253 by deposition of the silicon nitride material as the second gate dielectric layer 322, and if the material of the second gate dielectric layer 322 is silicon oxide, the silicon oxide layer may be formed on the inner wall of the second deep trench 302 and above the third P-type floating pillar 253 as the second gate dielectric layer 322 directly by oxidation.
In one embodiment, the inner wall of the second deep groove 302 may include the side wall of the second deep groove 302 and the bottom thereof.
In step S600, a first polysilicon layer 131 is formed in the first deep trench 301, a second polysilicon layer 132 is formed in the second deep trench 302, and the gate dielectric material is continuously deposited such that the first gate dielectric layer 321 wraps the first polysilicon layer 131, and the second gate dielectric layer 322 wraps the second polysilicon layer 132.
In this embodiment, the first polysilicon layer 131 is formed in the first deep trench 301, the first polysilicon layer 131 is located on the first gate dielectric layer 321 at the bottom of the first deep trench 301 or directly located on the first high-K dielectric layer 411, the first polysilicon layer 131 is isolated from the hole barrier layer 240, the first P-type floating pillar 251 and the second P-type floating pillar 252 by the first gate dielectric layer 321 on the sidewall of the first deep trench 301, and after the first polysilicon layer 131 is formed, the gate dielectric material is continuously deposited and may be integrated with the gate dielectric material on the inner wall of the first deep trench 301, so as to form the first gate dielectric layer 321 wrapping the first polysilicon layer 131.
In some embodiments, if the material of the first gate dielectric layer 321 is a silicon oxide material, the first polysilicon layer 131 may be directly oxidized by an oxidation process to form a silicon oxide layer as the first gate dielectric layer 321. If the material of the first gate dielectric layer 321 is a silicon nitride material, a silicon nitride layer may be formed as the first gate dielectric layer 321 over the first polysilicon layer 131 by depositing the silicon nitride material.
In this embodiment, the second polysilicon layer 132 is formed in the second deep trench 302, the second polysilicon layer 132 is located on the second gate dielectric layer 322 at the bottom of the second deep trench 302 or directly located on the second high-K dielectric layer 412, the second polysilicon layer 132 is isolated from the hole barrier layer 240, the third P-type floating pillar 253 and the second P-type floating pillar 252 by the second gate dielectric layer 322 on the sidewall of the second deep trench, and after the second polysilicon layer 132 is formed, the gate dielectric material is continuously deposited and may be integrated with the gate dielectric material on the inner wall of the second deep trench 302, so as to form the second gate dielectric layer 322 wrapping the second polysilicon layer 132.
In some embodiments, if the material of the second gate dielectric layer 322 is a silicon oxide material, the second polysilicon layer 132 may be directly oxidized by an oxidation process to form a silicon oxide layer as the second gate dielectric layer 322. If the material of the second gate dielectric layer 322 is a silicon nitride material, a silicon nitride layer may be formed over the second polysilicon layer 132 by depositing the silicon nitride material as the second gate dielectric layer 322.
In step S700, P-type dopant ions are implanted into the back surface of the silicon substrate to form the P-type collector 220.
In this embodiment, as shown in fig. 3, P-type dopant ions are implanted into the back surface of the silicon substrate to form a P-type collector region 220, and a PN junction is formed between the P-type collector region 220 and the potential cut-off layer 210.
In step S800, an emitter 120 is formed in contact with the first P-type heavily doped region 271, the first N-type heavily doped region 261, and the second N-type heavily doped region 262, and a collector 110 is formed in contact with the P-type collector 220, forming a first gate in contact with the first polysilicon layer 131 and a second gate in contact with the second polysilicon layer 132.
In one embodiment, as shown in fig. 8, the preparation method in this embodiment further includes: forming a first P-type shielding layer 421 at the bottom of the first deep trench 301 before depositing the high-k dielectric material in the first deep trench 301; a second P-type shield layer 422 is formed at the bottom of the second deep trench 302 prior to depositing the high-k dielectric material in the second deep trench 302.
In the present embodiment, as shown in fig. 4 and 8, after forming the first deep trench 301 and the second deep trench 302, the first P-type shielding layer 421 is formed at the bottom of the first deep trench 301, and the second P-type shielding layer 422 is formed at the bottom of the second deep trench 302. Specifically, the first P-type shielding layer 421 may be formed by performing an ion implantation process at the bottom of the first deep trench 301, the ion implantation angle being an angle between the implantation direction and the central axis of the first deep trench 301 within 30 °. Similarly, the second P-type shielding layer 422 may be formed by performing an ion implantation process at the bottom of the second deep trench 302, the ion implantation angle being within 30 ° and the ion implantation angle being an angle between the implantation direction and the central axis of the second deep trench 302.
In some embodiments, in the process of forming the first P-type shielding layer 421 by performing the ion implantation process on the bottom of the first deep trench 301, the implantation angle may be gradually increased from 0 ° to 30 °, so that P-type doped ions may be simultaneously implanted into the bottom of the first deep trench 301 and the bottoms of the two sidewalls thereof to form the first P-type shielding layer 421 with an arc structure, and the concentration of the P-type doped ions at the bottoms of the two sidewalls of the first deep trench 301 is smaller than that of the P-type doped ions at the bottom of the first deep trench 301.
In some embodiments, in the process of forming the second P-type shielding layer 422 by performing the ion implantation process on the bottom of the second deep trench 302, the implantation angle may be gradually increased from 0 ° to 30 °, so that P-type doped ions may be simultaneously implanted into the bottom of the second deep trench 302 and the bottoms of the two sidewalls thereof to form the second P-type shielding layer 422 with an arc structure, and the concentration of the P-type doped ions at the bottoms of the two sidewalls of the second deep trench 302 is smaller than that of the bottom of the second deep trench 302.
In some embodiments, the first P-type shielding layer 421 and the second P-type shielding layer 422 are concave structures, the first P-type shielding layer 421 wraps around the bottom of the first high-K dielectric layer 411, and the second P-type shielding layer 422 wraps around the bottom of the second high-K dielectric 41 layer.
In this embodiment, by disposing the first P-type shielding layer 421 at the bottom of the first high-K dielectric layer 411, the electric field peak value in the corner region at the bottom of the first high-K dielectric layer 411 can be reduced, and disposing the second P-type shielding layer 422 at the bottom of the second high-K dielectric layer 412, the electric field peak value in the corner region at the bottom of the second high-K dielectric layer 412 can be reduced.
In one embodiment, the concentration of P-type dopant ions within the first and second P-type shield layers 421 and 422 is greater than the concentration of N-type dopant ions within the N-type drift layer 310.
In one embodiment, the concentration of P-type dopant ions within the first and second P-type shield layers 421 and 422 is at least 10 times the concentration of N-type dopant ions within the N-type drift layer 310.
In one embodiment, the width of the first high-K dielectric layer 411 increases gradually from the potential blocking layer 210 toward the hole barrier layer 240.
In one embodiment, the width of the second high-K dielectric layer 412 increases gradually from the potential blocking layer 210 toward the hole barrier layer 240.
In one embodiment, the high-k dielectric material may be hafnium oxide, aluminum oxide, or the like.
In one embodiment, the concentration of N-type dopant ions within the potential blocking layer 210 is greater than the concentration of N-type dopant ions within the N-type drift layer 310 and less than the concentration of N-type dopant ions within the hole barrier layer 240.
In one embodiment, the first high-K dielectric layer 411 and the second high-K dielectric layer 412 are symmetrically disposed.
In one embodiment, the first high-K dielectric layer 411 is in contact with the first polysilicon layer 131 and the second high-K dielectric layer 412 is in contact with the second polysilicon layer 132.
The embodiment of the application also provides the HK-IGBT, which is prepared by the preparation method of any one of the embodiments.
The embodiment of the application also provides a chip, which comprises the HK-IGBT prepared by the preparation method according to any one of the embodiments.
In this embodiment, the chip includes a chip substrate on which one or more HK-IGBTs are disposed, which may be prepared by the preparation method in any of the above embodiments, or may be disposed on the chip substrate.
In one specific application embodiment, other related semiconductor devices may also be integrated on the chip substrate to form an integrated circuit with the HK-IGBT.
In one specific application embodiment, the chip may be a switching chip or a driving chip.
The embodiment of the application has the beneficial effects that: by forming the first high-K dielectric layer at the bottom of the first polysilicon layer and forming the second high-K dielectric layer at the bottom of the second polysilicon layer, the electric field distribution in the N-type drift layer can be regulated, the turn-off depletion speed of the device is improved, and the turn-off loss of the device is reduced.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of each doped region and device is illustrated, and in practical application, the above-described function allocation may be performed by different doped regions and devices according to needs, i.e. the internal structure of the device is divided into different doped regions, so as to perform all or part of the above-described functions. The doped regions and the devices in the embodiments can be integrated in one unit, or each unit can exist alone physically, or two or more units can be integrated in one unit.
In addition, the specific names of the doped regions and the devices are only used for distinguishing the doped regions and the devices from each other, and are not used for limiting the protection scope of the application.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
In addition, each doped region in the embodiments of the present application may be integrated in one unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (10)
1. The preparation method of the HK-IGBT is characterized by comprising the following steps of:
injecting N-type doping ions into the front surface of the silicon substrate to form a potential cut-off layer;
Epitaxially depositing a silicon layer on the potential cut-off layer, and forming an N-type drift layer, a hole barrier layer and a P-type well region through a plurality of ion implantation processes; the concentration of the N-type doping ions in the hole barrier layer is at least 10 times that in the N-type drift layer;
Injecting N-type doping ions and P-type doping ions into a first preset region and a second preset region on the P-type well region respectively to form a first P-type heavily doped region, a first N-type heavily doped region and a second N-type heavily doped region; the first P type heavily doped region is positioned between the first N type heavily doped region and the second N type heavily doped region;
Etching a third preset region and a fourth preset region on the P-type well region to form a first deep groove and a second deep groove, and depositing dielectric materials with high dielectric constants in the first deep groove and the second deep groove to form a first high-K dielectric layer and a second high-K dielectric layer; the first deep groove is in contact with the first N-type heavily doped region, and the second deep groove is in contact with the second N-type heavily doped region;
Forming a first grid dielectric layer on the inner wall of the first deep groove, and forming a second grid dielectric layer on the inner wall of the second deep groove;
Forming a first polysilicon layer in the first deep groove, forming a second polysilicon layer in the second deep groove, and continuing depositing a gate dielectric material, so that the first gate dielectric layer wraps the first polysilicon layer, and the second gate dielectric layer wraps the second polysilicon layer;
injecting P-type doping ions into the back of the silicon substrate to form a P-type collector region;
Forming an emitter electrode in contact with the first P-type heavily doped region, the first N-type heavily doped region and the second N-type heavily doped region, forming a collector electrode in contact with the P-type collector region, and forming a first grid electrode in contact with the first polysilicon layer and a second grid electrode in contact with the second polysilicon layer;
Forming a first P-type shielding layer at the bottom of the first deep groove before depositing a dielectric material with a high dielectric constant in the first deep groove; forming a second P-type shielding layer at the bottom of the second deep groove before depositing a dielectric material with a high dielectric constant in the second deep groove; the first P-type shielding layer wraps the bottom of the first high-K dielectric, and the second P-type shielding layer wraps the bottom of the second high-K dielectric;
In the process of forming the first P-type shielding layer by an ion implantation process at the bottom of the first deep groove, the implantation angle is gradually increased from 0 degrees to 30 degrees, so that P-type doping ions are simultaneously implanted into the bottom of the first deep groove and the bottoms of the two side walls of the first deep groove to form the first P-type shielding layer with an arc-shaped structure, and the concentration of the P-type doping ions at the bottoms of the two side walls of the first deep groove is smaller than that of the P-type doping ions at the bottom of the first deep groove; in the process of forming the second P-type shielding layer by performing an ion implantation process on the bottom of the second deep groove, the implantation angle is gradually increased from 0 degrees to 30 degrees, so that P-type doping ions are simultaneously implanted into the bottom of the second deep groove and the bottoms of the two side walls of the second deep groove to form the second P-type shielding layer with an arc-shaped structure, and the concentration of the P-type doping ions at the bottoms of the two side walls of the second deep groove is smaller than that of the bottom of the second deep groove.
2. The method of manufacturing HK-IGBTs of claim 1, further comprising:
Forming a first P-type shielding layer at the bottom of the first deep groove before depositing a dielectric material with a high dielectric constant in the first deep groove;
and before a dielectric material with high dielectric constant is deposited in the second deep groove, forming a second P-type shielding layer at the bottom of the second deep groove.
3. The method of manufacturing a HK-IGBT of claim 1, wherein the width of the first high K dielectric layer increases gradually from the potential cut-off layer in the direction of the hole barrier layer.
4. The method of manufacturing a HK-IGBT of claim 1, wherein the width of the second high K dielectric layer increases gradually from the potential cut-off layer in the direction of the hole barrier layer.
5. The method of manufacturing a HK-IGBT of claim 1, wherein the concentration of N type dopant ions in the potential cut-off layer is greater than the concentration of N type dopant ions in the N type drift layer and less than the concentration of N type dopant ions in the hole barrier layer.
6. The HK-IGBT fabrication method of claim 1 wherein the first high-K dielectric layer and the second high-K dielectric layer are symmetrically arranged.
7. The HK-IGBT manufacturing method of claim 2, wherein the first and second P-type shield layers are concave structures.
8. The method of manufacturing a HK-IGBT of claim 7, wherein the first high K dielectric layer is in contact with the first polysilicon layer and the second high K dielectric layer is in contact with the second polysilicon layer.
9. HK-IGBT, characterized in that it is prepared by the preparation method of HK-IGBT according to any of claims 1 to 8.
10. A chip comprising HK-IGBT prepared by the preparation method according to any one of claims 1 to 8.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105428408A (en) * | 2015-12-22 | 2016-03-23 | 电子科技大学 | Field-stop trench gate IGBT device |
| CN107731912A (en) * | 2017-09-02 | 2018-02-23 | 西安交通大学 | Double the groove carborundum IGBT devices and preparation method of a kind of low on-resistance, small grid electric charge |
| CN110010690A (en) * | 2019-03-29 | 2019-07-12 | 上海华虹宏力半导体制造有限公司 | The manufacturing method of NLDMOS |
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| JP6053103B2 (en) * | 2012-04-12 | 2016-12-27 | 富士電機株式会社 | Wide band gap semiconductor device and method of manufacturing the same |
| DE102020004718A1 (en) * | 2019-08-13 | 2021-02-18 | Semiconductor Components Industries Llc | SILICON CARBIDE DIGGING POWER DEVICE |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105428408A (en) * | 2015-12-22 | 2016-03-23 | 电子科技大学 | Field-stop trench gate IGBT device |
| CN107731912A (en) * | 2017-09-02 | 2018-02-23 | 西安交通大学 | Double the groove carborundum IGBT devices and preparation method of a kind of low on-resistance, small grid electric charge |
| CN110010690A (en) * | 2019-03-29 | 2019-07-12 | 上海华虹宏力半导体制造有限公司 | The manufacturing method of NLDMOS |
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