CN117497409A - Heterojunction reverse-conduction insulated gate bipolar transistor, preparation method thereof and chip - Google Patents

Heterojunction reverse-conduction insulated gate bipolar transistor, preparation method thereof and chip Download PDF

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CN117497409A
CN117497409A CN202311834862.XA CN202311834862A CN117497409A CN 117497409 A CN117497409 A CN 117497409A CN 202311834862 A CN202311834862 A CN 202311834862A CN 117497409 A CN117497409 A CN 117497409A
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layer
type
region
heterojunction
reverse
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原一帆
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Shenzhen Sirius Semiconductor Co ltd
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Shenzhen Sirius Semiconductor Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The utility model belongs to the technical field of power devices, a heterojunction reverse-conduction insulated gate bipolar transistor and a preparation method thereof and a chip thereof are provided, wherein a hole barrier layer and a P-type well region are sequentially formed on the front side of an N-type drift layer, a first P-type heavily doped region and a first N-type heavily doped region which are contacted with an emitter are formed on the P-type well region, a potential cut-off layer, a silicon carbide doped layer, an N-type collector region and a P-type collector region which are contacted with a collector are formed on the back side of the N-type drift layer, the polysilicon layer is isolated from the hole barrier layer, the P-type well region, the first N-type heavily doped region and the emitter through a gate dielectric layer, a heterojunction structure is arranged between the silicon carbide doped layer and the potential cut-off layer, and a heterojunction structure is arranged between the silicon carbide doped layer and the N-type collector region, so that the built-in potential in the device can be increased, the built-in potential is larger than the built-in potential between the P-type collector region and the potential cut-off layer, and the voltage rebound phenomenon in the device is eliminated.

Description

Heterojunction reverse-conduction insulated gate bipolar transistor, preparation method thereof and chip
Technical Field
The application belongs to the technical field of power devices, and particularly relates to a heterojunction reverse-conduction insulated gate bipolar transistor, a preparation method thereof and a chip.
Background
An Insulated Gate Bipolar Transistor (IGBT) is a semiconductor device having the advantages of both a power Metal-Oxide-semiconductor field effect transistor (MOSFET) and a bipolar junction transistor (bjt), has the characteristics of high input impedance and low on-voltage drop, and is generally applied in switching scenarios of medium frequency and medium power. However, since IGBTs do not have reverse conduction capability, when applied in an inductive load situation, a fast recovery diode (Fast Recovery Diode, FRD) is typically used in parallel with it to provide freewheeling protection. The two independent devices of the IGBT and the FWD are welded together through the lead wires to be made into a module for use, but parasitic inductance is brought in this way, and the use of the module is limited due to the large size. Therefore, heterojunction reverse-conduction insulated gate bipolar transistors (Reverse Conducting IGBT, RC-IGBT) are developed by integrating IGBT and FRD on the same chip, and reverse-conduction capability of the RC-IGBT can be obtained due to the fact that the collector short-circuit structure is arranged on the back surface of the RC-IGBT.
Compared with the traditional IGBT, the RC-IGBT can be used in an inductive load circuit without connecting a freewheeling diode in parallel, and a reverse current discharge channel is arranged in the RC-IGBT device. However, the collector short-circuit structure arranged on the back surface of the RC-IGBT can enable the device to be converted from the MOSFET conduction mode to the IGBT conduction mode when the device is conducted in the forward direction, and a voltage rebound phenomenon (namely a snapback phenomenon) exists at the moment, so that the parallel connection of the devices is not facilitated.
Disclosure of Invention
In order to solve the technical problems, the embodiment of the application provides a heterojunction reverse-conducting insulated gate bipolar transistor, a preparation method thereof and a chip, and the problem that the existing heterojunction reverse-conducting insulated gate bipolar transistor is poor in reverse recovery characteristic can be solved.
An embodiment of the present application provides a method for preparing a heterojunction reverse-conducting insulated gate bipolar transistor, where the method for preparing the heterojunction reverse-conducting insulated gate bipolar transistor includes:
p-type doping ions and N-type doping ions are respectively injected into the first doping region and the second doping region on the front surface of the silicon substrate to form a P-type collector region and an N-type collector region;
epitaxially growing a silicon material on the P-type collector region and the N-type collector region, and injecting N-type doping ions to form a potential cut-off layer;
etching a preset area on the potential cut-off layer to form a groove, and implanting N-type doping ions to form a silicon carbide doped layer after epitaxially growing a silicon carbide material inside and outside the groove; the silicon carbide doping layer and the potential cut-off layer are of a heterojunction structure, and the silicon carbide doping layer and the N-type collector region are of a heterojunction structure;
epitaxially depositing a silicon layer on the silicon carbide doped layer and the potential cut-off layer, and forming an N-type drift layer, a hole barrier layer and a P-type well region through a plurality of ion implantation processes;
injecting P-type doping ions and N-type doping ions into a first preset region and a second preset region on the P-type well region respectively to form a first P-type heavily doped region and a first N-type heavily doped region;
etching a third preset area on the P-type well region to form a first deep groove, and forming a grid dielectric layer on the inner wall of the first deep groove;
depositing a polysilicon material on the gate dielectric layer to form a polysilicon layer, and continuing to deposit the gate dielectric material after forming the polysilicon layer so that the gate dielectric layer wraps the polysilicon layer;
and forming an emitter electrode in contact with the first P-type heavily doped region and the first N-type heavily doped region, forming a collector electrode in contact with the P-type collector region and the N-type collector region, and forming a grid electrode in contact with the polycrystalline silicon layer.
In some embodiments, the method of making further comprises:
forming a high-K dielectric layer with the upper surface not exceeding the lower surface of the hole barrier layer at the bottom of the first deep groove; the high-K dielectric layer is positioned between the polysilicon layer and the N-type drift layer.
In some embodiments, before forming the high-K dielectric layer with an upper surface not exceeding a lower surface of the hole barrier layer at the bottom of the first deep trench, the method further comprises:
forming a P-type shielding layer at the bottom of the first deep groove; the P-type shielding layer is positioned between the high-K dielectric layer and the N-type drift layer.
In some embodiments, the width of the high-K dielectric layer increases gradually from the potential cut-off layer in the direction of the hole barrier layer.
In some embodiments, a schottky contact is between the N-type collector region and the collector.
In some embodiments, the concentration of N-type dopant ions within the potential cut-off layer is greater than the concentration of N-type dopant ions within the N-type drift layer and less than the concentration of N-type dopant ions within the hole barrier layer.
In some embodiments, the thickness of the N-type collector region is the same as the thickness of the P-type collector region.
In some embodiments, the high-K dielectric layer is in contact with the polysilicon layer.
The second aspect of the embodiment of the application also provides a heterojunction reverse-conduction insulated gate bipolar transistor, which is prepared by the preparation method of any one of the embodiments.
The third aspect of the embodiment of the application also provides a chip, which comprises the heterojunction reverse-conduction insulated gate bipolar transistor prepared by the preparation method according to any one of the embodiments.
The beneficial effects of the embodiment of the application are that: the front surface of the N-type drift layer is sequentially provided with a hole barrier layer and a P-type well region, a first P-type heavily doped region and a first N-type heavily doped region which are contacted with an emitter are formed on the P-type well region, the back surface of the N-type drift layer is provided with a potential cut-off layer, a silicon carbide doped layer, an N-type collecting region and a P-type collecting region which are contacted with a collector, the polysilicon layer is isolated from the hole barrier layer, the P-type well region, the first N-type heavily doped region and the emitter through a gate dielectric layer, a heterojunction structure is arranged between the silicon carbide doped layer and the potential cut-off layer, and a heterojunction structure is arranged between the silicon carbide doped layer and the N-type collecting region, so that the built-in potential in the device can be improved, and the built-in potential is larger than that between the P-type collecting region and the potential cut-off layer, thereby eliminating the voltage rebound phenomenon in the device.
Drawings
Fig. 1 is a schematic flow chart of a preparation method of a heterojunction reverse-conducting insulated gate bipolar transistor according to an embodiment of the present application;
FIG. 2 is a schematic diagram of forming a potential blocking layer, a P-type collector region, an N-type collector region provided in an embodiment of the present application;
fig. 3 is a schematic diagram of forming a heterojunction structure provided in an embodiment of the present application;
fig. 4 is a schematic diagram of forming an N-type drift layer, a hole barrier layer, a P-type well region, a first P-type heavily doped region, and a first N-type heavily doped region according to an embodiment of the present application;
fig. 5 is a schematic diagram of forming a gate dielectric layer and a polysilicon layer according to an embodiment of the present application;
fig. 6 is a schematic diagram of a collector and an emitter formed according to an embodiment of the present application;
fig. 7 is a schematic diagram of a heterojunction reverse-conducting insulated gate bipolar transistor according to an embodiment of the present application;
fig. 8 is a schematic diagram of a heterojunction reverse-conducting insulated gate bipolar transistor according to an embodiment of the present application;
110: a collector electrode; 120: an emitter; 130: a polysilicon layer; 210: a potential cut-off layer; 211: a silicon carbide doped layer; 220: a P-type collector region; 230: an N-type collector region; 240: hole barrier layer: 250: a P-type well region; 261: a first P-type heavily doped region; 271: a first N-type heavily doped region; 310: an N-type drift layer; 320: gate dielectric layer: 410: a high-K dielectric layer; 420: and a P-type shielding layer.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved by the present application more clear, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
An Insulated Gate Bipolar Transistor (IGBT) is a semiconductor device having the advantages of both a power Metal-Oxide-semiconductor field effect transistor (MOSFET) and a bipolar junction transistor (bjt), has the characteristics of high input impedance and low on-voltage drop, and is generally applied in switching scenarios of medium frequency and medium power. However, since IGBTs do not have reverse conduction capability, when applied in an inductive load situation, a fast recovery diode (Fast Recovery Diode, FRD) is typically used in parallel with it to provide freewheeling protection. The two independent devices of the IGBT and the FWD are welded together through the lead wires to be made into a module for use, but parasitic inductance is brought in this way, and the use of the module is limited due to the large size. Therefore, heterojunction reverse-conduction insulated gate bipolar transistors (Reverse Conducting IGBT, RC-IGBT) are developed by integrating IGBT and FRD on the same chip, and reverse-conduction capability of the RC-IGBT can be obtained due to the fact that the collector short-circuit structure is arranged on the back surface of the RC-IGBT.
Compared with the traditional IGBT, the RC-IGBT can be used in an inductive load circuit without connecting a freewheeling diode in parallel, and a reverse current discharge channel is arranged in the RC-IGBT device. However, the collector short-circuit structure arranged on the back surface of the RC-IGBT can enable the device to be converted from the MOSFET conduction mode to the IGBT conduction mode when the device is conducted in the forward direction, and a voltage rebound phenomenon (namely a snapback phenomenon) exists at the moment, so that the parallel connection of the devices is not facilitated.
In order to solve the above technical problems, the embodiment of the present application provides a method for preparing a heterojunction reverse-conducting insulated gate bipolar transistor, as shown in fig. 1, where the method for preparing a heterojunction reverse-conducting insulated gate bipolar transistor in the embodiment includes steps S100 to S800.
In step S100, P-type doped ions and N-type doped ions are respectively implanted into the first doped region and the second doped region on the front surface of the silicon substrate to form a P-type collector region 220 and an N-type collector region 230.
In this embodiment, as shown in fig. 2, a single crystal silicon material is selected as a silicon substrate, N-type doped ions are implanted into a first doped region on the front surface of the silicon substrate to form an N-type collector region 230, P-type doped ions are implanted into a second doped region on the front surface of the silicon substrate to form a P-type collector region 220, and the first doped region on the front surface of the silicon substrate is adjacent to the second doped region on the front surface of the silicon substrate.
In some embodiments, the first doped region of the front side of the silicon substrate is the same area as the second doped region of the front side thereof.
In step S200, a silicon material is epitaxially grown on the P-type collector region 220 and the N-type collector region 230, and N-type dopant ions are implanted to form a potential stop layer 210.
In this embodiment, as shown in fig. 2, the potential cut-off layer 210 is formed by epitaxially growing a silicon material and implanting N-type dopant ions, and a PN junction is formed between the p-type collector region 220 and the potential cut-off layer 210.
In step S300, a recess is etched in a preset area on the potential cut-off layer 210, and N-type doped ions are implanted to form a silicon carbide doped layer 211 after epitaxially growing a silicon carbide material in the recess.
In this embodiment, as shown in fig. 3, the silicon carbide doped layer 211 is disposed in parallel with the potential cut-off layer 210, a heterojunction structure is formed between the silicon carbide doped layer 211 and the potential cut-off layer 210, and a heterojunction structure is formed between the silicon carbide doped layer 211 and the N-type collector region 230. By introducing a heterojunction structure into the collector region of the device, the built-in potential within the device can be increased such that it is greater than the built-in potential between the P-type collector region 220 and the potential blocking layer 210, thereby eliminating voltage bouncing within the device.
In step S400, a silicon layer is epitaxially deposited on the silicon carbide doped layer 211 and the potential cut-off layer 210, and an N-type drift layer 310, a hole barrier layer 240, and a P-type well region 250 are formed through a plurality of ion implantation processes.
In this embodiment, as shown in fig. 4, a silicon material is epitaxially grown on the potential cut-off layer 210 and the silicon carbide doped layer 211, and N-type doped ions are implanted into the newly epitaxially grown silicon material to form an N-type drift layer 310, and N-type doped ions are implanted again into the front surface of the N-type drift layer 310 to form a hole barrier layer 240, wherein the implantation concentration of the second N-type doped ions is greater than the implantation concentration of the first N-type doped ions, so that the concentration of the N-type doped ions in the hole barrier layer 240 is greater than the concentration of the N-type doped ions in the N-type drift layer 310, and the implantation energy of the second N-type doped ions is smaller than the implantation energy of the first N-type doped ions, and at this time, the thickness of the hole barrier layer 240 is smaller than the thickness of the N-type drift layer 310.
In this embodiment, the P-type doped ions are continuously injected on the hole barrier layer 240, and the P-type well region 250 may be formed on the hole barrier layer 240, wherein the injection energy of the P-type doped ions injected on the hole barrier layer 240 is smaller than the injection energy of the second N-type doped ions, and the concentration of the P-type doped ions injected on the hole barrier layer 240 is greater than the injection concentration of the second N-type doped ions, and the doping concentration of the P-type doped ions in the hole barrier layer 240 is at least 10 times the concentration of the N-type doped ions in the hole barrier layer 240.
In some embodiments, the concentration of N-type dopant ions within the hole barrier layer 240 is at least 10 times the concentration of N-type dopant ions within the N-type drift layer 310.
In this embodiment, by providing the hole barrier layer 240 between the N-type drift layer 310 and the P-type well region 250, holes can be collected below the hole barrier layer 240, which plays a role in enhancing the conductivity modulation.
In step S500, P-type doped ions and N-type doped ions are respectively implanted into the first preset region and the second preset region on the P-type well region to form a first P-type heavily doped region 261 and a first N-type heavily doped region 271.
In this embodiment, as shown in fig. 4, P-type doped ions are implanted into a first preset area on the P-type well 250 to form a first P-type heavily doped area 261, N-type doped ions are respectively implanted into a second preset area on the P-type well 250 to form a first N-type heavily doped area 271, the first preset area and the second preset area on the P-type well 250 are adjacently arranged, a PN junction is formed between the first P-type heavily doped area 261 and the first N-type heavily doped area 271, and a PN junction is formed between the first N-type heavily doped area 271 and the P-type well 250. The concentration of P-type dopant ions implanted in the first predetermined region over the P-type well region 250 is greater than the concentration of P-type dopant ions implanted in the hole barrier layer 240, and the implantation energy of P-type dopant ions implanted in the first predetermined region over the P-type well region 250 is less than the implantation energy of P-type dopant ions implanted in the hole barrier layer 240. The concentration of the N-type dopant ions respectively injected into the second predetermined regions on the P-type well region 250 is greater than the concentration of the P-type dopant ions respectively injected into the hole barrier layer 240, and the injection energy of the N-type dopant ions respectively injected into the second predetermined regions on the P-type well region 250 is smaller than the injection energy of the P-type dopant ions respectively injected into the hole barrier layer 240.
In some embodiments, the concentration of P-type dopant ions implanted in the first predetermined region on the P-type well region 250 is at least 10 times that of P-type dopant ions implanted in the hole barrier layer 240, and the concentration of N-type dopant ions implanted in the second predetermined region on the P-type well region 250 is at least 10 times that of P-type dopant ions implanted in the hole barrier layer 240.
In step S600, a first deep trench is etched in a third preset area on the P-type well 250, and a gate dielectric layer 320 is formed on an inner wall of the first deep trench.
In this embodiment, as shown in fig. 5, the third preset region and the second preset region on the P-type well region 250 are adjacent, and the second preset region is located between the first preset region and the third preset region. A first deep trench is etched in the third preset region on the P-type well 250, and a gate dielectric layer 320 is formed on the inner wall of the first deep trench. Specifically, the gate dielectric layer 320 may be formed on the inner wall of the first deep trench by a deposition or oxidation process, if the material of the gate dielectric layer 320 is a silicon nitride material, the silicon nitride layer may be formed on the inner wall of the first deep trench by depositing the silicon nitride material to serve as the gate dielectric layer 320, and if the material of the gate dielectric layer 320 is a silicon oxide material, the silicon oxide layer may be directly formed on the inner wall of the first deep trench by an oxidation process to serve as the gate dielectric layer 320, where the inner wall of the first deep trench includes the side wall of the first deep trench and the bottom thereof.
In step S700, a polysilicon material is deposited on the gate dielectric layer to form a polysilicon layer 130, and the gate dielectric material is deposited after forming the polysilicon layer 130 so that the gate dielectric layer 320 wraps around the polysilicon layer 130.
In this embodiment, as shown in fig. 5, a polysilicon layer 130 is formed in the first deep trench, the polysilicon layer 130 is located on the gate dielectric layer 320 at the bottom of the first deep trench, and is isolated from the hole barrier layer 240 and the P-type well region 250 by the gate dielectric layer 320 on the sidewall of the first deep trench, and the gate dielectric layer 320 wrapping the polysilicon layer 130 may be formed by forming the polysilicon layer 130 to be thicker and further depositing the gate dielectric material.
In some embodiments, if the material of the gate dielectric layer 320 is a silicon oxide material, the polysilicon layer 130 may be directly oxidized by an oxidation process to form a silicon oxide layer as the gate dielectric layer 320. If the material of the gate dielectric layer 320 is a silicon nitride material, a silicon nitride layer may be formed as the gate dielectric layer 320 over the polysilicon layer 130 by depositing the silicon nitride material.
In step S800, an emitter 120 is formed in contact with the first P-type heavily doped region 261 and the first N-type heavily doped region 271, and a collector 110 is formed in contact with the P-type collector 220 and the N-type collector 230, forming a gate in contact with the polysilicon layer 130.
In this embodiment, the emitter 120 may be formed by depositing a metal material layer on the first P-type heavily doped region 261 and the first N-type heavily doped region 271 through a metal deposition process, and the collector 110 may be formed by depositing a metal material layer on the P-type collector region 220 and the N-type collector region 230 on the back surface of the device. A gate electrode in contact with the polysilicon layer 130 is formed by etching the gate dielectric layer 320 to form a via hole and filling a metal material in contact with the polysilicon layer 130.
In one embodiment, as shown in fig. 6, schottky contact is formed between the collector 110 and the N-type collector region 230, and since the potential difference between the N-type collector region 230 and the potential blocking layer 210 is small, holes are not injected into the P-type collector region 220 in the initial stage of device turn-on, so that by setting schottky contact between the collector 110 and the N-type collector region 230, the turn-on potential of the N-type collector region 230 can be increased, thereby suppressing the occurrence of the voltage bouncing phenomenon of the device.
In one embodiment, N-type collector region 230 is disposed opposite first P-type heavily doped region 261.
In some embodiments, in step S100, N-type doped ion implantation may be directly performed on a partial area of the P-type collector region 220 to form an N-type collector region 230 in contact with the P-type collector region 220, where the ion implantation energy of directly performing N-type doped ion implantation on the partial area of the P-type collector region 220 is equal to the implantation energy of implanting P-type doped ions into the back surface of the silicon substrate to form the P-type collector region 220, so that the thicknesses of the N-type collector region 230 and the P-type collector region 220 are the same, and the ion implantation concentration of directly performing N-type doped ion implantation on the partial area of the P-type collector region 220 is greater than the implantation concentration of implanting P-type doped ions into the back surface of the silicon substrate to form the P-type collector region 220.
In one embodiment, in step S300, etching a predetermined region on the potential cut-off layer 210, and implanting N-type doping ions into the silicon carbide material after depositing the silicon carbide material to form the silicon carbide doping layer 211 in contact with the N-type collector region 230; wherein, a heterojunction structure is formed between the N-type collector region 230 and the silicon carbide doped layer 211.
In this embodiment, the silicon carbide doped layer 211 is made of an N-type silicon carbide material, and a heterojunction structure is formed between the N-type silicon carbide material and the potential cut-off layer 210, so that the potential difference between the N-type collector region 230 and the potential cut-off layer 210 can be increased, so that the built-in potential in the heterojunction structure is greater than the built-in potential of the PN junction between the P-type collector region 220 and the potential cut-off layer 210, and the phenomenon of voltage bounce in the device is eliminated.
In one embodiment, the thickness of N-type collector region 230 is the same as the thickness of P-type collector region 220.
In one embodiment, the thickness of the polysilicon layer 130 is greater than the sum of the thicknesses of the hole barrier layer 240, the P-type well region 250, and the first N-type heavily doped region 271.
In one embodiment, as shown in fig. 7, the preparation method in this embodiment further includes: a high-K dielectric layer 410 is formed between the polysilicon layer 130 and the potential blocking layer 210.
In this embodiment, in step S600, before forming the gate dielectric layer 320 at the bottom of the first deep trench, a high-K dielectric material is deposited at the bottom of the first deep trench to form the high-K dielectric layer 410, and then a gate dielectric material or a polysilicon material is deposited.
In this embodiment, by forming the high-K dielectric layer 410 between the polysilicon layer 130 and the potential cut-off layer 210, the voltage bouncing phenomenon of the device can be improved, and the turn-off loss of the device can be reduced.
In one embodiment, high-K dielectric layer 410 is a high-K dielectric material, for example, high-K dielectric layer 410 may be hafnium oxide, aluminum oxide, or the like.
In one embodiment, as shown in connection with fig. 7, high-K dielectric layer 410 is in contact with polysilicon layer 130.
In one embodiment, a P-type shield layer 420 is formed at the bottom of the first deep trench before forming a high-K dielectric layer 410 having an upper surface that does not exceed the lower surface of the hole barrier layer 240 at the bottom of the first deep trench. Referring to fig. 8, a P-type shielding layer 420 is disposed between the high-K dielectric layer 410 and the N-type drift layer 310, and the peak value of the electric field in the corner region at the bottom of the high-K dielectric layer 410 can be reduced by disposing the P-type shielding layer 420.
In one embodiment, P-type dopant ions may be implanted into the designated region after the N-type drift layer 310 is formed to form the P-type shield layer 420, and then the silicon material is epitaxially grown, and N-type dopant ions are implanted into the newly epitaxially grown silicon material to form the P-type shield layer 420 by thickening the N-type drift layer 310.
In some embodiments, the P-type shield layer 420 may have a "U" shaped structure, and the P-type shield layer 420 wraps around the bottom of the high-K dielectric layer 410, reducing the electric field peak in the corner region of the bottom of the high-K dielectric layer 410.
In some embodiments, the width of the high-K dielectric layer 410 increases gradually from the potential blocking layer 210 toward the hole barrier layer 240.
In this embodiment, since the N-type drift layer 310 is formed by epitaxially growing a silicon material and then implanting N-type dopant ions, the dopant concentration in the N-type drift layer 310 gradually increases in the direction from the potential cut-off layer 210 to the hole barrier layer 240, and by providing the high-K dielectric layer 410 with a width that gradually increases in the direction from the potential cut-off layer 210 to the hole barrier layer 240, the electric field in the N-type drift layer 310 can be balanced so that the electric field distribution is more uniform.
In one embodiment, the schottky contact is formed between the collector 110 and the N-type collector region 230, and since the potential difference between the N-type collector region 230 and the potential blocking layer 210 is small, the P-type collector region 220 will not inject holes in the initial stage of device conduction, so that by setting the schottky contact between the collector 110 and the N-type collector region 230, the conduction potential of the N-type collector region 230 can be increased, thereby suppressing the occurrence of the voltage rebound phenomenon of the device.
In one embodiment, the concentration of N-type dopant ions within the potential blocking layer 210 is greater than the concentration of N-type dopant ions within the N-type drift layer 310 and less than the concentration of N-type dopant ions within the hole barrier layer 240.
In this embodiment, in order to avoid the punch-through of the device, the potential cut-off layer 210 with a doping concentration greater than that of the N-type drift layer 310 is provided, and the hole barrier layer 240 is provided between the N-type drift layer 310 and the P-type well region 250, so that holes can be collected below the hole barrier layer 240, and the effect of enhancing the conductivity modulation is achieved.
The embodiment of the application also provides a heterojunction reverse-conduction insulated gate bipolar transistor, which is prepared by the preparation method of any one of the embodiments.
In this embodiment, as shown in fig. 4, a hole barrier layer 240 is formed on the front surface of the N-type drift layer 310, and a gate dielectric layer 320 is formed on the front surface of the N-type drift layer 310, the gate dielectric layer 320 includes a polysilicon layer 130, the gate electrode can contact the polysilicon layer 130 through a through hole on the gate dielectric layer 320, a P-type well region 250 is formed on the hole barrier layer 240, and a first P-type heavily doped region 261 and a first N-type heavily doped region 271 are formed on the P-type well region 250. The upper surfaces of the first P-type heavily doped region 261 and the first N-type heavily doped region 271 are flush with the upper surface of the gate dielectric layer 320 and are both in contact with the emitter 120. The back surface of the N-type drift layer 310 is formed with a potential cut-off layer 210 and a silicon carbide doped layer 211, the back surface of the silicon carbide doped layer 211 is formed with an N-type collector region 230, and the back surface of the potential cut-off layer 210 is formed with a P-type collector region 220. The silicon carbide doped layer 211 is made of an N-type silicon carbide material, a heterojunction structure is formed between the N-type silicon carbide material and the potential cut-off layer 210, and a heterojunction structure is formed between the silicon carbide doped layer 211 and the N-type collector region 230, so that the built-in potential in the device can be increased, and is greater than the built-in potential between the P-type collector region 220 and the potential cut-off layer 210, and the voltage rebound phenomenon in the device is eliminated.
In one embodiment, the collector 110 is in contact with the N-type collector region 230 and the P-type collector region 220, schottky contact is formed between the collector 110 and the N-type collector region 230, and since the potential difference between the N-type collector region 230 and the potential cut-off layer 210 is small, holes are not injected into the P-type collector region 220 in the initial stage of device conduction, so that by setting schottky contact between the collector 110 and the N-type collector region 230, the conduction potential of the N-type collector region 230 can be increased, thereby suppressing the occurrence of the voltage bouncing phenomenon of the device.
The embodiment of the application also provides a chip which comprises the heterojunction reverse-conduction insulated gate bipolar transistor prepared by the preparation method according to any one of the embodiments.
In this embodiment, the chip includes a chip substrate, and one or more heterojunction reverse-conducting insulated gate bipolar transistors are disposed on the substrate, where the heterojunction reverse-conducting insulated gate bipolar transistors may be prepared by the preparation method in any of the foregoing embodiments, or the heterojunction reverse-conducting insulated gate bipolar transistors in any of the foregoing embodiments may be disposed on the chip substrate.
In one specific application embodiment, other related semiconductor devices can also be integrated on the chip substrate to form an integrated circuit with the heterojunction reverse-conducting insulated gate bipolar transistor.
In one specific application embodiment, the chip may be a switching chip or a driving chip.
The beneficial effects of the embodiment of the application are that: the front surface of the N-type drift layer is sequentially provided with a hole barrier layer and a P-type well region, a first P-type heavily doped region and a first N-type heavily doped region which are contacted with an emitter are formed on the P-type well region, the back surface of the N-type drift layer is provided with a potential cut-off layer, a silicon carbide doped layer, an N-type collecting region and a P-type collecting region which are contacted with a collector, the polysilicon layer is isolated from the hole barrier layer, the P-type well region, the first N-type heavily doped region and the emitter through a gate dielectric layer, a heterojunction structure is arranged between the silicon carbide doped layer and the potential cut-off layer, and a heterojunction structure is arranged between the silicon carbide doped layer and the N-type collecting region, so that the built-in potential in the device can be improved, and the built-in potential is larger than that between the P-type collecting region and the potential cut-off layer, thereby eliminating the voltage rebound phenomenon in the device.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of each doped region and device is illustrated, and in practical application, the above-described function allocation may be performed by different doped regions and devices according to needs, i.e. the internal structure of the device is divided into different doped regions, so as to perform all or part of the above-described functions. The doped regions and the devices in the embodiments can be integrated in one unit, or each unit can exist alone physically, or two or more units can be integrated in one unit.
In addition, the specific names of the doped regions and the devices are only used for distinguishing the doped regions and the devices from each other, and are not used for limiting the protection scope of the application.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
In addition, each doped region in each embodiment of the present application may be integrated in one unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.

Claims (10)

1. The preparation method of the heterojunction reverse-conduction insulated gate bipolar transistor is characterized by comprising the following steps of:
p-type doping ions and N-type doping ions are respectively injected into the first doping region and the second doping region on the front surface of the silicon substrate to form a P-type collector region and an N-type collector region;
epitaxially growing a silicon material on the P-type collector region and the N-type collector region, and injecting N-type doping ions to form a potential cut-off layer;
etching a preset area on the potential cut-off layer to form a groove, and implanting N-type doping ions to form a silicon carbide doped layer after epitaxially growing a silicon carbide material inside and outside the groove; the silicon carbide doping layer and the potential cut-off layer are of a heterojunction structure, and the silicon carbide doping layer and the N-type collector region are of a heterojunction structure;
epitaxially depositing a silicon layer on the silicon carbide doped layer and the potential cut-off layer, and forming an N-type drift layer, a hole barrier layer and a P-type well region through a plurality of ion implantation processes;
injecting P-type doping ions and N-type doping ions into a first preset region and a second preset region on the P-type well region respectively to form a first P-type heavily doped region and a first N-type heavily doped region;
etching a third preset area on the P-type well region to form a first deep groove, and forming a grid dielectric layer on the inner wall of the first deep groove;
depositing a polysilicon material on the gate dielectric layer to form a polysilicon layer, and continuing to deposit the gate dielectric material after forming the polysilicon layer so that the gate dielectric layer wraps the polysilicon layer;
and forming an emitter electrode in contact with the first P-type heavily doped region and the first N-type heavily doped region, forming a collector electrode in contact with the P-type collector region and the N-type collector region, and forming a grid electrode in contact with the polycrystalline silicon layer.
2. The method for manufacturing a heterojunction reverse-conduction insulated gate bipolar transistor according to claim 1, further comprising:
forming a high-K dielectric layer with the upper surface not exceeding the lower surface of the hole barrier layer at the bottom of the first deep groove; the high-K dielectric layer is positioned between the polysilicon layer and the N-type drift layer.
3. The method of fabricating a heterojunction reverse-conducting insulated gate bipolar transistor of claim 2, further comprising, before forming a high-K dielectric layer having an upper surface that does not exceed a lower surface of the hole barrier layer at a bottom of the first deep trench:
forming a P-type shielding layer at the bottom of the first deep groove; the P-type shielding layer is positioned between the high-K dielectric layer and the N-type drift layer.
4. The method of manufacturing a heterojunction reverse-conducting insulated gate bipolar transistor according to claim 2, wherein the width of the high-K dielectric layer gradually increases from the potential cut-off layer toward the hole barrier layer.
5. The method of manufacturing a heterojunction reverse-conduction insulated gate bipolar transistor according to claim 1, wherein schottky contact is formed between the N-type collector region and the collector.
6. The method of manufacturing a heterojunction reverse-conduction insulated gate bipolar transistor according to claim 1, wherein the concentration of N-type dopant ions in the potential cut-off layer is greater than the concentration of N-type dopant ions in the N-type drift layer and less than the concentration of N-type dopant ions in the hole barrier layer.
7. The method of manufacturing a heterojunction reverse-conduction insulated gate bipolar transistor according to claim 1, wherein the thickness of the N-type collector region is the same as the thickness of the P-type collector region.
8. The method of fabricating a heterojunction reverse-conducting insulated gate bipolar transistor of claim 2, wherein said high-K dielectric layer is in contact with said polysilicon layer.
9. A heterojunction reverse-conducting insulated gate bipolar transistor characterized in that the heterojunction reverse-conducting insulated gate bipolar transistor is prepared by the preparation method of the heterojunction reverse-conducting insulated gate bipolar transistor according to any one of claims 1-8.
10. A chip comprising a heterojunction reverse-conducting insulated gate bipolar transistor prepared by the preparation method of any one of claims 1-8.
CN202311834862.XA 2023-12-28 2023-12-28 Heterojunction reverse-conduction insulated gate bipolar transistor, preparation method thereof and chip Pending CN117497409A (en)

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