CN106783983A - Insulated gate bipolar transistor device and manufacturing method thereof - Google Patents
Insulated gate bipolar transistor device and manufacturing method thereof Download PDFInfo
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- CN106783983A CN106783983A CN201611019709.1A CN201611019709A CN106783983A CN 106783983 A CN106783983 A CN 106783983A CN 201611019709 A CN201611019709 A CN 201611019709A CN 106783983 A CN106783983 A CN 106783983A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 61
- 229920005591 polysilicon Polymers 0.000 claims abstract description 57
- 229910052751 metal Inorganic materials 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 20
- 238000002347 injection Methods 0.000 claims abstract description 14
- 239000007924 injection Substances 0.000 claims abstract description 14
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 14
- 239000010937 tungsten Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000002161 passivation Methods 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims description 57
- 239000011248 coating agent Substances 0.000 claims description 45
- 238000000576 coating method Methods 0.000 claims description 45
- 230000000873 masking effect Effects 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 24
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 16
- 230000003647 oxidation Effects 0.000 claims description 11
- 238000007254 oxidation reaction Methods 0.000 claims description 11
- 238000000137 annealing Methods 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 7
- 238000001459 lithography Methods 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 3
- 238000011049 filling Methods 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 description 22
- 230000015572 biosynthetic process Effects 0.000 description 15
- 238000000151 deposition Methods 0.000 description 8
- 238000001020 plasma etching Methods 0.000 description 8
- 230000001413 cellular effect Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 210000004027 cell Anatomy 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 230000004913 activation Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- -1 boron (Boron) ion Chemical class 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 210000000170 cell membrane Anatomy 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229920003223 poly(pyromellitimide-1,4-diphenyl ether) Polymers 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides an insulated gate bipolar transistor device and a manufacturing method thereof. The front structure of the insulated gate bipolar transistor device comprises: the structure comprises a plurality of grooves on the front surface of an N-type substrate and a plurality of groove polysilicon gate structures filled in the grooves; an oxide layer dielectric film layer above the multiple groove polysilicon gate structures and side wall structures on two sides of the oxide layer dielectric film layer; a plurality of contact holes respectively located in the plurality of trench polysilicon gate structures and between adjacent trench polysilicon gate structures; the N-type doped emitter regions are positioned on two sides of the contact holes and below the side wall structures; the P-type injection region is arranged at the bottom of the contact holes; a tungsten plug filling structure filled in the plurality of contact holes; the oxide layer dielectric film layer and the front metal layer covered on the side wall structures on the two sides of the oxide layer dielectric film layer; and a surface passivation layer over the front side metal layer. According to the invention, the size of the device cell structure can be reduced, and the cell density can be improved, so that the current density per unit area can be improved, and the cost can be reduced.
Description
Technical field
The present invention relates to field of semiconductor devices, more particularly to a kind of insulated-gate bipolar transistor device and its manufacturer
Method.
Background technology
It is the main flow of current field of power electronics device with the mos semiconductor power device that IGBT, MOSFET are mark,
Wherein most representational device IGBT (Insulated Gate Bipolar Transistor), also known as insulated gate bipolar
Transistor, the compound full-control type voltage driven type being made up of BJT (double pole triode) and MOS (insulating gate type field effect tube)
Power semiconductor, driving power is small, has Metal-Oxide Semiconductor field effect transistor M OSFET (Metal- concurrently
Oxide-Semiconductor Field-Effect Transistor) high input impedance and power transistor (Power
BJT advantage of both low conduction voltage drop), it is the converter system such as friendship of 600V and the above to be highly suitable to be applied for DC voltage
The fields such as stream motor, frequency converter, Switching Power Supply, lighting circuit, Traction Drive.Its as novel power transistor typical generation
Table, enjoys favor in middle high-pressure application field.According to the technique classification of IGBT, be typically divided into PT-IGBT (punch),
The structures such as NPT-IGBT (non-punch), FS-IGBT (field cut-off type), RC-IGBT (inverse conductivity type), are mainly reflected in Withstand voltage layer
The structure and manufacture method difference of structure change and device collector.
Because IGBT device is (overleaf to integrate a PNP crystal from the structural development of MOSFET power devices
Pipe), so the structure and manufacture method of its MOSFET part are substantially similar to MOSFET element.But due to by manufacturing process
Influence, using normal lithography alignment technique, the cellular size of 600V high pressure trench gates IGBT is general in more than 3um, makes device
The current density lifting of unit area is restricted.
To sum up, it is necessary to propose that one kind can reduce cellular size, to improve the IGBT device knot of unit area current density
Structure and fabrication scheme.
The content of the invention
In view of this, the present invention provides a kind of insulated-gate bipolar transistor device and its manufacture method, can reduce cellular
Physical dimension, improves the current density of unit area.
According to the first aspect of the invention, there is provided a kind of insulated-gate bipolar transistor device, the front knot of the device
Structure includes：The positive multiple grooves of N-type substrate and the multiple trench polysilicon Si-gate structures being filled in the multiple groove；Institute
State the oxide layer media coating of multiple trench polysilicon Si-gate superstructures and its sidewall structure of both sides；It is located at respectively the multiple
The multiple contact holes between trench polysilicon Si-gate structure in trench polysilicon Si-gate structure, adjacent；Positioned at the multiple contact hole
Both sides and the n-type doping emitter region below the sidewall structure；The p-type injection region of the multiple contact hole bottom；Filling
Tungsten plug interstitital texture in the multiple contact hole；Covered on the sidewall structure of the oxide layer media coating and its both sides
Front metal layer；And the surface passivation layer above the front metal layer.
Further, the insulated-gate bipolar transistor device is field cut-off type/punch/non-punch/inverse conductivity type
Insulated-gate bipolar transistor device.
According to a second aspect of the present invention, there is provided a kind of manufacture method of insulated-gate bipolar transistor device, including：In N
Thermally grown pad oxide on type substrate, as the cushion of the masking layer of etching groove；One layer is deposited on the pad oxide
Silicon nitride film layer, and the silicon nitride film layer is etched using trench lithography plate, form the masking layer of etching groove；Covered based on described
Covering layer carries out etching groove, forms multiple grooves；Multiple trench polysilicon Si-gate structures are generated in the multiple groove；Deposition oxygen
Change layer dielectric layer, and the oxide layer media coating and the masking layer are performed etching, retain the multiple trench polysilicon
Oxide layer media coating above silicon gate structure, forms multiple ion implanting windows；Entered by the multiple ion implanting window
Row ion implanting, forms PN junction and n-type doping emitter region；It is situated between in the oxide layer of the multiple trench polysilicon Si-gate superstructure
Plasma membrane layer both sides form sidewall structure, etch to form multiple contact holes with based on the sidewall structure autoregistration；Described many
Ion implanting is carried out at individual contact hole and annealing is activated, form p-type injection region；Tungsten is filled in the multiple contact hole,
Form tungsten plug interstitital texture；Front metal layer is formed, surface passivation layer is generated on the metal layer, and etching forms front side emitter pole
Package window；Carry out the making of backside structure.
Further, multiple trench polysilicon Si-gate structures are generated in the multiple groove, including：In the multiple groove
The thermally grown gate oxidation dielectric layer in surface；The deposit polycrystalline silicon on the gate oxidation dielectric layer of the multiple groove；To the polysilicon
Perform etching, form trench polysilicon Si-gate structure.
Further, the oxide layer media coating and the masking layer are performed etching, retains the multiple groove many
The oxide layer media coating of crystal silicon grid superstructure, forms multiple ion implanting windows, including：On the etching removal masking layer
The oxide layer media coating of side, retains the oxide layer media coating of the multiple trench polysilicon Si-gate superstructure；Etching removal
The masking layer, formed between the oxide layer media coating of the multiple trench polysilicon Si-gate superstructure for retaining it is multiple from
Son injection window.
Further, side wall knot is formed in the oxide layer media coating both sides of the multiple trench polysilicon Si-gate superstructure
Structure, multiple contact holes are formed to be etched based on the sidewall structure autoregistration, including：One layer of side wall oxide layer film layer of deposition；
The side wall oxide layer film layer is performed etching, retains the oxide layer media coating of the multiple trench polysilicon Si-gate superstructure
The side wall oxide layer of both sides, forms sidewall structure；Oxidation layer dielectric based on two neighboring trench polysilicon Si-gate superstructure
The contact hole window formed between the side wall of layer carries out contact hole etching, forms multiple contact holes.
Further, the insulated-gate bipolar transistor device is field cut-off type/punch/non-punch/inverse conductivity type
Insulated-gate bipolar transistor device.
Such scheme of the invention, forms sidewall structure, and contacted by depositing side wall oxide layer and etching
Hole etches, and can adjust side wall thicknesses by controlling the thickness and plasma etching amount of side wall oxide layer, so that, control contact
Hole realizes autoregistration of the contact hole to trench polysilicon Si-gate structure to the spacing of groove and the size of contact hole.The present invention
Can reduce the size of device structure cell, improve cellular density, so as to improve the current density of unit area, reduce chip into
This, improves cost performance.
Described above is only the general introduction of technical solution of the present invention, in order to better understand technological means of the invention,
And can be practiced according to the content of specification, below with presently preferred embodiments of the present invention and coordinate accompanying drawing describe in detail as after.
Brief description of the drawings
The accompanying drawing for constituting a part of the invention is used for providing a further understanding of the present invention, schematic reality of the invention
Apply example and its illustrate, for explaining the present invention, not constitute inappropriate limitation of the present invention.In the accompanying drawings：
Fig. 1 shows that the Facad structure of insulated-gate bipolar transistor device according to an embodiment of the invention is illustrated
Figure.
Fig. 2 shows the flow chart of the manufacture method of insulated gate bipolar transistor according to an embodiment of the invention.
Fig. 3 shows the knot after Grown pad oxide and silicon nitride film layer according to an embodiment of the invention
Structure schematic diagram.
Fig. 4 shows that formation etching groove after photoetching is carried out to silicon nitride film layer according to an embodiment of the invention is covered
Cover the structural representation of layer.
Fig. 5 shows and according to an embodiment of the invention carries out the structural representation after etching groove forms multiple grooves
Figure.
Fig. 6 shows the structure after multiple flute surfaces generation gate oxidation dielectric layer according to an embodiment of the invention
Schematic diagram.
Fig. 7 shows the structural representation of formation trench polysilicon Si-gate structure according to an embodiment of the invention.
Fig. 8 shows the structural representation that deposited after oxide layer media coating according to an embodiment of the invention.
After Fig. 9 shows the oxide layer media coating above etching removal masking layer according to an embodiment of the invention
Structural representation.
Figure 10 shows the structural representation after etching removal masking layer according to an embodiment of the invention.
Figure 11 shows the structural representation after formation PN junction according to an embodiment of the invention.
Figure 12 forms n-type doping emitter region after showing N+ emitter stages ion implanting according to an embodiment of the invention
Structural representation afterwards.
Figure 13 shows the structural representation after one layer of side wall oxide layer film layer of deposition according to an embodiment of the invention.
Figure 14 shows the structural representation after formation side wall according to an embodiment of the invention.
Figure 15 shows that ion implanting according to an embodiment of the invention and annealing activation form the knot behind p-type injection region
Structure schematic diagram.
Figure 16 shows the structural representation after formation tungsten plug interstitital texture according to an embodiment of the invention.
Figure 17 shows the structural representation after formation front metal layer according to an embodiment of the invention.
Figure 18 is shown according to a structure for the field cut-off type insulated gate bipolar transistor of specific embodiment of the invention
Schematic diagram.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with the specific embodiment of the invention and
Corresponding accompanying drawing is clearly and completely described to technical solution of the present invention.Obviously, described embodiment is only the present invention one
Section Example, rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art are not doing
Go out the every other embodiment obtained under the premise of creative work, belong to the scope of protection of the invention.
Below in conjunction with brief description of the drawings insulated-gate bipolar transistor device of the invention.
Fig. 1 shows that the Facad structure of insulated-gate bipolar transistor device according to an embodiment of the invention is illustrated
Figure.
As shown in figure 1, the insulated-gate bipolar transistor device (abbreviation IGBT device) is groove-shaped IGBT device, should
The Facad structure of device includes：The positive multiple grooves 104 of N-type substrate and the multiple being filled in the multiple groove 104
Trench polysilicon Si-gate structure 106；The surface of groove 104 (bottom and side wall) is gate oxidation medium and trench polysilicon Si-gate structure between
Layer 105；The oxide layer media coating 107 of the top of the multiple trench polysilicon Si-gate structure 106 and its sidewall structure of both sides
112；PN junction 109 between adjacent trenches；Respectively in the multiple trench polysilicon Si-gate structure, adjacent trench polisilicon
Multiple contact holes 114 between grid structure；Mixed positioned at the multiple contact hole both sides and the N-type below the sidewall structure
Miscellaneous emitter region 110；The p-type injection region 115 of the multiple contact hole bottom；It is filled in the tungsten in the multiple contact hole 114
Plug interstitital texture 116；The front metal layer covered on the sidewall structure 112 of the oxide layer media coating 107 and its both sides
117；And the surface passivation layer 118 above the front metal layer.
The sidewall structure 112 of the both sides of oxide layer media coating 107 of the top of the multiple trench polysilicon Si-gate structure 106 is
Side wall oxide layer and plasma etching formation is carried out by being deposited on oxide layer media coating, etched with can be used for autoregistration
The multiple contact hole 114 is formed, and contact can be adjusted by various sizes of lateral wall width (side wall oxidated layer thickness)
The spacing of groove 114 and the size of contact hole 114 are arrived in hole 114.The cell region of device is by side wall 112 and oxide layer media coating
107 form dielectric structure, reach autoregistration effect of the contact hole to trench polysilicon Si-gate structure.By controlling side wall oxide layer
Thickness, can narrow down to less than 0.1 μm by the spacing of contact hole to groove, and the size of structure cell can narrow down to less than 2 μm.
It is exhausted that the insulated-gate bipolar transistor device is specifically as follows a cut-off type/punch/non-punch/inverse conductivity type
Edge grid bipolar transistor device.
Fig. 2 shows the flow of the manufacture method of insulated-gate bipolar transistor device according to an embodiment of the invention
Figure.
As shown in Fig. 2 the manufacture method of the insulated-gate bipolar transistor device, comprises the following steps：
Step S1, the thermally grown pad oxide 102 in N-type substrate 101.
The data of the parameter requests such as the voltage specification according to needed for device, binding isotherm and emulation, choose suitable substrate
Material specification (such as final thickness thinning of resistivity, epitaxy layer thickness or FZ-wafer), if corresponding to a cut-off type
(field-stop) and the IGBT device structure such as punch (punch through), also need to confirm the specification of field cutoff layer.Example
Such as, the substrate can be n-type doping epitaxial silicon chip substrate or n type single crystal silicon piece substrate.
Step S2, one layer of silicon nitride film layer 103a of deposition on the pad oxide 102, and using trench lithography plate etching
The silicon nitride film layer, forms the masking layer 103b of etching groove.
Fig. 3 shows the knot after Grown pad oxide and silicon nitride film layer according to an embodiment of the invention
Structure schematic diagram.Fig. 4 shows and according to an embodiment of the invention silicon nitride film layer is carried out to form etching groove after photoetching
The structural representation of masking layer.
As shown in figure 3, in the thermally grown one layer of pad oxide 102 (Pad Oxide) in the front of the N-type substrate 101, as ditch
The cushion of groove etched masking layer.102 one layer of silicon nitride (Nitride) film layer 103a of redeposition on pad oxide.Such as Fig. 4
It is shown, photoetching is carried out to the silicon nitride film layer using trench lithography plate, groove figure is formed, being allowed to be formed carries out etching groove
Masking layer 103b.
Step S3, etching groove is carried out based on the masking layer 103b, form multiple grooves 104.
Fig. 5 shows and according to an embodiment of the invention carries out the structural representation after etching groove forms multiple grooves
Figure.Formed after masking layer 103b, etching groove is carried out according to masking layer 103b, as shown in figure 5, etching forms multiple grooves
104。
Step S4, the multiple trench polysilicon Si-gate structures 106 of generation in the multiple groove 104.
Further, step S4 includes step S41, S42 and S43.
Step S41, in the thermally grown gate oxidation dielectric layer 105 in the surface of the multiple groove 104.
Fig. 6 shows that the structure in multiple flute surfaces generation gate oxidation dielectric layer according to an embodiment of the invention is shown
It is intended to.As shown in fig. 6, after forming multiple grooves 104, by after the steps such as groove corners, in the surface (bottom of groove 104
And side wall) on thermally grown one layer of gate oxidation dielectric layer 105 (Gate Oxide).
Step S42, the deposit polycrystalline silicon on the gate oxidation dielectric layer 105 of the multiple groove 104.
Wherein it is possible to using chemical vapor deposition in multiple grooves 104 deposit polycrystalline silicon.
Step S43, the polysilicon is performed etching, form trench polysilicon Si-gate structure 106.
Fig. 7 shows the structural representation of formation trench polysilicon Si-gate structure according to an embodiment of the invention.Using
Plasma etching industrial, performs etching to the polysilicon in groove 104, forms trench polysilicon Si-gate structure 106 as shown in Figure 7
(trench poly)。
Step S5, deposited oxide layer media coating 107, and to the oxide layer media coating 107 and the masking layer
103b is performed etching.
Step S5 can specifically include step S51, S52 and S53；
Step S51, deposited oxide layer media coating 107.
Fig. 8 shows the structural representation that deposited after oxide layer media coating according to an embodiment of the invention.
Using chemical vapor deposition method, the redeposited layer of oxide layer media coating 107 in the structure for having been formed.
Oxide layer media coating 107 above step S52, the etching removal masking layer 103b, retains the multiple ditch
Oxide layer media coating 107 above groove polysilicon grating structure.
After Fig. 9 shows the oxide layer media coating above etching removal masking layer according to an embodiment of the invention
Structural representation.Using plasma etching industrial, the oxide layer media coating above silicon nitride masking layer 103b is etched away, retained
The oxide layer media coating 107 of the top of the multiple trench polysilicon Si-gate structure 106, i.e. etching stopping is in silicon nitride masking layer
103b, as shown in Figure 9.
Step S53, the etching removal masking layer 103b.
Figure 10 shows the structural representation after etching removal masking layer according to an embodiment of the invention.Using wet method
Etching technics, etching removal silicon nitride masking layer 103b is that follow-up ion implanting etc. opens window, as shown in Figure 10, is being protected
Multiple ion implanting windows are formed between the oxide layer media coating 107 of the top of multiple trench polysilicon Si-gate structures 106 stayed
108。
Step S6, ion implanting is carried out, form PN junction and n-type doping emitter region；
Figure 11 shows the structural representation after formation PN junction according to an embodiment of the invention.Figure 12 shows root
According to the structural representation after formation n-type doping emitter region after the N+ emitter stage ion implantings of one embodiment of the invention.
As shown in figure 11, by multiple ion implanting windows 108, trap technique, shape are pushed away using full wafer ion implanting and diffusion
Into PN junction 109 so as to form p-well (region between the two neighboring trench polysilicon Si-gate structure in PN junction top), wherein, injection
Ion is boron (Boron) ion.As shown in figure 12, by multiple ion implanting windows 108 carry out N+ emitter stages ion implanting and
Diffusion annealing, forms n-type doping emitter region 110, i.e. inject N between multiple grooves by multiple ion implanting windows 108
+ ion, forms n-type doping emitter region 110, wherein, the N+ ions of injection are arsenic (arsenic) ion.
Step S7, the both sides of the oxide layer media coating 107 formation side in the top of the multiple trench polysilicon Si-gate structure 106
Wall construction 112, etches to form multiple contact holes with based on the sidewall structure autoregistration.
Further, step S7 can specifically include step S71, S72 and S73.
Step S71, one layer of side wall oxide layer film layer 111 of deposition.
Figure 13 shows the structural representation after deposition side wall oxide layer film layer according to an embodiment of the invention.Using
Chemical vapor deposition, deposits one layer of side wall oxide layer (Space oxide) film layer 111.
Step S72, the side wall oxide layer film layer 111 is performed etching, retain the multiple trench polysilicon Si-gate structure
The side wall oxide layer of the both sides of oxide layer media coating 107 of 106 tops, forms sidewall structure 112.
Figure 14 shows the structural representation after formation sidewall structure according to an embodiment of the invention.Such as Figure 14 institutes
Show, plasma etching is carried out to side wall oxide layer 111, be only remained in the oxide layer of the top of multiple trench polysilicon Si-gate structures 107
The side wall oxide layer film layer 111 of the both sides of media coating 107, forms side wall (Sidewall) structure 112.
The side wall of step S73, the oxide layer media coating 107 based on the top of two neighboring trench polysilicon Si-gate structure 106
The contact hole window 113 formed between 112 carries out contact hole etching, forms multiple contact holes.
Specifically, contact hole etching is carried out using plasma etching industrial, forms multiple contact holes 114.
Above-mentioned steps autocollimatic forms the contact hole window of N+ emitter stages over the ground, by the thickness for adjusting side wall oxide layer 111
Degree and plasma etching amount, can obtain various sizes of lateral wall width, so as to determine contact hole 114 between groove 114
Away from the size with contact hole 114.The cell region of device does not need litho pattern, but by side wall oxide layer 111 and oxide layer
The dielectric structure that media coating 107 is formed, reaches autoregistration effect of the contact hole to trench polysilicon Si-gate structure.By control
The thickness of side wall oxide layer, can narrow down to less than 0.1 μm by the spacing of contact hole to groove, and the size of structure cell can reduce
To less than 2 μm.
Step S8, ion implanting and annealing activation are carried out at the multiple contact hole 114, form p-type injection region.
Figure 15 shows that ion implanting according to an embodiment of the invention and annealing activation form the knot behind p-type injection region
Structure schematic diagram.As shown in figure 15, after the completion of contact hole etching, multiple contact holes 114 are formed, contact hole p-type ion is carried out therewith
Injection and annealing activation, form p-type injection region 115.
Step S9, tungsten is filled in the multiple contact hole 114, form tungsten plug interstitital texture 116.
Figure 16 shows the structural representation after formation tungsten plug interstitital texture according to an embodiment of the invention.Such as Figure 16
It is shown, tungsten is filled in the contact hole 114 using magnetron sputtering and chemical vapor deposition method, and to excess surface
W film carve, and only retains tungsten plug interstitital texture 116 in the contact hole, used as contact pore electrod.
Step S10, formation front metal layer 117, generate surface passivation layer 118 on the metal layer, and etching forms front
Emitter stage package window.
Figure 17 shows the structural representation after formation front metal layer according to an embodiment of the invention.Such as Figure 17 institutes
Show, using magnetron sputtering technique, carry out front side emitter pole (Emitter) metal deposit, metal layer lithography and etching, form front
Metal-layer structure 117, as front side emitter pole.Surface passivation layer 118 is generated on front metal layer 117, by different components
It is required that, can select to generate the surface passivation layer (such as Kapton) of organic media, or the table for generating inorganic medium
Face passivation layer (such as silicon nitride film), and carry out photoetching or etching forms final front side emitter pole package window, so far device
Part is positive to complete, and forms the Facad structure of insulated-gate bipolar transistor device as shown in Figure 1.
Step S11, the making for carrying out backside structure.
For back process flow, can be according to field cut-off type (field-stop), non-punch (non punch
Through), the classification such as punch (punch through) and inverse conductivity type (Reverse Conducting), is carried out corresponding
Structure prepare.For example, Figure 18 shows the insulated gate bipolar transistor so that (field-stop) type IGBT is ended in field as an example
Structural representation, as shown in figure 18, its backside structure includes：N-type field cut-off region 120, p-type collecting zone 121 and back metal
Layer 122.
The manufacture method of above-mentioned insulated-gate bipolar transistor device of the invention, can be used for a cut-off type/break-through
The manufacture of type/non-punch/inverse conductivity type insulated-gate bipolar transistor device.
The structure and its manufacture method to insulated gate bipolar transistor of the invention are described above.According to this hair
Bright such scheme, sidewall structure is formed by depositing side wall oxide layer and etching, and carries out contact hole etching, can be by control
The thickness and plasma etching amount of side wall oxide layer processed adjusts side wall thicknesses so that, the spacing of control contact hole to groove with
And the size of contact hole, realize autoregistration of the contact hole to trench polysilicon Si-gate structure.The present invention can reduce device cellular knot
The size of structure, improves cellular density, so as to improve the current density of unit area, reduces chip cost, improves cost performance.
It should be noted that in the case where not conflicting, the embodiment in the present invention and the feature in embodiment can phases
Mutually combination.
The above, is only presently preferred embodiments of the present invention, and any formal limitation is not made to the present invention, according to
Any simple modification, equivalent variations and the modification made to above example according to technical spirit of the invention, still fall within this hair
In the range of bright technical scheme.
Claims (7)
1. a kind of insulated-gate bipolar transistor device, it is characterised in that the front of the insulated-gate bipolar transistor device
Structure includes：
The positive multiple grooves of N-type substrate and the multiple trench polysilicon Si-gate structures being filled in the multiple groove；
The oxide layer media coating of the multiple trench polysilicon Si-gate superstructure and its sidewall structure of both sides；
Multiple contacts respectively in the multiple trench polysilicon Si-gate structure, between adjacent trench polysilicon Si-gate structure
Hole；
N-type doping emitter region positioned at the multiple contact hole both sides and below the sidewall structure；
The p-type injection region of the multiple contact hole bottom；
It is filled in the tungsten plug interstitital texture in the multiple contact hole；
The front metal layer covered on the sidewall structure of the oxide layer media coating and its both sides；
And the surface passivation layer above the front metal layer.
2. insulated-gate bipolar transistor device as claimed in claim 1, it is characterised in that the insulated gate bipolar crystal
Tube device is field cut-off type/punch/non-punch/inverse conductivity type insulated-gate bipolar transistor device.
3. a kind of manufacture method of insulated-gate bipolar transistor device, it is characterised in that including：
The thermally grown pad oxide in N-type substrate, as the cushion of the masking layer of etching groove；
One layer of silicon nitride film layer is deposited on the pad oxide, and the silicon nitride film layer, shape are etched using trench lithography plate
Into the masking layer of etching groove；
Etching groove is carried out based on the masking layer, multiple grooves are formed；
Multiple trench polysilicon Si-gate structures are generated in the multiple groove；
Deposited oxide layer media coating, and the oxide layer media coating and the masking layer are performed etching；
Ion implanting is carried out, PN junction and n-type doping emitter region is formed；
Sidewall structure is formed in the oxide layer media coating both sides of the multiple trench polysilicon Si-gate superstructure, with based on described
Sidewall structure autoregistration ground etching forms multiple contact holes；
Ion implanting is carried out at the multiple contact hole and annealing is activated, form p-type injection region；
Tungsten is filled in the multiple contact hole, tungsten plug interstitital texture is formed；
Front metal layer is formed, surface passivation layer is generated on the metal layer, and etching forms front side emitter pole package window；
Carry out the making of backside structure.
4. the manufacture method of insulated-gate bipolar transistor device as claimed in claim 3, it is characterised in that the multiple
Multiple trench polysilicon Si-gate structures are generated in groove, including：
In the thermally grown gate oxidation dielectric layer of the multiple flute surfaces；
The deposit polycrystalline silicon on the gate oxidation dielectric layer of the multiple groove；
The polysilicon is performed etching, trench polysilicon Si-gate structure is formed.
5. the manufacture method of the insulated-gate bipolar transistor device as described in claim 3 or 4, it is characterised in that to described
Oxide layer media coating and the masking layer are performed etching, including：
Oxide layer media coating above the etching removal masking layer, retains the multiple trench polysilicon Si-gate superstructure
Oxide layer media coating；
The masking layer of the etching removal etching groove, in the oxide layer of the multiple trench polysilicon Si-gate superstructure for retaining
Multiple ion implanting windows are formed between media coating.
6. the manufacture method of the insulated-gate bipolar transistor device as described in claim any one of 3-5, it is characterised in that
The oxide layer media coating both sides of the multiple trench polysilicon Si-gate superstructure form sidewall structure, with based on the side wall knot
Structure autoregistration ground etching forms multiple contact holes, including：
One layer of side wall oxide layer film layer of deposition；
The side wall oxide layer film layer is performed etching, retains the oxide layer medium of the multiple trench polysilicon Si-gate superstructure
The side wall oxide layer of film layer both sides, forms sidewall structure；
The contact hole window formed between the side wall of the oxide layer media coating based on two neighboring trench polysilicon Si-gate superstructure
Mouth carries out contact hole etching, forms multiple contact holes.
7. the manufacture method of the insulated-gate bipolar transistor device as described in claim any one of 3-6, it is characterised in that institute
It is field cut-off type/punch/non-punch/inverse conductivity type insulated gate bipolar transistor device to state insulated-gate bipolar transistor device
Part.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108878290A (en) * | 2018-07-18 | 2018-11-23 | 厦门芯代集成电路有限公司 | A kind of slot grid igbt chip and its manufacturing method |
| CN110752149A (en) * | 2019-09-18 | 2020-02-04 | 珠海格力电器股份有限公司 | Power device processing method |
| CN112103186A (en) * | 2020-09-22 | 2020-12-18 | 深圳市芯电元科技有限公司 | Process method for improving cell density of trench MOSFET and trench MOSFET structure |
| CN113035948A (en) * | 2019-12-24 | 2021-06-25 | 珠海格力电器股份有限公司 | Power device, power electronic equipment and manufacturing method of power device |
| CN114628247A (en) * | 2022-05-12 | 2022-06-14 | 北京芯可鉴科技有限公司 | IGBT device manufacturing method and IGBT device |
| WO2024212537A1 (en) * | 2023-04-14 | 2024-10-17 | 无锡华润上华科技有限公司 | Insulated gate bipolar transistor and manufacturing method therefor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1489214A (en) * | 2002-08-30 | 2004-04-14 | ��ʿͨ��ʽ���� | Semiconductor device and manufacturing method thereof |
| US20120015492A1 (en) * | 2001-02-19 | 2012-01-19 | Hitachi Tobu Semiconductor, Ltd. | Insulated gate type semiconductor device and method for fabricating the same |
-
2016
- 2016-11-18 CN CN201611019709.1A patent/CN106783983A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120015492A1 (en) * | 2001-02-19 | 2012-01-19 | Hitachi Tobu Semiconductor, Ltd. | Insulated gate type semiconductor device and method for fabricating the same |
| CN1489214A (en) * | 2002-08-30 | 2004-04-14 | ��ʿͨ��ʽ���� | Semiconductor device and manufacturing method thereof |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108878290A (en) * | 2018-07-18 | 2018-11-23 | 厦门芯代集成电路有限公司 | A kind of slot grid igbt chip and its manufacturing method |
| CN110752149A (en) * | 2019-09-18 | 2020-02-04 | 珠海格力电器股份有限公司 | Power device processing method |
| CN113035948A (en) * | 2019-12-24 | 2021-06-25 | 珠海格力电器股份有限公司 | Power device, power electronic equipment and manufacturing method of power device |
| CN113035948B (en) * | 2019-12-24 | 2022-08-30 | 珠海格力电器股份有限公司 | Power device, power electronic equipment and manufacturing method of power device |
| CN112103186A (en) * | 2020-09-22 | 2020-12-18 | 深圳市芯电元科技有限公司 | Process method for improving cell density of trench MOSFET and trench MOSFET structure |
| CN112103186B (en) * | 2020-09-22 | 2022-03-15 | 深圳市芯电元科技有限公司 | Process method for improving cell density of trench MOSFET and trench MOSFET structure |
| CN114628247A (en) * | 2022-05-12 | 2022-06-14 | 北京芯可鉴科技有限公司 | IGBT device manufacturing method and IGBT device |
| WO2024212537A1 (en) * | 2023-04-14 | 2024-10-17 | 无锡华润上华科技有限公司 | Insulated gate bipolar transistor and manufacturing method therefor |
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