CN110752149A - Power device processing method - Google Patents
Power device processing method Download PDFInfo
- Publication number
- CN110752149A CN110752149A CN201910883126.0A CN201910883126A CN110752149A CN 110752149 A CN110752149 A CN 110752149A CN 201910883126 A CN201910883126 A CN 201910883126A CN 110752149 A CN110752149 A CN 110752149A
- Authority
- CN
- China
- Prior art keywords
- hard mask
- etching
- ion implantation
- substrate
- window
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
Abstract
The invention relates to the technical field of semiconductors, in particular to a power device processing method, which comprises the following steps: arranging a hard mask on a substrate, and photoetching an etching window on the hard mask; performing groove etching on the substrate through the etching window, and reserving the hard mask; carrying out transverse etching on the hard mask to form an ion implantation window; and carrying out an N + ion implantation process, forming an N-type conducting layer corresponding to the etched area of the hard mask, and etching the formed ion implantation window, so that the technical difficulty of N + process photoetching is reduced, and the hard mask carries out self-alignment blocking on N + ion implantation, thereby solving the problem of deviation of N + ion implantation and ensuring the electrical property and the stability of dynamic parameters of the power device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a power device processing method.
Background
In the process of manufacturing the power device IGBT or MOSFET, there is an N + implant to form the Emitter (or Source). With the continuous development of chip technology, the chip structure becomes smaller and smaller, and the requirements on the photoetching line width and the alignment technology are higher and higher. The line width of the N + structure is very small, photoetching misalignment is easy to occur, N + ion implantation misalignment is caused, and the N + ion implantation misalignment can greatly influence the electrical property and the dynamic parameters of the device.
Disclosure of Invention
The invention aims to provide a power device processing method which can solve the problem of offset of N + ion implantation in the power device processing process.
The embodiment of the invention is realized by the following steps:
a method of processing a power device, comprising:
arranging a hard mask on a substrate, and photoetching an etching window on the hard mask;
performing groove etching on the substrate through the etching window, and reserving the hard mask;
carrying out transverse etching on the hard mask to form an ion implantation window;
and performing an N + ion implantation process to form an N-type conducting layer corresponding to the etched area of the hard mask.
Further, in an embodiment of the present invention, the substrate is grown with an oxide layer and densified, and the densified oxide layer is used as the hard mask.
Further, in an embodiment of the present invention, the laterally etching the hard mask includes growing a sacrificial oxide layer on a surface of the hard mask.
Further, in an embodiment of the present invention, the hard mask is laterally etched by using a wet etching process, and the size of the ion implantation window is controlled by etching time.
Further, in an embodiment of the present invention, after the hard mask on both sides of the trench is laterally etched, a gate oxide layer and a polysilicon growing process are performed, and the polysilicon is etched.
Further, in an embodiment of the present invention, after the polysilicon etching is completed, P-type impurity implantation and well pulling are performed on the substrate, and then N + ion implantation and annealing processes are performed.
Further, in an embodiment of the present invention, after the N + ion implantation process, an ILD isolation layer is grown, and a lead hole is etched at a position of the ILD isolation layer corresponding to the hard mask, and the hard mask is removed by etching.
Further, in an embodiment of the present invention, after the etching of the wire hole is completed, metal pads are respectively disposed on the front surface side and the back surface side of the substrate.
The embodiment of the invention has the beneficial effects that:
the method comprises the steps of arranging a hard mask on a substrate, reserving the hard mask during groove etching, carrying out transverse etching on the hard mask, controlling the size of an ion implantation window, carrying out an N + ion implantation process, forming an N-type conducting layer corresponding to an etched area of the hard mask, and etching the formed ion implantation window, so that the technical difficulty of N + process photoetching is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1-8 are schematic flow diagrams of embodiments of the present invention.
Icon: 1-a substrate; 2-a hard mask; 3, etching a window; 4-a groove; 5-ion implantation window; a 6-N type conductive layer; 7-polycrystalline silicon; 8-P well; 9-ILD isolation layer; 10-a lead hole; 11-front metal pad layer; 12-back metal pad layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the manufacturing process of the insulated gate bipolar transistor or the metal-oxide-semiconductor field effect transistor, an emitter or a source is formed through N + ion injection, the line width of an N + structure is very small, and the scheme provides a power device processing method to solve the problem of N + deflection in the power device processing process. Arranging a hard mask 2 on a substrate 1, photoetching an etching window 3 on the hard mask 2, etching a groove 4 on the substrate 1 through the etching window 3, and reserving the hard mask 2 in the etching process of the groove 4; then, the reserved hard mask 2 is transversely etched, the etched area of the hard mask 2 serves as an ion implantation window 5, an N + ion implantation process is performed, an N-type conducting layer 6 is formed corresponding to the etched area of the hard mask 2, referring to fig. 3 and 6, the size of the N + ion window formed on the two sides of the groove 4 is guaranteed to be equal through etching of the hard mask 2, meanwhile, the hard mask 2 can block the N + ion implantation, the problem of deviation of the N + ion implantation is solved, the requirement of the N + ion implantation on the photoetching capacity is lowered, and the electrical property and the stability of dynamic parameters of the power device are guaranteed.
Example 1:
the embodiment provides a power device processing method, which comprises the following steps:
step 1: referring to fig. 1, an oxide layer is grown on a substrate 1, which is a wafer substrate; densifying the oxide layer, using the densified oxide layer as a hard mask 2, and photoetching an etching window 3 on the hard mask 2;
step 2: referring to fig. 2, the substrate 1 is etched through the etching window 3 by using the trench 4, and the hard mask 2 is remained in the etching process of the trench 4, that is, the substrate is etched only through the etching window in the etching process;
and step 3: referring to fig. 3, a sacrificial oxide layer is grown on the surface of the hard mask 2, the sacrificial oxide layer is removed by using a wet etching process, meanwhile, the hard mask 2 is laterally etched, an ion implantation window 5 is formed in an etched area of the hard mask 2, and the size of the ion implantation window 5 can be controlled by etching time;
and 4, step 4: referring to fig. 4, a gate oxide layer is grown in the trench 4, polysilicon 7 is filled in the trench, and then the polysilicon 7 is etched;
and 5: referring to fig. 5, a P-type impurity implantation and a drive-in process are performed on a substrate to form a P-well, the P-type impurity is B ions, and the hard mask 2 does not affect the implantation of the B ions due to the deeper implantation depth of the B ions;
step 6: referring to fig. 6, an N + ion implantation process is performed, arsenic ions are implanted into the ion implantation window 5 and annealed, and an N-type conductive layer 6 is formed on the substrate corresponding to the etched region of the hard mask 2, because the implantation depth of the arsenic ions is shallow, the implantation of the arsenic ions can be blocked by the coverage area of the hard mask 2, and thus the hard mask 2 can be used as a self-aligned barrier;
and 7: referring to fig. 7, an ILD isolation layer 9 is grown on the surface of the hard mask 2, and a lead hole 10 is etched at a position of the ILD isolation layer 9 corresponding to the hard mask 2, and the hard mask 2 is removed by etching, and the etching amount can be increased during the etching process of the lead hole 10 to ensure that the hard mask 2 is removed.
And 8: referring to fig. 8, a front metal pad 11 is provided on the front side of the substrate 1, and a rear metal pad 12 is provided on the rear side of the substrate 1.
In summary, the present embodiment provides a method for processing a power device, which mainly solves the problem of misalignment caused by N + ion implantation, and densifies an oxide layer on a substrate 1, a hard mask 2 is retained in an etching process of a trench 4, and the hard mask 2 is laterally etched by a wet etching process, so that ion implantation windows 5 formed on two sides of the trench 4 have the same size, and self-alignment is achieved in the N + ion implantation process, and the hard mask 2 can also block the N + ion implantation, thereby solving the problem of misalignment caused by N + ion implantation, reducing the requirement of N + ion implantation on the lithography capability, and ensuring the stability of the electrical property and dynamic parameters of the power device.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A method of processing a power device, comprising:
arranging a hard mask (2) on a substrate (1), and photoetching an etching window (3) on the hard mask (2);
etching a groove (4) on the substrate (1) through the etching window (3) and reserving the hard mask (2);
performing lateral etching on the hard mask (2) to form an ion implantation window (5);
and carrying out an N + ion implantation process, and forming an N-type conducting layer (6) corresponding to the etched region of the hard mask (2).
2. The processing method according to claim 1, characterized in that the substrate (1) is grown with an oxide layer and densified, the densified oxide layer acting as the hard mask (2).
3. The process according to claim 1, characterized in that said lateral etching of said hard mask (2) comprises a preliminary growth of a sacrificial oxide layer on the surface of said hard mask (2).
4. The processing method according to claim 1, characterized in that the hard mask (2) is laterally etched using a wet etching process, the size of the ion implantation window (5) being controlled by the etching time.
5. The processing method according to claim 1, wherein said lateral etching of said hard mask (2) on both sides of said trench (4) is followed by a gate oxide and polysilicon (7) growth process and said polysilicon (7) etching.
6. The processing method according to claim 5, wherein after the polysilicon (7) is etched, P-type impurity implantation and drive-in are performed on the substrate, and then N + ion implantation and annealing processes are performed.
7. The process according to claim 1, characterized in that after said N + ion implantation process, an ILD isolation layer (9) is grown and a wire hole (10) is etched in said ILD isolation layer (9) in correspondence of said hard mask (2) while etching away said hard mask (2).
8. The processing method according to claim 7, wherein after the etching of the lead hole (10) is completed, metal pads are provided on the front surface side and the back surface side of the substrate (1), respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910883126.0A CN110752149A (en) | 2019-09-18 | 2019-09-18 | Power device processing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910883126.0A CN110752149A (en) | 2019-09-18 | 2019-09-18 | Power device processing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110752149A true CN110752149A (en) | 2020-02-04 |
Family
ID=69276611
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910883126.0A Pending CN110752149A (en) | 2019-09-18 | 2019-09-18 | Power device processing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110752149A (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1592960A (en) * | 2001-11-20 | 2005-03-09 | 通用半导体公司 | Method of forming narrow trenches in semiconductor substrates |
| US20060292764A1 (en) * | 2003-04-03 | 2006-12-28 | Hirofumi Harada | Method of manufacturing a vertical MOS transistor |
| CN101123204A (en) * | 2006-08-10 | 2008-02-13 | 中芯国际集成电路制造(上海)有限公司 | Method for forming shallow groove separation structure and shallow groove separation structure |
| CN102064129A (en) * | 2009-11-13 | 2011-05-18 | 英特赛尔美国股份有限公司 | Semiconductor process using mask openings of varying widths to form two or more device structures |
| CN102074478A (en) * | 2009-11-24 | 2011-05-25 | 上海华虹Nec电子有限公司 | Manufacturing process method for trench MOS |
| CN102280487A (en) * | 2011-08-22 | 2011-12-14 | 无锡新洁能功率半导体有限公司 | Power MOSFET (Metal-Oxide -Semiconductor Field Effect Transistor) device of novel groove structure and manufacture method thereof |
| CN106783983A (en) * | 2016-11-18 | 2017-05-31 | 珠海格力电器股份有限公司 | A kind of insulated-gate bipolar transistor device and its manufacture method |
| CN106876453A (en) * | 2017-01-04 | 2017-06-20 | 上海华虹宏力半导体制造有限公司 | Trench gate IGBT and preparation method |
| CN108172563A (en) * | 2017-12-14 | 2018-06-15 | 中航（重庆）微电子有限公司 | A kind of ditch flute profile device and its manufacturing method with self-aligned contact hole |
| CN109473477A (en) * | 2017-09-07 | 2019-03-15 | 富士电机株式会社 | Semiconductor device |
-
2019
- 2019-09-18 CN CN201910883126.0A patent/CN110752149A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1592960A (en) * | 2001-11-20 | 2005-03-09 | 通用半导体公司 | Method of forming narrow trenches in semiconductor substrates |
| US20060292764A1 (en) * | 2003-04-03 | 2006-12-28 | Hirofumi Harada | Method of manufacturing a vertical MOS transistor |
| CN101123204A (en) * | 2006-08-10 | 2008-02-13 | 中芯国际集成电路制造(上海)有限公司 | Method for forming shallow groove separation structure and shallow groove separation structure |
| CN102064129A (en) * | 2009-11-13 | 2011-05-18 | 英特赛尔美国股份有限公司 | Semiconductor process using mask openings of varying widths to form two or more device structures |
| CN102074478A (en) * | 2009-11-24 | 2011-05-25 | 上海华虹Nec电子有限公司 | Manufacturing process method for trench MOS |
| CN102280487A (en) * | 2011-08-22 | 2011-12-14 | 无锡新洁能功率半导体有限公司 | Power MOSFET (Metal-Oxide -Semiconductor Field Effect Transistor) device of novel groove structure and manufacture method thereof |
| CN106783983A (en) * | 2016-11-18 | 2017-05-31 | 珠海格力电器股份有限公司 | A kind of insulated-gate bipolar transistor device and its manufacture method |
| CN106876453A (en) * | 2017-01-04 | 2017-06-20 | 上海华虹宏力半导体制造有限公司 | Trench gate IGBT and preparation method |
| CN109473477A (en) * | 2017-09-07 | 2019-03-15 | 富士电机株式会社 | Semiconductor device |
| CN108172563A (en) * | 2017-12-14 | 2018-06-15 | 中航（重庆）微电子有限公司 | A kind of ditch flute profile device and its manufacturing method with self-aligned contact hole |
Non-Patent Citations (1)
| Title |
|---|
| 雷剑梅等: "具有埋界面漏的Trench功率MOSFET研究 ", 《电力电子技术》 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10763351B2 (en) | Vertical trench DMOSFET having integrated implants forming enhancement diodes in parallel with the body diode | |
| JP6741070B2 (en) | Semiconductor device and manufacturing method thereof | |
| US5536959A (en) | Self-aligned charge screen (SACS) field effect transistors and methods | |
| KR20020086726A (en) | Method of forming a trench dmos having reduced threshold voltage | |
| JPH0969528A (en) | Semiconductor device and fabrication thereof | |
| CN108538911B (en) | Optimized L-type tunneling field effect transistor and preparation method thereof | |
| US8492221B2 (en) | Method for fabricating power semiconductor device with super junction structure | |
| CN111384179A (en) | Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device | |
| CN116613215A (en) | Linear planar power VDMOS structure and preparation method thereof | |
| KR100488099B1 (en) | A mos transistor having short channel and a manufacturing method thereof | |
| CN110752149A (en) | Power device processing method | |
| CN115911087A (en) | SGT-MOSFET (Metal-oxide-semiconductor field Effect transistor) for improving UIS (ultra thin silicon) performance and manufacturing method thereof | |
| CN104282762A (en) | Radio frequency transverse double-diffusion field effect transistor and manufacturing method thereof | |
| CN112309853A (en) | Preparation method of shielded gate trench structure | |
| CN108054099B (en) | Method for manufacturing semiconductor power device | |
| CN111244154A (en) | PMOS device and manufacturing method thereof | |
| CN213519864U (en) | Super junction | |
| CN214203693U (en) | Power semiconductor, transistor and electronic device | |
| JP2006332231A (en) | Manufacturing method of semiconductor device | |
| CN108493240B (en) | Z-type heterojunction tunneling field effect transistor with lightly doped drain structure and preparation method thereof | |
| KR960008736B1 (en) | Mosfet and the manufacturing method thereof | |
| KR100567030B1 (en) | Methood for manufacturing Transistor | |
| CN113658866A (en) | Preparation method of power device and power device | |
| KR100399948B1 (en) | Method for forming isolation layer of semiconductor device | |
| KR20040002411A (en) | Trench-gate semiconductor devices and their manufacture |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200204 |
|
| RJ01 | Rejection of invention patent application after publication |