CN101123204A - Method for forming shallow groove separation structure and shallow groove separation structure - Google Patents

Method for forming shallow groove separation structure and shallow groove separation structure Download PDF

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CN101123204A
CN101123204A CN 200610029904 CN200610029904A CN101123204A CN 101123204 A CN101123204 A CN 101123204A CN 200610029904 CN200610029904 CN 200610029904 CN 200610029904 A CN200610029904 A CN 200610029904A CN 101123204 A CN101123204 A CN 101123204A
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dielectric
trench
chemical vapor
vapor deposition
insulating medium
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CN100483667C (en
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刘明源
吴汉明
郑春生
郭佳衢
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中芯国际集成电路制造(上海)有限公司
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一种在半导体器件中形成浅沟槽隔离的方法,包括:在半导体衬底上形成掩膜层;图案化所述掩膜层以露出对应沟槽位置的半导体衬底;刻蚀所述衬底形成沟槽并在沟槽中形成衬垫氧化层;在所述沟槽中轮流淀积第一绝缘介质和第二绝缘介质直至填满所述沟槽;对所述半导体衬底进行快速热退火处理;平坦化所述绝缘介质以形成浅沟槽隔离结构。 A method for forming a shallow trench isolation in a semiconductor device, comprising: forming a mask layer on a semiconductor substrate; patterning the mask layer to expose the semiconductor substrate corresponding to the position of the trench; etching the substrate forming a trench and forming a pad oxide layer in the trench; alternately depositing a first dielectric and a second dielectric in said trench to fill up the trenches; the semiconductor substrate rapid thermal annealing processing; planarizing said insulating medium to form a shallow trench isolation structure. 本发明的浅沟槽隔离结构包括半导体衬底和衬底中形成的沟槽,沟槽中填充有绝缘介质,所述绝缘介质包括第一绝缘介质和第二绝缘介质,第一绝缘介质和第二绝缘介质彼此堆叠形成堆栈结构。 Shallow trench isolation structure according to the present invention comprises a semiconductor substrate and a trench formed in the substrate, the trench is filled with an insulating medium, the insulation medium comprises a first and a second insulating dielectric insulating medium, the first and second insulating medium two dielectric stacked together to form a stack structure. 本发明能够有效地控制浅沟槽隔离结构的应力,从而提高半导体器件的性能。 The present invention can effectively control the stress of the shallow trench isolation structure, thereby improving the performance of the semiconductor device.

Description

形成浅沟槽隔离结构的方法和浅沟槽隔离结构技术领域本发明涉及半导体制造技术领域,特别涉及一种在半导体器件中形成浅沟槽隔离结构的方法和浅沟槽隔离结构。 The method of forming a shallow trench isolation structure and the shallow trench isolation structure BACKGROUND Technical Field The present invention relates to semiconductor fabrication and more particularly relates to a method of forming a shallow trench isolation structure and the shallow trench isolation structure in a semiconductor device. 背景技术随着半导体工艺进入深亚微米时代,0. 13 jam以下的元件例如CMOS器件中,NMOS晶体管和PMOS晶体管之间的隔离层均采用浅沟槽隔离工艺(STI)形成。 BACKGROUND As semiconductor technology deep sub-micron regime, 0. 13 jam following elements such as CMOS devices, the isolation layer between the NMOS and PMOS transistors are formed in shallow trench isolation process (STI). 在这种工艺中,先在衬底上形成浅沟槽,元件之间用刻蚀的浅沟槽隔开, 然后在沟槽侧壁和底部形成氧化衬垫,再利用化学气相淀积(CVD)在浅沟槽中填入绝缘介质,例如氧化硅。 In this process, first a shallow trench is formed on the substrate, between elements separated by a shallow trench etching, the pad oxide is then formed in the trench sidewalls and bottom, and then using a chemical vapor deposition (CVD ) filled in the shallow trench dielectric such as silicon oxide. 在填入绝缘介质之后,用化学机械研磨(CMP) 的方法使沟槽表面平坦化。 After the filled insulating medium, by chemical mechanical polishing (CMP) to planarize the surface of the trench. 浅沟槽隔离结构的制造工艺中,在半导体基底材料上形成沟槽后,隔离沟槽的侧壁在后续的工艺步骤(如热氧化工艺)中发生氧化,其结果造成隔离沟槽基底的体积膨胀,因而引发沟槽侧壁与绝缘填充物之间的应力问题, 在浅沟槽内形成衬垫氧化层后,村垫材料与绝缘填充物之间也会产生应力。 Process for producing a shallow trench isolation structure, after forming a trench on the semiconductor substrate material, oxide sidewall isolation trench in a subsequent process steps (e.g., thermal oxidation process), which is resulting in the isolation trench of the substrate volume expansion, thereby inducing stress problems between the trench sidewalls and the insulating filler, the pad oxide layer is formed in the shallow trench, will produce stress between the mat material and villages insulating filler. 消除这种应力的方法主要集中在浅沟槽村垫材料的选择以及使用退火工艺来释放沟槽侧壁与绝缘填充层之间的应力和衬垫材料与绝缘填充层之间的应力。 This method eliminates the stress concentrated in the shallow trench selected village pad material and a stress and the stress between the liner and the insulating filling layer between the trench sidewalls and the insulating filling layer using an annealing process to release. 专利号为ZL98125145. 5的中国专利公开了一种在半导体器件内形成隔离沟槽的方法,其采用在沟槽中沉积衬垫氧化层和填充绝缘介质后进行退火的方法解决浅沟槽侧壁与绝缘填充层之间的应力问题。 The method of annealing after Patent No. ZL98125145. 5 Chinese Patent discloses a method of forming an isolation trench in the semiconductor device and the pad oxide layer is deposited using insulating medium is filled in the shallow trench sidewall trench solution problems stress between the insulating filling layer. 该方法首先在衬底上形成沟槽,然后在沟槽内沉积一层氧化层并利用HDP-CVD(高密度等离子体化学气相淀积)工艺在沟槽中填充绝缘介质,随后在不低于115(TC的温度进行退火。申请号为02146140. 6的中国专利申请公开了一种在半导体基底中形成浅沟槽隔离物的方法,该方法在沟槽内形成氧化硅衬垫之后,在含有氩气的环境下进行退火。申请号为02148740. 5的中国专利申请同样公开了一种在半导体基底中形成浅沟槽隔离物的方法,该方法沟槽内形成氧化硅层之后,在含氧化氮或氮气/氧气的环境下对半导体基底(如硅基底)进行回火。在申请号为01109498.2的中国专利申请中,其降低衬垫材料与绝缘填充物之间应力的方法是利用氮氧化硅或是氧化硅/氮化硅/氧化硅的多层结构形成浅沟槽的衬 In this method, a trench is formed on the substrate, an oxide layer is then deposited within the trench and in a trench filled with an insulating medium using a HDP-CVD (High Density Plasma Chemical Vapor Deposition) process, followed by not less than after 115 (TC annealing temperature. Chinese Patent application No. 02146140.6 application discloses a method of forming a shallow trench isolation in a semiconductor substrate, the method of forming a silicon oxide liner in the trench, containing after annealing under argon environment. application No. of China Patent application No. 02148740.5 also discloses a method of forming a shallow trench isolation in a semiconductor substrate, a silicon oxide layer within the trench method, the oxide-containing the method under a nitrogen or nitrogen / oxygen environment of a semiconductor substrate (e.g. silicon substrate) is tempered in Chinese Patent application No. 01109498.2, the liner that reduces stress between the insulating material and the filler using silicon oxynitride or a silicon oxide / silicon nitride / silicon oxide, a multilayer structure is formed shallow trench liner

垫。 pad. 目前还存在将退火工艺和衬垫材料的选择结合起来,以降低沟槽侧壁与绝缘填充层之间的应力和衬垫材料与绝缘填充层之间的应力的方法。 Unfortunately there is a method to select the annealing process and the cushioning material combine to reduce the stress and the stress between the liner and the insulating filling layer between the trench sidewalls and the insulating filling layer. 然而,由于利用HDP-CVD工艺在沟槽中填充的绝缘介质非常致密,绝缘介质自身会产生较强的压应力(compressive stress),虽然沟槽侧壁和衬垫材料与沟槽中填充的绝缘介质之间的应力可通过上述方法降低或消除,但绝缘介质自身产生的压应力依然存在,使浅沟槽隔离结构呈现较高的压应力状态。 However, since the HDP-CVD process is filled in the trench dielectric is very dense, insulating medium itself will produce a strong compressive stress (compressive stress), although the trench sidewalls and the trench is filled with a gasket material insulating stress between the medium by the above method can reduce or eliminate, the stress itself generated by the dielectric remains the shallow trench isolation structure exhibits high compressive stress. 当器件的特征尺寸进入到65nm以及65nm以下的工艺节点后,元件的密集程度越来越高,元件之间的空间距离变得非常微小,这种应力会改变沟槽两侧丽OS 和PMOS的沟道晶格结构,影响栽流子浓度,导致栽流子的迁移率的改变,从而增加了产生漏电流的机会。 When the feature size of the device into the 65nm and 65nm node technology, increasing the intensity of the element, the space distance between the elements becomes very small, this will change the stress on both sides of the trench and a PMOS OS Korea channel lattice structure, affect plant carrier concentration, leading to changes in the mobility of carriers in the plant, thus increasing the chance of leakage current. 发明内容本发明提供了一种在半导体器件中形成浅沟槽隔离结构的方法和浅沟槽隔离结构,能够有效地降低浅沟槽隔离结构的应力。 The present invention provides a method of forming a shallow trench isolation structure in a semiconductor device and shallow trench isolation structure, it is possible to effectively reduce the stress of the shallow trench isolation structure. 本发明的一个目的在于提供一种在半导体器件中形成浅沟槽隔离结构的方法,包才舌:在半导体村底上形成掩膜层;图案化所述掩膜层以露出对应沟槽位置的半导体村底;刻蚀所述村底形成沟槽并在沟槽中形成衬垫氧化层;在所述沟槽中轮流淀积第一绝缘介质和第二绝缘介质直至填满所述沟槽;对所述半导体衬底进行快速热退火处理; 平坦化所述绝缘介质以形成浅沟槽隔离结构。 An object of the present invention to provide a method for forming a shallow trench isolation structure in a semiconductor device, the package before the Tongue: forming a mask layer on the semiconductor substrate; patterning the mask layer to expose the position corresponding to the groove semiconductor substrate; forming a trench bottom etching the village and the pad oxide layer is formed in the trench; alternately depositing a first dielectric and a second dielectric in we said trench to fill up the trenches; the rapid thermal annealing of the semiconductor substrate; planarizing the insulating medium to form a shallow trench isolation structure. 所述第一绝缘介质是利用亚常压化学气相淀积工艺淀积的绝缘介质。 Said first insulating medium using sub-atmospheric chemical vapor deposition dielectric deposition process. 所述第二绝缘介质是利用高密度等离子体化学气相淀积工艺淀积的绝缘介质。 The second insulating dielectric medium using a high density plasma chemical vapor deposition process deposition. 所述第一绝缘介质是利用高密度等离子体化学气相淀积工艺淀积的绝缘介质。 Said first dielectric medium is insulating high density plasma chemical vapor deposition process deposition. 所述第二绝缘介质是利用亚常压化学气相淀积工艺淀积的绝缘介质。 Said second insulating medium using sub-atmospheric chemical vapor deposition dielectric deposition process. 所述绝缘介质为氧化硅。 The dielectric is silicon oxide. 所述亚常压化学气相淀积的工艺参数包括: The sub-atmospheric chemical vapor deposition process parameter comprises:

压力:300-500Torr; 氦气(He)流量:500-2000sccs; 氧气(03)流量:10000-20000sccs; 正硅酸乙脂(TEOS)流量:1000-3000sccs。 Pressure: 300-500Torr; Helium (He) flow rate: 500-2000sccs; oxygen (03) flow rate: 10000-20000sccs; tetraethyl orthosilicate (TEOS) flow rate: 1000-3000sccs. 所述高密度等离子体化学气相淀积的工艺参数包括: 压力:5-12mTor厂, 射频功率:6000-9000W; 氢气(H2)流量:200-1000sccs; 氧气(0》流量:30-36sccs; 硅烷(SiH4)流量:10-14.5sccs。 所述快速热退火的温度为900-1100°C;时间为20-50s。 本发明的另一个目的在于提供一种在半导体器件中形成'浅沟槽隔离结构的方法,包4舌:在半导体衬底上形成掩膜层;图案化所述掩膜层以露出对应沟槽位置的半导体衬底; 刻蚀所述衬底形成沟槽并在沟槽中形成衬垫氧化层; 在所述沟槽中循环交替淀积和减薄第一绝缘介质和第二绝缘介质直至填满所述沟槽;对所述半导体衬底进行快速热退火处理;平坦化所述绝缘介质以形成浅沟槽隔离结构。所述第一绝缘介质是利用亚常压化学气相淀积工艺淀积的绝缘介质。所述第二绝缘介质是利用高密度等离子体化学气相淀积工艺淀积的绝缘介质 The high-density plasma chemical vapor deposition process parameters include: pressure: 5-12mTor plant, RF power: 6000-9000W; hydrogen (H2) flow rate: 200-1000sccs; oxygen (0 "Traffic: 30-36sccs; Silane . (of SiH4) flow rate: 10-14.5sccs the rapid thermal annealing temperature of 900-1100 ° C; time 20-50s another object of the present invention is a method of forming 'shallow trench isolation in a semiconductor device. configuration method, the packet tongue 4: mask layer is formed on a semiconductor substrate; patterning the masking layer to expose the semiconductor substrate corresponding to a position of the trench; and etching the substrate, forming a trench in the trench forming a pad oxide layer; depositing alternating cycle and the first thin insulating dielectric medium and the second medium until filling the trench in said trench; the semiconductor substrate rapid thermal annealing process; planarizing the insulating medium to form a shallow trench isolation structure using the first dielectric sub-atmospheric CVD processes deposited dielectric. the second is the use of insulating medium high density plasma chemical vapor deposition process deposited dielectric 所述第一绝缘介质是利用高密度等离子体化学气相淀积工艺淀积的绝缘介质。所述第二绝缘介质是利用亚常压化学气相淀积工艺淀积的绝缘介质。所述绝缘介质为氧化硅。所述亚常压化学气相淀积的工艺参数包括:压力:300-500Torr;氦气(He)流量:500-2000sccs;氧气(03)流量:10000-20000sccs; 正石圭酸乙脂(TEOS)流量:1000-3000sccs。所述高密度等离子体化学气相淀积的工艺参数包括: 压力:5-12mTorr;射频功率:6000-9000W;氢气(H2)流量:200-1000sccs;氧气(0》流量:30-36sccs;硅烷(SiH4)流量:10-14. 5sccs。所述快速热退火的温度900-IIO(TC;时间为20_50s。利用回刻工艺对所述绝缘介质层进行减薄。 Said first dielectric insulating medium is a high density plasma chemical vapor deposition process is deposited. The second insulating medium using sub-atmospheric chemical vapor deposition dielectric deposition process. The dielectric is silicon oxidation process parameters of the sub-atmospheric chemical vapor deposition comprising: pressure: 300-500Torr; helium (He) flow rate: 500-2000sccs; oxygen (03) flow rate: 10000-20000sccs; n stone Kyu aliphatic acid b . (TEOS) flow rate: 1000-3000sccs the high density plasma chemical vapor deposition process parameters comprising: pressure: 5-12mTorr; RF power: 6000-9000W; hydrogen (H2) flow rate: 200-1000sccs; oxygen (0 "flow: 30-36sccs; silane (SiH4) flow rate:. 10-14 5sccs the rapid thermal annealing temperature of 900-IIO (TC; 20_50s time of the insulating dielectric layer is thinned using an etch-back process...

本发明的再一个目的在于提供一种浅沟槽隔离结构,包括半导体衬底和衬底中形成的沟槽,所述沟槽中填充有绝缘介质,其特征在于:所述绝缘介质包括第一绝缘介质和第二绝缘介质,所述第一绝缘介质和第二绝缘介质彼此堆叠形成堆栈结构。 A further object of the present invention to provide a shallow trench isolation structure, comprising a semiconductor substrate and a trench formed in the substrate, the trench is filled with an insulating medium, characterized in that: said medium comprises a first insulating and a second insulating dielectric medium, the first and second insulating dielectric medium are stacked together to form a stack structure. 所述第一绝缘介质是利用亚常压化学气相淀积工艺淀积的绝缘介质,所述第二绝缘介质是利用高密度等离子体化学气相淀积工艺淀积的绝缘介质。 It said first insulating medium using sub-atmospheric chemical vapor deposition dielectric deposition process, using the second insulating medium is a high density plasma chemical vapor deposition dielectric deposition process.

所述第一绝缘介质是利用高密度等离子体化学气相淀积工艺淀积的绝缘介质,所述第二绝缘介质是利用亚常压化学气相淀积工艺淀积的绝缘介质。 Said first dielectric medium is insulating high density plasma chemical vapor deposition process is deposited, the second insulating medium using sub-atmospheric chemical vapor deposition dielectric deposition process. 与现有技术相比,本发明具有以下优点: Compared with the prior art, the present invention has the following advantages:

本发明的形成浅沟槽隔离的方法利用亚常压化学气相淀积工艺和高密度等离子化学气相淀积工艺在隔离沟槽中交替轮流淀积绝缘介质氧化硅,从而在沟槽中形成亚常压化学气相淀积的氧化硅层和高密度等离子化学气相淀积的氧化硅层彼此堆叠在一起直至填满整个隔离沟槽,也就是沟槽中填充的绝缘介质是由亚常压化学气相淀积工艺形成的氧化硅层和由高密度等离子化学气相淀积工艺形成的氧化硅层堆叠在一起形成的堆栈结构。 The present invention is formed of a shallow trench isolation method using a sub-atmospheric CVD processes and a high density plasma chemical vapor deposition process turns alternately depositing silicon oxide dielectric isolation trench, thereby forming a trench in the sub often pressure chemical vapor deposition of silicon oxide layer and a high density plasma chemical vapor deposition silicon oxide layer are stacked each other until fill the isolation trench, the trench is filled with an insulating medium is a sub-atmospheric chemical vapor lake forming a silicon oxide layer deposition process and a silicon oxide layer formed by high density plasma chemical vapor deposition process of a stacked together to form a stack structure. 这样,由于亚常压化学气相淀积工艺形成的氧化硅在应力分布上呈现压应力状态,由高密度等离子化学气相淀积工艺形成的氧化硅层在应力分布上呈现拉应力状态,具有方向相反的应力的各氧化硅层堆叠在一起后,在应力方向上各层的应力叠加后相互抵消,使沟槽中填充的整个绝缘介质层的应力非常小,极大地降低了浅沟槽隔离结构的应力水平,正如本领域技术人员所知,沟槽中的应力会 As such, since the sub-atmospheric chemical oxide silicon vapor deposition process exhibits stress on the state of stress distribution, a silicon oxidation layer is formed by high density chemical plasma CVD processes tension stress appears in stress distribution, having opposite directions each of the silicon oxide layer stacked after stress, the stress in the direction of superposition of the respective layers cancel each other out stress, stress across the insulating dielectric layer filling the trench is very small, which greatly reduces the shallow trench isolation structure stress level, as the person skilled in the art, the stresses in the trench

对附近半导体器件例如NMOS和PMOS器件沟道中的晶格结构产生影响,通过本发明方法获得的低应力浅沟槽隔离结构降低了对画OS和PMOS沟道晶格结构和载流子浓度以及迁移率的影响,从而改善了半导体器件的性能。 NMOS and PMOS devices lattice structure in the channel impact in the vicinity, for example, a semiconductor device, low-stress shallow trench isolation structure obtained by the process according to the present invention reduces the OS and PMOS Videos lattice structure and carrier concentration and the mobility of the channel Effect rate, thereby improving the performance of semiconductor devices. 更为重要的是,根据压阻效应,拉应力有利于NMOS器件沟道中栽流子浓度和迁移率的增加,压应力有利于PMOS器件沟道中栽流子浓度和迁移率的增加。 More importantly, according to the piezoresistive effect, help to increase the tensile stress in the carrier concentration and the mobility of the channel of the NMOS device plant, help to increase the flow stress concentration and the mobility of the PMOS device channel planted. 应用本发明的方法,可以根据CMOS器件沟道和栅极结构应力工程设计的需要,使由亚常压化学气相淀积工艺形成的氧化硅层和由高密度等离子化学气相淀积工艺形成的氧化硅层堆叠在一起形成的堆栈结构在整体上表现出特定大小和方向的应力状态,实现应力由压应力向拉应力的梯度变化。 The method of application of the invention, as needed and the gate CMOS device channel engineering structural stress, the silicon oxide layer is formed by the sub-atmospheric chemical vapor deposition process and is formed by oxidation of a high density plasma chemical vapor deposition process silicon layer stack together to form a stack structure exhibits a certain magnitude and direction of the overall stress state, the stress gradient achieved by the compressive stress to tensile stress. 有针对性地改善CMOS器件中丽OSFET或PMOSFET的电学性能。 Targeted to improve electrical performance of a CMOS device or a PMOSFET OSFET Korea. 附图说明图1为根据本发明第一实施例的形成浅沟槽隔离结构的方法流程图; 图2A至图2C为说明图1所示方法的浅沟槽隔离结构简化剖面示意图; 图3为根据本发明第二实施例的形成浅沟槽隔离结构的方法流程图; 图4为说明图3所示方法的浅沟槽隔离结构简化剖面示意图。 BRIEF DESCRIPTION OF DRAWINGS FIG 1 is a flowchart of a method for forming a shallow trench isolation structure according to a first embodiment of the present invention; FIGS. 2A to 2C are simplified schematic cross-sectional view for explaining a method of shallow trench isolation structure shown in FIG. 1; FIG. 3 is a the method of shallow trench isolation structure formation according to a second embodiment of a flow diagram of the embodiment of the present invention; FIG. 4 is a method of shallow trench isolation structure shown in Figure 3 a simplified schematic cross-sectional view. 具体实施方式为使本发明的上述目的、特征和优点能够更加明显易懂,下面结合附图对本发明的具体实施方式做详细的说明。 DETAILED DESCRIPTION To make the above objects, features and advantages of the present invention can be more fully understood in conjunction with the accompanying drawings in detail description of specific embodiments of the present invention. 本发明是关于半导体集成电路制造技术领域,特别是关于在半导体器件中形成浅沟槽隔离结构的方法和浅沟槽隔离结构。 Invention relates to a semiconductor integrated circuit fabrication techniques, and in particular a method for forming a shallow trench isolation structure in a semiconductor device and a shallow trench isolation structure. 这里需要说明的是,本说明书提供了不同的实施例来说明本发明的各个特征,但这些实施例仅是利用特别的组成和结构以方使^兌明,并非对本方面的限定。 It is noted that the present description provides various embodiments to illustrate various features of the present invention, but these examples are only using special composition and structure that the side against ^ out, is not limited to this aspect. 器件的载流子迁移率的影响变得越来越明显。 Influence mobility of carriers devices become more and more evident. NOMS和PMOS器件之间的浅沟槽隔离结构(STI)的应力已经是影响CMOS器件的一个非常重要的因素。 A very important factor stress shallow trench isolation (STI) structure between NOMS and PMOS devices of CMOS devices are already impact. 应力状态的设计是获得器件目标性能的关键因素之一。 Design stress state is a key factor for the target device performance. 由于STI隔离沟槽中的应力分布依赖于沟槽内部填充物的结构形态,因此需要改变沟槽内部填充物的结构形态以调整沟槽内部的应力分布。 Since STI isolation trenches stress distribution depends on the morphology of the internal filling the trenches, it is necessary to change the internal structure and morphology of the trench fill the trench to adjust the internal stress distribution. 图1为根据本发明第一实施例的形成浅沟槽隔离结构的方法流程图,所述示意图只是实例,其在此不应过度限制本发明保护的范围。 Figure 1 is an embodiment of a method of forming a shallow trench isolation structure of the first embodiment of the present invention, a flow chart, the diagrams are merely examples, which should not unduly limit the scope of the present invention.

如图1所示,在半导体衬底中刻蚀形成沟槽(S101),该步骤中在提供的半导体衬底上依次形成氧化硅层和氮化硅层,氧化硅层和氮化硅层作为掩膜层。 1, in a semiconductor substrate etched to form a trench (S101), the step of sequentially forming a silicon oxide layer and a silicon nitride layer provided on a semiconductor substrate, the silicon oxide layer and a silicon nitride layer as a mask layer. 氮化硅层也可以是氮化硅和氮氧化硅的混合物。 The silicon nitride layer or a mixture of silicon nitride and silicon oxynitride. 氧化硅层和氮化硅层可以提供热生长或化学气相淀积等方法形成。 A silicon nitride layer and a silicon oxide layer may provide thermally grown or chemical vapor deposition or the like is formed. 氧化硅作为半导体村底和氮化硅之间的过渡层。 Silicon oxide as a buffer layer between the semiconductor substrate and a silicon nitride. 由于氮化硅具有较高的致密程度,可作为后续的刻蚀停止层和化学机械研磨(CMP)的研磨阻挡层。 Since the silicon nitride having high degree of densification, can be used as an etch stop layer and the subsequent chemical mechanical polishing (CMP) polishing the barrier layer. 图案化上述掩膜层以露出对应沟槽位置的半导体衬底,利用掩膜在衬底中刻蚀出沟槽;然后,在沟槽中形成衬垫氧化层以利于后续氧化硅层的淀积(S102);在接下来的工艺步骤中,在沟槽中利用亚常压化学气相淀积(SACVD)工艺淀积氧化硅(S103),这里为方便起见将该氧化硅称为SACVD膜。 The patterned mask layer above the semiconductor substrate to expose the position corresponding to the trench, using a mask to etch trenches in the substrate; Then, the pad oxide layer is formed in the trench in order to facilitate the subsequent depositing a silicon oxide layer, (S102); in the next process step, the sub-atmospheric chemical vapor deposition (SACVD) process of silicon oxide is deposited (S103) in the trench, for convenience herein referred to this silicon oxide film SACVD. 淀积过程中,将半导体衬底放入反应室中, 将反应室内的压力控制在300-500Torr;向反应室中通入氦气、氧气和正硅酸乙脂,流量分别为氦气(He)流量:500-2000sccs ; 氧气(03)流量: 10000-20000sccs;正硅酸乙脂(TEOS )流量:1000-3000sccs。 Deposition process, the semiconductor substrate placed in the reaction chamber, the reaction chamber pressure is controlled 300-500Torr; into the reaction chamber of helium, oxygen and TEOS, respectively, the flow rate of helium (He) flow: 500-2000sccs; oxygen (03) flow rate: 10000-20000sccs; tetraethyl orthosilicate (TEOS) flow rate: 1000-3000sccs. 利用SACVD 工艺在沟槽中淀积的氧化硅具有较强的拉应力(tensile stress )。 SACVD deposition process of the silicon oxide in the trench with a strong tensile stress (tensile stress). 这是由于SACVD是在亚大气压状态下进行的,形成的氧化硅膜层的致密程度不是很高, 氧化硅分子之间分子键合力的作用没有达到紧密收缩的程度;在随后的工艺步骤中,回刻氧化硅(S104),使沟槽中的氧化硅减薄;然后再利用HDP-CVD 工艺在沟槽内的上述氧化硅表面继续淀积氧化硅(S105 ),这里为方便起见将该氧化硅膜称为HDP膜。 This is because SACVD is performed at sub-atmospheric pressure, the degree of dense silicon oxide film layer formed is not very high, the bonding force acting between the molecules of silicon oxide molecules are not tight to the extent of shrinkage; in a subsequent process step, silica etch-back (S104), the silicon oxide trench thinning; then using the silicon oxide surface of the HDP-CVD process in the deposition of a silicon oxide trench continues (S105), where for convenience sake of the oxidation of HDP silicon film called membrane. 在这个过程中,反应室内的压力控制在5-12mTorr; 产生等离子体射频功率为6000-9000W;向反应室中通入氢气、氧气和硅烷(SiH4),氢气(H2)的流量为200-1000sccs;氧气(02)的流量为30-36sccs; 硅烷(SiH4)的流量为10-14. 5sccs。 In this process, the pressure in the reaction chamber is controlled 5-12mTorr; generating a plasma and RF power of 6000-9000W; the reaction chamber into hydrogen, oxygen and silane (of SiH4), flow rate of hydrogen (H2) is 200-1000sccs ; flow rate of oxygen (02) is 30-36sccs; flow rate of silane (SiH4) is 10-14 5sccs.. 由HDP-CVD工艺淀积的氧化硅膜层具有很高的致密程度,因而其具有较高的压应力。 Deposited by HDP-CVD process a silicon oxide film having a high degree of densification, and thus it has a higher compressive stress. 如此一来, 一层具有拉应力的SACVD膜和一层具有压应力的HDP膜堆叠在一起,两层膜的应力相互抵消,从整体上表现为无应力状态。 Thus, SACVD layer having a tensile stress film and a compressive stress layer having a HDP film stacked together, two stress film cancel each other, it showed no stress state on the whole. 接下来,再回刻该层HDP膜使其减薄(S106);然后继续执行步骤S103、 S104和S105,也就是执行SACVD—回刻—HDPCVD—回刻—SACVD这样一个循环交替淀积、减薄、再淀积的步骤,直至填满沟槽。 Next, the engraving layer to return it HDP film thinning (S106); then proceed to Step S103, S104 and S105, etch-back is performed SACVD- -HDPCVD- etched back such an alternating cycle -SACVD deposition, Save thin, then the deposition step until the filled trench. 通过控制沟槽中SACVD膜和HDP膜的数量和厚度可以使沟槽内填充的氧化硅的应力相互抵消。 Stress can be filled with silicon oxide within the trench by controlling the number and thickness of the film and the trench SACVD HDP film cancel each other out. 在接下来的工艺步骤中,对衬底进行快速热退火(RTA)处理(S107),温度控制在则-1100。 In the next process step, the substrate is a rapid thermal annealing (RTA) process (S107), the temperature control is -1100. C,时间为20-50s。 C, time 20-50s. 以进一步消除村垫氧化 To further eliminate the pad oxide village

层和沟槽侧壁与填充的氧化硅之间的应力;最后通过化学机械研磨对沟槽进行平坦化(S108),从而得到应力水平很低的STI隔离结构。 Stress between the silicon oxide layer and the trench sidewalls and filling; finally planarized (S108) of the trench by chemical mechanical polishing to obtain a low stress level STI isolation structure 这里需要说明的是,SACVD和HDPCVD循环交替淀积的次数可以视沟槽深度而定,本领域技术人员可以灵活掌握。 It should be noted that the number and SACVD deposition HDPCVD alternating cycle may be set depending on the depth of the groove, those skilled in the art to have flexibility. 当沟槽深度较高时,刻适当增加循环淀积的次数;当深度较小时,可适当减少循环淀积的次数。 When higher groove depth, number of suitably engraved deposition cycles increased; when the depth is small, the number of cycles can be reduced appropriately deposited. 此外,每层SACVD 膜和HDPCVD膜的厚度和淀积顺序也可以根据实际情况而定,即可以先淀积SACVD膜也可以先淀积HDP膜,只要使沟槽中形成SACVD膜和HDPCVD膜的堆栈结构在整体上表现为无应力状态即可,本领域技术人员可以膜的厚度做出许多修改和变化。 Further, the film and the thickness of each layer and SACVD deposition sequence HDPCVD film may be determined according to the actual situation, i.e., the film may also be first deposited to SACVD HDP deposited film, so long as the film and the trench is formed SACVD film HDPCVD stacked structure can be reflected in the overall thickness of the film of the present art can make many modifications and variations of stress-free state. 例如,若沟槽深度为2um,可以利用如表2所示的SACVD膜和HDP膜的不同厚度组合,获得无应力状态的堆栈结构。 For example, if the groove depth is 2um, SACVD film may be utilized as shown in Table 2, and various combinations of HDP film thickness obtained stack structure unstressed state. 当然,也可以根据CMOS器件沟道和栅极结构应力工程设计的需要,使SACVD膜和HDPCVD膜的堆栈结构在整体上表现出特定大小和方向的应力状态。 Of course, a CMOS device may also need to channel and gate structure engineering stress, and that the membrane stack structure SACVD HDPCVD film exhibits a stress state of a particular size and direction as a whole. 表2:应力(Mpa ) SACVD膜厚度(A) HDP膜厚度(A )-120 1000 4000-40 2000 300040 3000 2000120 4000 1000图2A至图2C为说明图1所示方法的浅沟槽隔离结构简化剖面示意图, 所述示意图只是实例,其在此不应过度限制本发明保护的范围。 Table 2: Stress (Mpa) SACVD film thickness (A) HDP film thickness (A) -120 1000 4000-40 2000 300040 3000 2000120 4000 1000 FIGS. 2A to 2C shallow trench isolation structure for explaining the method shown in Figure 1 a simplified cross-sectional schematic diagram is merely an example, which should not unduly limit the scope of the invention. 如图2A所示, 在提供的半导体衬底100上依次形成氧化硅层110和氮化硅层120,氮化硅层120也可以示氮化硅或氮氧化硅的混合物。 2A, a silicon oxide layer 110 is formed and a silicon nitride layer 120 on the semiconductor substrate 100 is successively provided, a silicon nitride layer 120 shown may be silicon nitride or a mixture of silicon oxide. 氧化硅层110和氮化硅层120可以提供热生长或化学气相淀积等方法形成。 The silicon oxide layer 110 and silicon nitride layer 120 may provide thermal growth or chemical vapor deposition or the like is formed. 氧化硅110作为半导体衬底100和氮化硅120之间的过渡层。 Silicon oxide 110 as the semiconductor substrate 100 and buffer layer 120 between the silicon nitride. 氮化硅120具有较高的致密程度,可以作为后续的刻蚀停止层和化学机械研磨(CMP)的研磨阻挡层。 Silicon nitride 120 having a high degree of densification, and the layer can be a chemical mechanical polishing (CMP) polishing a subsequent barrier layer to stop etching. 图案化上述掩膜层以露出对应沟槽位置的半导体衬底,利用掩膜在衬底中刻蚀出沟槽130。 The patterned mask layer above a semiconductor substrate to expose the position corresponding to the trench, a trench 130 is etched by using a mask in a substrate. 然后,如图2B所示,在沟槽中形成衬垫氧化层140,以利于后续氧化硅层的淀积。 Then, 2B, pad oxide layer 140 is formed in the trench, in order to facilitate the subsequent deposition of a silicon oxide layer. 衬垫氧化层140通常采用热氧化的方法形成。 Pad oxide layer 140 is typically formed by thermal oxidation. 在接下来的工艺步骤中,如图2C所示,在沟槽中利用亚常压化学气相淀积(SACVD)工艺淀积氧化硅层131。 In the next process step shown in Figure 2C, using sub-atmospheric chemical vapor deposition (SACVD) process of a silicon oxide layer 131 is deposited in the trench. 利用SACVD工艺在沟槽中淀积的氧化硅膜131具有较强的拉应力(tensile stress)。 SACVD deposition process using a silicon oxide film in the trench 131 has a strong tensile stress (tensile stress). 然后,回刻氧化硅膜131,使 Then, a silicon oxide film 131 is etched back, so that

沟槽中的氧化硅减薄;再利用HDP-CVD工艺在沟槽内的上述氧化硅表面继续淀积氧化硅膜132,由HDP-CVD工艺淀积的氧化硅膜层具有很高的致密程度, 因而其具有较高的压应力。 Thinning the silicon oxide trench; reuse the silicon oxide surface in the HDP-CVD process continues trench silicon oxide film 132 is deposited by HDP-CVD silicon oxide film deposition process has high degree dense thus it has a higher compressive stress. 接下来,回刻该层氧化硅膜132使其减薄,继续利用SACVD工艺淀积氧化硅膜133,再回刻该氧化硅膜133使其减薄,继续利用HDP-CVD工艺在氧化硅膜133上淀积氧化硅膜134。 Subsequently, the layer is etched back so that thinning a silicon oxide film 132, the process continues using a SACVD deposition of silicon oxide film 133, silicon oxide film engraved return 133 so as thinning, continued use of HDP-CVD process a silicon oxide film depositing a silicon oxide film 134 133. 由于具有拉应力的SACVD 氧化硅膜和具有压应力的HDP氧化硅膜堆叠在一起后,膜的应力相互抵消。 Since the silicon oxide film having a tensile stress SACVD, and HDP silicon oxide film having compressive stress of the stacked, stress film cancel each other. 沟槽中填充的SACVD膜131和133, HDP膜132和134堆叠在一起组成的堆栈结构从整体上表现为无应力状态。 SACVD trench filled film 131 and 133, HDP film 132 and 134 are stacked together to form the stacked structure as a whole to exhibit a stress-free state. 这里需要说明的是,SACVD和HDPCVD循环交替淀积的次数可以视沟槽深度而定,本领域技术人员可以灵活掌握。 Note that here, the number of alternating cycles HDPCVD SACVD deposition and can optionally set the groove depth, those skilled in the art to have flexibility. 当沟槽深度较高时,刻适当增加循环淀积的次数;当深度较小时,可适当减少循环淀积的次数。 When the groove depth is high, the number of engraved appropriately increased deposition cycles; when the depth is small, can be appropriate to reduce the number of cycles of deposition. 此外,每层SACVD 膜和HDPCVD膜的厚度淀积顺序也可以才艮据实际情况而定,即可以先淀积SACVD 膜也可以先淀积HDP膜,本领域技术人员可以膜的厚度做出许多修改和变化。 Further, the thickness of each film, and SACVD deposition film may be sequentially HDPCVD Gen only according to the actual circumstances, i.e., the film may also be first deposited to SACVD HDP deposited films, those skilled in the art may make many film thickness modifications and variations. 就本实施例而言,氧化硅膜131、 132、 133和134已经将沟槽填满。 With the present embodiment, the silicon oxide film 131, 132, 133 and 134 have been filled trench. 图3为根据本发明第二实施例的形成浅沟槽隔离结构的方法流程图,所述示意图只是实例,其在此不应过度限制本发明保护的范围。 Figure 3 is a method of forming a shallow trench isolation structure of a second embodiment of the present invention, a flowchart diagram is merely an example, which should not unduly limit the scope of the present invention. 如图3所示, 本实施例中,首先在半导体衬底中刻蚀形成沟槽(S301);该步骤中,在提供的半导体村底上依次形成氧化硅层和氮化硅层,氧化硅层和氮化硅层作为掩膜层。 Silicon oxide in this step, sequentially forming a silicon oxide layer and a silicon nitride layer over the semiconductor substrate provided; FIG. 3, the present embodiment example, first etching to form a trench (S301) on a semiconductor substrate layer and a silicon nitride layer as a mask layer. 氮化硅层也可以是氮化硅和氮氧化硅的混合物。 The silicon nitride layer may be a mixture of silicon nitride and silicon oxynitride. 氧化硅层和氮化硅层可以提供热生长或化学气相淀积等方法形成。 A silicon nitride layer, silicon oxide layer and may provide thermally grown or chemical vapor deposition or the like is formed. 氧化硅作为半导体衬底和氮化硅之间的过渡层。 Silicon oxide as a buffer layer between the semiconductor substrate and a silicon nitride. 由于氮化硅具有较高的致密程度,可作为后续的刻蚀停止层和化学机械研磨(CMP)的研磨阻挡层。 Since the silicon nitride has a high degree of densification, it can be used as an etch stop layer and the subsequent chemical mechanical polishing (CMP) polishing the barrier layer. 图案化上述掩膜层以露出对应沟槽位置的半导体衬底,利用掩膜在衬底中刻蚀出沟槽。 The patterned mask layer above the semiconductor substrate to expose the position corresponding to the trench, a trench etched using a mask in a substrate. 然后,在沟槽中形成衬垫氧化层以利于后续氧化硅层的淀积(S302 );随后在沟槽中利用亚常压化学气相淀积(SACVD)工艺淀积氧化硅膜(S303 ),这里为方便起见也将该氧化硅称为SACVD膜。 Then, a pad oxide layer to facilitate deposition (S302) a subsequent silicon oxide layer in the trench; then using a sub-atmospheric chemical vapor deposition (SACVD) process of a silicon oxide film is deposited (S303) in the trench, this is also referred to herein SACVD silicon oxide film for convenience. 淀积过程中,将半导体衬底放入反应室中,将反应室内的压力控制在300-500Torr;向反应室中通入氦气、氧气和正硅酸乙脂,流量分别为氦气(He)流量:500-2000sccs;氧气(03)流量:10000-20000sccs;正硅酸乙脂(TEOS)流量:1000-3000sccs。 Deposition process, the semiconductor substrate placed in the reaction chamber, the reaction chamber pressure is controlled 300-500Torr; into the reaction chamber of helium, oxygen and TEOS, respectively, the flow rate of helium (He) flow: 500-2000sccs; oxygen (03) flow rate: 10000-20000sccs; tetraethyl orthosilicate (TEOS) flow rate: 1000-3000sccs. 利用SACVD工艺在沟槽中淀积的氧化硅具有较强的拉应力(tensile stress )。 SACVD deposition process of the silicon oxide in the trench with a strong tensile stress (tensile stress). 然后,再利用HDP-CVD工艺在沟槽内的上述氧化硅表面继续淀积氧化硅(S304 ),这里为方便起见同样将该氧化硅膜称为HDP膜。 Then, using the silicon oxide surface of the HDP-CVD process in the deposition of a silicon oxide trench continued (S304,), where the same film is a silicon oxide film HDP called for convenience. 在这个过程中,反应室内的压力控制在5-12mTorr;产生等离子体射频功率为6000-9000W;向反应室中通入氢气、氧气和硅烷(SiH4), 氢气(HJ的流量为200-1000sccs;氧气(0》的流量为30-36sccs;硅烷(SiHj 的流量为10-14. 5sccs。由HDP-CVD工艺淀积的氧化硅膜层具有很高的致密程度,因而其具有较高的压应力。接着,重复执行步骤S303和S304,利用这种SACVD工艺和HDP-CVD工艺交替淀积氧化硅膜的方式,直至填满沟槽。通过控制沟槽中SACVD和HDP-CVD淀积的数量和厚度可以使沟槽内填充的氧化硅的应力相互抵消。在接下来的工艺步骤中,对衬底进行快速热退火(RTA)处理(S305 ),温度控制在900-1100°C,时间为20-50s。以进一步消除衬垫氧化层和沟槽侧壁与填充的氧化硅之间的应力;最后通过化学机械研磨对沟槽进行平坦化(S306 )。图4为说明图3所示方法的浅沟槽隔离结构的简化剖面示意图,所 In this process, the pressure in the reaction chamber is controlled 5-12mTorr; generating a plasma and RF power of 6000-9000W; the reaction chamber into hydrogen, oxygen and silane (of SiH4), hydrogen gas flow rate (HJ is 200-1000sccs; oxygen (0 "traffic to 30-36sccs; silane (10-14 5sccs flow SiHj is deposited by HDP-CVD process a silicon oxide film has a high degree of densification, and thus it has a higher compressive stress. Next, steps S303 and S304, are repeatedly performed, and the process using this SACVD HDP-CVD process a silicon oxide film is deposited in an alternating manner until filled in the grooves. SACVD trench by controlling the number and HDP-CVD deposited and the thickness of the stress can be filled with silicon oxide within the trench cancel each other. in the next process step, the substrate is a rapid thermal annealing (RTA) treated (S305), temperature controlled at 900-1100 ° C, for 20 . -50s to further eliminate stress between the pad oxide layer and the silicon oxide filled trench sidewalls; finally planarized (S306) of the trench by chemical mechanical polishing method shown in FIG. 4 is a 3 in FIG. a simplified cross sectional schematic diagram of the shallow trench isolation structure, the 述示意图只是实例,其在此不应过度限制本发明保护的范围。如图4所示,形成掩膜层和衬垫氧化层的步骤与前述图2A和图2B描述的相同,亦是在提供的半导体衬底1QQ上依次形成氧化硅层110和氮化硅层120,氮化硅层120也可以是氮化硅或氮氧化硅的混合物。氧化硅层110和氮化硅层120可以提供热生长或化学气相淀积等方法形成。氧化硅110作为半导体衬底10Q和氮化硅120之间的过渡层。氮化硅120具有较高的致密程度,可以作为后续的刻蚀停止层和化学机械研磨(CMP)的研磨阻挡层。图案化上述掩膜层以露出对应沟槽位置的半导体衬底,在衬底中刻蚀出沟槽,并在沟槽中形成衬垫氧化层。 然后,在沟槽中利用亚常压化学气相淀积(SACVD)工艺淀积氧化硅层141, 再利用HDP-CVD工艺在沟槽内的上述氧化硅层表面继续淀积氧化硅膜142。接下来,继续利用SACVD工艺淀积氧化 Said diagrams are merely examples, which should not unduly limit the scope of the present invention is shown in Figure 4, he is formed. 2A and 2B the same steps described in the aforementioned FIG FIGS pad oxide layer and the masking layer, is also provided successively forming a silicon oxide layer 110 and nitride layer 120 on the semiconductor substrate 1QQ, the silicon nitride layer 120 may also be a mixture of silicon oxide, silicon nitride or silicon oxide layer 110 and the silicon nitride layer 120 may provide heat growth or chemical vapor deposition or the like formed as a silicon oxide buffer layer 110 between the silicon semiconductor substrate 120 and 10Q. silicon nitride 120 having a high degree of densification, as a subsequent chemical etch stop layer and polishing mechanical polishing (CMP) of the barrier layer above the patterned mask layer to expose the semiconductor substrate corresponding to the position of the trench, etching trenches in the substrate, and forming a pad oxide layer in the trench. then, using sub-atmospheric chemical vapor deposition in trench (SACVD) process of depositing a silicon oxide layer 141, using the HDP-CVD process and then the surface of the silicon oxide layer is deposited in the trench continues to 142. then the silicon oxide film, oxidation using a SACVD deposition process continues 膜143,继续利用HDP-CVD工艺在氧化硅膜143上淀积氧化硅膜144。由于具有拉应力的SACVD氧化硅膜和具有压应力的HDP氧化硅膜堆叠在一起后,膜的应力相互抵消,沟槽中填充的SACVD 膜141和143, HDP膜142和144堆叠在一起组成的堆栈结构从整体上即表现为无应力状态。这里同样需要说明的是,本实施例中,SACVD和HDPCVD循环交替淀积的次数可以视沟槽深度而定,本领域技术人员可以灵活掌握。 Film 143, continued use of HDP-CVD process depositing a silicon oxide film 144. Since the silicon oxide film having a tensile stress SACVD, and HDP silicon oxide film having compressive stress are stacked together after the stress film cancel each other on the silicon oxide film 143 , the trenches are filled SACVD film 141 and 143, HDP film 142 and 144 are stacked together to form a stacked structure from whole showed an unstressed state. here again be noted that, in this embodiment, SACVD cycle and HDPCVD depending on the number of times alternately deposited groove depth may be, those skilled in the art to have flexibility. 本实施例中,氧 Embodiment, the oxygen present embodiment

化硅膜141、 142、 143和134已经将沟槽填满。 Silicon film 141, 142, 134 have grooves 143 and fill. 当沟槽深度较高时,可适当增加循环淀积的次数;当深度较小时,可适当减少循环淀积的次数。 When higher groove depth, number of cycles can be increased deposition; when the depth is small, the number of cycles can be reduced appropriately deposited. 此外, 每层SACVD膜和HDPCVD膜的厚度淀积顺序也可以根椐实际情况而定,即可以先淀积SACVD膜也可以先淀积HDP膜,本领域技术人员可以膜的厚度做出许多修改和变化,只要使沟槽中形成SACVD膜和HDPCVD膜的堆栈结构在整体上表现为无应力状态即可。 Further, the thickness of each film, and SACVD deposition sequence HDPCVD film may be noted in the actual circumstances, i.e., the film may also be first deposited to SACVD HDP deposited films, those skilled in the art may make many modifications to the thickness of the film and variations, as long as the stack structure is formed and the film SACVD HDPCVD film showed that the trench can be in an unstressed state as a whole. 本实施例中,同样可以利用前述如表2所示的SACVD 膜和HDP膜的不同厚度组合,获得无应力状态的堆栈结构。 Embodiment, the same may be utilized as shown in Table 2, films with different thickness SACVD combinations HDP film of the present embodiment, to obtain an unstressed state of the stack structure. 还可根据CMOS器件沟道和栅极结构应力工程设计的需要,使SACVD膜和HDPCVD膜的堆栈结构在整体上表现出特定大小和方向的应力状态。 The device further required channel CMOS gate structure and stress engineering the film and the stack structure SACVD HDPCVD film exhibits a stress state of a particular size and direction as a whole. 本发明的浅沟槽隔离结构,在沟槽中填充的氧化硅具有如图2C和图4所示的结构形式,其整体应力水平处于极低或无应力状态。 Shallow trench isolation structure according to the present invention, filling in the trench and the silicon oxide having a structure shown in FIG. 2C in FIG. 4, the overall stress level at which little or no stress. 因此,在通过退火消除沟槽侧壁和衬垫氧化层与填充氧化硅之间的应力之后,STI隔离结构的应力水平便处于极低或基本无应力状态。 Thus, after the stress relief between the pad oxide layer and the sidewalls of the trench filled with silicon oxide by annealing, stress levels will STI isolation structures in a very low or substantially unstressed state. 当然,也可根据CMOS器件沟道和栅极结构应力工程设计的需要,使SACVD膜和HDPCVD膜的堆栈结构在整体上表现出特定大小和方向的应力状态。 Of course, according to need and the gate CMOS device channel engineering structural stresses the film and a stacked structure SACVD HDPCVD film exhibits a stress state of a particular size and direction as a whole. 本发明虽然以较佳实施例公开如上,但其并不是用来限定本发明,任何本领域技术人员在不脱离本发明的精神和范围内,都可以做出可能的变动和修改,因此本发明的保护范围应当以本发明权利要求所界定的范围为准。 While the preferred embodiments of the present invention to the above disclosed embodiments, but not intended to limit the present invention, anyone skilled in the art without departing from the spirit and scope of the invention, can be made possible variations and modifications of the present invention is thus the scope of claims of the invention should be defined by the scope of equivalents.

Claims (22)

1、 一种在半导体器件中形成浅沟槽隔离结构的方法,包括:在半导体衬底上形成掩膜层;图案化所述掩膜层以露出对应沟槽位置的半导体衬底;刻蚀所述村底形成沟槽并在沟槽中形成衬垫氧化层;在所述沟槽中轮流淀积第一绝缘介质和第二绝缘介质直至填满所述沟槽;对所述半导体衬底进行快速热退火处理; 平坦化所述绝缘介质以形成、浅沟槽隔离结构。 1. A method for forming a shallow trench isolation structure in a semiconductor device, comprising: forming a mask layer on a semiconductor substrate; patterning the mask layer to expose the semiconductor substrate corresponding to the position of the trench; etching the village and said bottom forming a trench is formed in the pad oxide layer in the trench; alternately depositing a first dielectric and a second dielectric in said trench to fill up the trenches; the semiconductor substrate rapid thermal annealing process; planarizing said insulating medium to form a shallow trench isolation structure.
2、 根据权利要求l所述的方法,其特征在于:所述第一绝缘介质是利用亚常压化学气相淀积工艺淀积的绝缘介质。 2. The method according to claim l, wherein: said first dielectric insulating medium is a sub-atmospheric chemical vapor deposition using a deposition process.
3、 根据权利要求l所述的方法,其特征在于:所述第二绝缘介质是利用高密度等离子体化学气相淀积工艺淀积的绝缘介质。 3. The method as claimed in claim l, wherein: said second dielectric insulating medium using a high density plasma chemical vapor deposition process deposition.
4、 根据权利要求l所述的方法,其特征在于:所述第一绝缘介质是利用高密度等离子体化学气相淀积工艺淀积的绝缘介质。 4. The method according to claim l, wherein: said first insulating medium using a high density plasma chemical vapor deposition dielectric deposition process.
5、 根据权利要求l所述的方法,其特征在于:所述第二绝缘介质是利用亚常压化学气相淀积工艺淀积的绝缘介质。 5. The method as claimed in claim l, wherein: said second insulating medium using sub-atmospheric chemical vapor deposition dielectric deposition process.
6、 根据权利要求2、 3、 4或5所述的方法,其特征在于:所述绝缘介质为氧化硅。 6. The method of claim 2, 3, 4 or claim 5, wherein: the dielectric is silicon oxide.
7、 根据权利要求2或5所述的方法,其特征在于:所述亚常压化学气相淀积的工艺参数包括:压力:300-500Torr; 氦气(He)流量:5QG-2G0()sccs; 氧气(03)流量:10000-20000sccs; 正硅酸乙脂(TE0S)流量:1000-3000sccs。 7. A method according to claim 2 or claim 5, wherein: said sub-atmospheric chemical vapor deposition process parameters include: pressure: 300-500Torr; helium (He) flow rate: 5QG-2G0 () sccs ; oxygen (03) flow rate: 10000-20000sccs; tetraethyl orthosilicate (TE0S) flow rate: 1000-3000sccs.
8、 根据权利要求3或4所述的方法,其特征在于:所述高密度等离子体化学气相淀积的工艺参数包括: 压力:5-12mTorr; 射频功率:6000-9000W; 氢气(H2)流量:200-1000sccs; 氧气(02)流量:30-36sccs; 硅烷(SiH4)流量:10-14.5sccs。 8. The method of claim 3 or claim 4, wherein: said high-density plasma chemical vapor deposition process parameters include: pressure: 5-12mTorr; RF power: 6000-9000W; hydrogen (H2) flow rate : 200-1000sccs; oxygen (02) flow rate: 30-36sccs; silane (SiH4) flow rate: 10-14.5sccs.
9、 根据权利要求l所述的方法,其特征在于:所述快速热退火的温度为900-IIO(TC;时间为20-50s。 9. The method according to claim l, wherein: the rapid thermal annealing temperature of 900-IIO (TC; time 20-50s.
10、 一种在半导体器件中形成浅沟槽隔离结构的方法,包括: 在半导体衬底上形成掩膜层;图案化所述掩膜层以露出对应沟槽位置的半导体衬底; 刻蚀所迷衬底形成沟槽并在沟槽中形成村垫氧化层; 在所述沟槽中循环交替淀积和减薄第一绝缘介质和第二绝缘介质直至填满所述沟槽;对所述半导体衬底进行快速热退火处理;平坦化所述绝缘介质以形成浅沟槽隔离结构。 10. A method of forming a shallow trench isolation structure in a semiconductor device, comprising: forming a mask layer on a semiconductor substrate; patterning the mask layer to expose the semiconductor substrate corresponding to the position of the trench; etching the forming a trench formed in the substrate and fans village pad oxide layer in the trench; and circulating alternately depositing a first thin insulating dielectric medium and the second medium until filling the trench in said trench; the the semiconductor substrate rapid thermal annealing process; planarizing said insulating medium to form a shallow trench isolation structure.
11、 根据权利要求10所述的方法,其特征在于:所述第一绝缘介质是利用亚常压化学气相淀积工艺淀积的绝缘介质。 11. The method of claim 10, wherein: said first insulating medium using sub-atmospheric chemical vapor deposition dielectric deposition process.
12、 根据权利要求IO所述的方法,其特征在于:所述第二绝缘介质是利用高密度等离子体化学气相淀积工艺淀积的绝缘介质。 12. The method of claim IO, wherein: said second insulating medium using a high density plasma chemical vapor deposition dielectric deposition process.
13、 根据权利要求10所述的方法,其特征在于:所述第一绝缘介质是利用高密度等离子体化学气相淀积工艺淀积的绝缘介质。 13. The method of claim 10, wherein: said first insulating medium using a high density plasma chemical vapor deposition dielectric deposition process.
14、 根据权利要求IO所述的方法,其特征在于:所述第二绝缘介质是利用亚常压化学气相淀积工艺淀积的绝缘介质。 14. The method of claim IO, wherein: said second dielectric insulating medium is a sub-atmospheric chemical vapor deposition using a deposition process.
15、 根据权利要求11、 12、 13或14所述的方法,其特征在于:所述绝缘介质为氧化硅。 15. The method of 11, 12, 13 or claim 14, wherein: the dielectric is silicon oxide.
16、 根据权利要求11或14所述的方法,其特征在于:所述亚常压化学气相淀积的工艺参数包括:压力:300-500Torr; 氦气(He)流量:500-2000sccs; 氧气(0》流量:10000-20000sccs; 正硅酸乙脂(TEOS)流量:1000-3000sccs。 16. The method of claim 11 or 14, wherein: said process parameter sub-atmospheric chemical vapor deposition comprising: pressure: 300-500Torr; helium (He) flow rate: 500-2000sccs; Oxygen ( 0 "flow rate: 10000-20000sccs; tetraethyl orthosilicate (TEOS) flow rate: 1000-3000sccs.
17、 根据权利要求12或13所述的方法,其特征在于:所述高密度等离子体化学气相淀积的工艺参数包括:压力:5-12mTorr; 射频功率:6000-9000W;氢气(H2)流量:200-1 OOOsccs;氧气(02)流量:30-36sccs;硅烷(SiH4)流量:10-14.5sccs。 17. The method of claim 12 or claim 13, wherein: said high-density plasma chemical vapor deposition process parameters include: pressure: 5-12mTorr; RF power: 6000-9000W; hydrogen (H2) flow rate : 200-1 OOOsccs; oxygen (02) flow rate: 30-36sccs; silane (SiH4) flow rate: 10-14.5sccs.
18、 根据权利要求10所述的方法,其特征在于:所述快速热退火的温度900-1100°C;时间为20-50s。 18. The method of claim 10, wherein: said rapid thermal annealing temperature of 900-1100 ° C; time 20-50s.
19、 根据权利要求10所述的方法,其特征在于:利用回刻工艺对所述绝缘介质层进行减薄。 19. The method of claim 10, wherein: said insulating dielectric layer is thinned using an etch-back process.
20、 一种浅沟槽隔离结构,包括半导体村底和衬底中形成的沟槽,所述沟槽中填充有绝缘介质,其特征在于:所述绝缘介质包括第一绝缘介质和第二绝缘介质,所述第一绝缘介质和第二绝缘介质彼此堆叠形成堆栈结构。 20. A shallow trench isolation structure, comprising a semiconductor substrate and a trench formed in the substrate, the trench is filled with an insulating medium, characterized in that: said insulating medium comprises a first and a second insulating dielectric insulating medium, the first medium and the second dielectric insulating stacked together to form a stack structure.
21、 根据权利要求20所述的浅沟槽隔离结构,其特征在于:所述第一绝缘介质是利用亚常压化学气相淀积工艺淀积的绝缘介质,所述第二绝缘介质是利用高密度等离子体化学气相淀积工艺淀积的绝缘介质。 21, shallow trench isolation structure as claimed in claim 20, wherein: said first insulating medium using sub-atmospheric chemical vapor deposition dielectric deposition process, using the second insulating medium is a high insulating medium density plasma chemical vapor deposition process deposition.
22、 根据权利要求20所述的浅沟槽隔离结构,其特征在于:所述第一绝缘介质是利用高密度等离子体化学气相淀积工艺淀积的绝缘介质,所述第二绝缘介质是利用亚常压化学气相淀积工艺淀积的绝缘介质。 22, shallow trench isolation structure as claimed in claim 20, wherein: said first dielectric insulating medium is a high density plasma chemical vapor deposition deposition process, using the second insulating medium sub-atmospheric chemical vapor deposition dielectric deposition process.
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