CN116613215A - Linear planar power VDMOS structure and preparation method thereof - Google Patents

Linear planar power VDMOS structure and preparation method thereof Download PDF

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CN116613215A
CN116613215A CN202310761606.6A CN202310761606A CN116613215A CN 116613215 A CN116613215 A CN 116613215A CN 202310761606 A CN202310761606 A CN 202310761606A CN 116613215 A CN116613215 A CN 116613215A
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implantation
injection
jfet
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苗东铭
杨世红
余远强
徐永年
李小红
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Shaanxi Reactor Microelectronics Co ltd
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Shaanxi Reactor Microelectronics Co ltd
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    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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Abstract

The invention provides a linear planar power VDMOS structure and a preparation method thereof, which are used for solving the technical problems that the conventional VDMOS structure is only suitable for small-size power MOS, and when a barrier shielding structure is formed by adopting high-concentration high-energy impurity ion implantation and a secondary annealing scheme, the process is difficult to realize, the stability is poor and the resistance of a JFET region is overlarge. The VDMOS structure preparation method provided by the invention has the advantages that one photoetching and etching process is added, and the common low-energy ion implantation and annealing process is adopted, so that the ion implantation and annealing process parameters do not need to be finely controlled, the process realization difficulty is reduced, and the structure reliability is improved. Meanwhile, as the ion implantation energy of the Shield region is lower, the junction depth of the Shield region in the VDMOS structure is shallower, the depth of the JFET region is reduced, and the resistance of the JFET region is reduced; in addition, the lateral extension length of the Shield region is defined by adopting a photoetching pattern, so that the additional lateral extension length of the Shield region relative to the Base region is controllable, and the method is suitable for improving the Id-Vd linear characteristic of the large-size power MOS device.

Description

Linear planar power VDMOS structure and preparation method thereof
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a linear planar power VDMOS structure and a preparation method thereof.
Background
The conventional planar VDMOS device has the advantages of high input resistance, high switching speed, low switching loss, and the like, and is widely used as a power switch in high frequency, consumer electronics, household appliances, embedded systems, electric vehicles, photovoltaics, and other industrial systems. However, when the power amplifier is used as linear application such as power radio frequency amplification, linear voltage regulation and automobile fan control, the input and output characteristics are linear due to the square relation between drain current and grid voltage caused by channel pinch-off due to high Vds voltage, so that output signals are distorted, and stable output of a power management system is not facilitated. In the prior art, high-energy ion implantation is adopted before the base region of the VDMOS is implanted and doped, a high-concentration reverse gradient doped region is formed at the bottom of the base region and annealed, and due to the influence of the low base region implantation concentration and the secondary base region implantation annealing, the high-concentration reverse doped region can form stronger transverse expansion relative to the base region in the base region and the gate structure direction of the MOS device, when the MOS device bears higher turn-off Vds voltage, a potential shielding effect is generated on a base region channel, the channel pinch-off of the MOSFET under the high Vds voltage is relieved, the device works in a linear region in a wider Vds voltage range, and the linear output characteristic is improved. However, in the technical scheme, the formation of the barrier shielding region and the additional transverse expansion of the barrier shielding region relative to the base region depend on the accurate control of the high-concentration high-energy impurity ion implantation and annealing process, and the process is difficult to realize and has poor stability; meanwhile, the junction depth of the finally formed shielding structure is too deep and the length of the JFET region is too large due to high-energy ion implantation, so that the resistance of the JFET region is increased; in addition, the extra lateral expansion length of the barrier shielding region relative to the base region is realized through controlling impurity ion implantation and annealing processes, so that the absolute value of the extra lateral expansion length is very limited, the method is only suitable for small-size power MOS, and the shielding effect of a shielding structure on MOS channel potential is difficult to realize for larger-size power MOS devices.
Disclosure of Invention
The invention aims to solve the technical problems that the conventional VDMOS structure is only suitable for small-size power MOS, and the process is difficult to realize and poor in stability and the resistance of a JFET region is overlarge when a barrier shielding structure is formed by adopting a high-concentration high-energy impurity ion implantation and secondary annealing scheme, and provides a linear planar power VDMOS structure and a preparation method thereof.
In order to achieve the above object, the technical solution of the present invention is:
the linear planar power VDMOS structure is characterized by comprising a silicon substrate, a Drift region positioned on the upper surface of the silicon substrate and a drain electrode positioned on the lower surface of the silicon substrate;
the upper surface of the Drift region is provided with a JFET region;
the two sides of the JFET region are respectively provided with a Shield region extending transversely from the outer side to the inner side;
the Base region transversely extending from the outer side to the inner side is arranged in the Shield region, and the upper surface of the Base region exceeds the upper surface of the Shield region and is flush with the upper surface of the JFET region; the lateral extension length of the Shield region is greater than that of the Base region;
the doping peak concentration of the JFET region is higher than that of the Drift region, the doping concentration of the Shield region is higher than that of the Base region, and the corresponding depths of the doping peak concentrations of the JFET region and the Shield region are both positioned at the bottom of the Base region;
The Base region is internally provided with a Source region which transversely extends from the outer side to the inner side, and the upper surface of the Source region is flush with the upper surface of the Base region; the Base region has a lateral extension greater than the Source region;
an active electrode contact area is arranged in the Source area and close to the edge of the wafer;
the upper surface of the JFET region is provided with a gate oxide layer, and the gate oxide layer extends to the upper surfaces of the Base region and the Source region towards two sides;
a gate electrode is arranged on the upper surface of the gate oxide layer;
injection shielding oxide layers are arranged on the two sides and the upper surface of the gate electrode, and the positions of the injection shielding oxide layers corresponding to the two sides of the gate electrode are in contact with the gate electrode;
the upper surfaces of the Source region and the injection shielding oxide layer are provided with dielectric layers;
an active electrode is arranged on the upper surface of the dielectric layer, and two sides of the active electrode are in contact with the active electrode contact area and the Base area.
Further, the silicon substrate, the Drift region, the JFET region and the Source region are of N type; the Shield region and the Base region are of a P type;
or the silicon substrate, the Drift region, the JFET region and the Source region are of a P type; the Shield region and the Base region are of N type.
The invention also provides another linear planar power VDMOS structure, which is characterized by comprising a silicon substrate, a Drift region positioned on the upper surface of the silicon substrate and a drain electrode positioned on the lower surface of the silicon substrate;
The upper surface of the Drift region is provided with a JFET region;
the two sides of the JFET region are respectively provided with a Shield region extending from the outer side to the inner side in the transverse direction, and the Shield regions extend downwards into the Drift region;
the Base region transversely extending from the outer side to the inner side is arranged in the Shield region, and the upper surface of the Base region exceeds the upper surface of the Shield region and is flush with the upper surface of the JFET region; the lateral extension length of the Shield region is greater than that of the Base region;
the doping peak concentration of the JFET region is higher than that of the Drift region, the doping concentration of the Shield region is higher than that of the Base region, and the corresponding depths of the doping peak concentrations of the JFET region and the Shield region are both positioned at the bottom of the Base region;
the Base region is internally provided with a Source region which transversely extends from the outer side to the inner side, and the upper surface of the Source region is flush with the upper surface of the Base region; the Base region has a lateral extension greater than the Source region;
an active electrode contact area is arranged in the Source area and close to the edge of the wafer;
the upper surface of the JFET region is provided with a gate oxide layer, and the gate oxide layer extends to the upper surfaces of the Base region and the Source region towards two sides;
a gate electrode is arranged on the upper surface of the gate oxide layer;
injection shielding oxide layers are arranged on the two sides and the upper surface of the gate electrode, and the positions of the injection shielding oxide layers corresponding to the two sides of the gate electrode are in contact with the gate electrode;
The upper surfaces of the Source region and the injection shielding oxide layer are provided with dielectric layers;
and an active electrode is arranged on the upper surface of the dielectric layer, and the source electrode is respectively contacted with the source electrode contact area and the Base area.
Further, the silicon substrate, the Drift region, the JFET region and the Source region are of N type; the Shield region and the Base region are of a P type;
or the silicon substrate, the Drift region, the JFET region and the Source region are of a P type; the Shield region and the Base region are of N type.
The invention also provides a preparation method of the linear planar power VDMOS structure, which is characterized by comprising the following steps:
selecting a silicon substrate as a wafer, and depositing an epitaxial layer on the silicon substrate to form a Drift region; performing first type ion implantation on the Drift region, annealing the first type ion implantation after the implantation is finished, and forming an initial JFET region on the upper surface of the Drift region after annealing;
forming an injection masking pattern at the middle position of the upper surface of the initial JFET region by adopting a photoetching process, then performing second-type ion injection on the upper surface of the JFET region, and respectively forming first injection regions at the two sides of the initial JFET region corresponding to the positions where the injection masking pattern is not formed;
removing the implantation masking pattern on the surface of the initial JFET region, and carrying out first type ion implantation on the surface of the initial JFET region to change the second type impurity on the upper surface of the first implantation region into first type impurity, and simultaneously improving the impurity concentration of the initial JFET region and forming an integrated JFET region with the part of the upper surface of the first implantation region corresponding to the first type impurity;
Thermally growing an oxide layer on the upper surface of the JFET region to form a gate oxide layer; meanwhile, in the process of thermally growing the oxide layer, the second type ions injected by the first injection region generate thermal diffusion, so that the first injection region becomes a doped region;
sequentially performing polysilicon deposition and dry-oxygen oxidation processes on the upper surface of the gate oxide layer, and forming a gate electrode and injection shielding oxide layer structure through a photoetching process; thinning two sides of the gate oxide layer, wherein the gate oxide layer of the thinned part is used as a gate injection window;
performing second-type ion implantation on the local part of the JFET region through a grid implantation window to form a second implantation region;
performing an annealing process on the second injection region, and changing the second injection region into a Base region after annealing; simultaneously, along with the annealing process, ions injected into the doped region generate thermal diffusion to form a Shield region;
performing first-type ion implantation on the upper surface of the Base region through a gate implantation window to form a third implantation region;
performing an annealing process on the third injection region, and forming a Source region after annealing;
depositing a dielectric layer on the upper surface of the wafer for forming the Source region; forming a metal electrode contact hole on the dielectric layer through a photoetching process; performing second-type ion implantation through the metal electrode contact hole, and annealing after implantation to form a source electrode contact region; depositing an AlSiCu metal layer on the upper surface of a wafer with an active electrode contact area, and forming a source electrode through photoetching and etching processes;
And 11, evaporating a Ti/Ni/Ag metal layer on the lower surface of the silicon substrate (1) to form a drain electrode, thereby completing the preparation of the linear planar power VDMOS structure based on the graphical injection and impurity compensation process.
Further, the silicon substrate is of an N type, the first type of ions are of an N type, and the second type of ions are of a P type;
or the silicon substrate is of a P type, the first type of ions are of a P type, and the second type of ions are of an N type.
Further, in step 1 ], the silicon substrate is of an n+ type, the epitaxial layer is of an N-type, the Drift region is of an N-type, and the initial JFET region is of an N-type; the first type of ion is arsenic ion with implantation energy of 40-60 KeV and implantation dosage of 0.8-1.2E13 cm -2 The method comprises the steps of carrying out a first treatment on the surface of the The annealing temperature of arsenic ion implantation is 900-950 ℃ and the annealing time is 70-80 min;
in the step 2, the second type of ions are boron ions, the implantation energy is 40-50 KeV, and the implantation dosage is 2-4E 13 cm -2 The method comprises the steps of carrying out a first treatment on the surface of the The first injection region is of a P+ type;
in the step 3, the first type of ions are arsenic ions, the implantation energy is 40-50 KeV, and the implantation dosage is 1-2E 13 cm -2 The method comprises the steps of carrying out a first treatment on the surface of the The P-type impurity on the upper surface of the first injection region is changed into N-type impurity, and the JFET region is of N+ type;
in the step 4, the thermal growth process of the oxide layer is a dry-oxygen oxidation process; the thickness of the gate oxide layer is 50-80 nm; the doped region is of a P+ type;
In the step 5, the two sides of the gate oxide layer are thinned by adopting a dry etching process;
in the step 6, the second type of ions are boron ions, the implantation energy is 30-40 KeV, and the implantation dosage is 1-1.5E13 cm -2 The method comprises the steps of carrying out a first treatment on the surface of the The second injection region is of a P type;
in the step 7, the annealing temperature of the second injection region is 1100-1150 ℃ and the annealing time is 70-80 min; the Shield region is of a P+ type;
in the step 8, the first type of ions are arsenic ions, the implantation energy is 50-60 KeV, and the implantation dosage is 0.5-1.0E16 cm -2 The method comprises the steps of carrying out a first treatment on the surface of the The third injection region is of an N+ type;
in the step 9, the annealing temperature of the third injection region is 950-980 ℃ and the annealing time is 120-150 min; the Source region is of an N+ type;
in the step 10, the thickness of the dielectric layer is 1.0-1.5 mm; the second type of ion being BF 2 The injection energy is 60-80 KeV, and the injection dosage is 3E 14-5E 14; BF (BF) 2 The annealing temperature of the injection is 900-1000 ℃ and the annealing time is 20-30 min; the AlSiCu metalThe thickness of the layer is 4-6 μm.
The invention also provides a preparation method of the linear planar power VDMOS structure, which is characterized by comprising the following steps:
selecting a silicon substrate as a wafer, and depositing an epitaxial layer on the silicon substrate to form a Drift region; performing second-type ion implantation on the Drift region, and forming a first implantation region on the upper surface of the Drift region;
Performing first-type ion implantation on the upper surface of the first implantation region, annealing the implanted first-type ions, and forming an initial JFET region on the upper surface of the first implantation region;
forming implantation masking patterns on two sides of the upper surface of the initial JFET region by adopting a photoetching process, and then carrying out first type ion implantation on the upper surface of the initial JFET region to enable second type impurities on the first implantation region corresponding to the positions where the implantation masking patterns are not formed to be changed into first type impurities, and simultaneously enabling the impurity concentration of the initial JFET region to be improved and forming an integral JFET region with the part of the first implantation region which is changed into first type impurities;
thermally growing an oxide layer on the upper surface of the JFET region to form a gate oxide layer; meanwhile, in the process of thermally growing the oxide layer, the second type ions injected by the first injection region generate thermal diffusion, so that the first injection region becomes a doped region;
sequentially performing polysilicon deposition and dry-oxygen oxidation processes on the upper surface of the gate oxide layer, and forming a gate electrode and injection shielding oxide layer structure through a photoetching process; thinning two sides of the gate oxide layer, wherein the gate oxide layer of the thinned part is used as a gate injection window;
performing second-type ion implantation on the local part of the JFET region through a grid implantation window to form a second implantation region;
Performing an annealing process on the second injection region, and changing the second injection region into a Base region after annealing; simultaneously, along with the annealing process, ions injected into the doped region generate thermal diffusion to form a Shield region;
performing first-type ion implantation on the upper surface of the Base region through a gate implantation window to form a third implantation region;
performing an annealing process on the third injection region, and forming a Source region after annealing;
depositing a dielectric layer on the upper surface of the wafer to form a Source region; forming a metal electrode contact hole on the dielectric layer through a photoetching process; performing second-type ion implantation through the metal electrode contact hole, and annealing after implantation to form a source electrode contact region; depositing an AlSiCu metal layer on the upper surface of a wafer with an active electrode contact area, and forming a source electrode through photoetching and etching processes;
and 11, evaporating a Ti/Ni/Ag metal layer on the lower surface of the silicon substrate to form a drain electrode, thereby completing the preparation of the linear planar power VDMOS structure based on the graphical injection and impurity compensation process.
Further, the silicon substrate is of an N type, the first type of ions are of an N type, and the second type of ions are of a P type;
or the silicon substrate is of a P type, the first type of ions are of a P type, and the second type of ions are of an N type.
Further, in step 1 ], the silicon substrate is of an n+ type, the epitaxial layer is of an N-type, the Drift region is of an N-type, and the first injection region is of a p+ type; the second type of ion is boron ion with implantation energy of 40-60 KeV and implantation dosage of 4.0-5.0E13 cm -2 ；
In the step 2, the first type of ions are arsenic ions, the implantation energy is 60-80 KeV, and the implantation dosage is 3-4E 13cm -2 Annealing temperature is 950-1000 ℃ and annealing time is 70-80 min; the initial JFET region (3-1) being N-type;
in the step 3, the first type of ions are arsenic ions, the implantation energy is 60-80 KeV, and the implantation dosage is 2-3E 13cm -2 The method comprises the steps of carrying out a first treatment on the surface of the P-type impurities corresponding to the position of the non-implanted masking pattern on the first implantation region are changed into N-type impurities, and the JFET region is of an N+ type;
in the step 4, the thermal growth process of the oxide layer is a dry-oxygen oxidation process; the thickness of the gate oxide layer is 50-80 nm; the doped region is of a P+ type;
in the step 5, the two sides of the gate oxide layer are thinned by adopting a dry etching process;
in step 6 ], the second type is separatedThe ion is boron ion, the implantation energy is 30-40 KeV, the implantation dosage is 1-1.5E13 cm -2 The method comprises the steps of carrying out a first treatment on the surface of the The second injection region is of a P type;
in the step 7, the annealing temperature of the second injection region is 1100-1150 ℃ and the annealing time is 70-80 min; the Shield region is of a P+ type;
In the step 8, the first type of ions are arsenic ions, the implantation energy is 50-60 KeV, and the implantation dosage is 0.5-1.0E16 cm -2 The method comprises the steps of carrying out a first treatment on the surface of the The third injection region is of an N+ type;
in the step 9, the annealing temperature of the third injection region is 950-980 ℃ and the annealing time is 120-150 min; the Source region is of an N+ type;
in the step 10, the thickness of the dielectric layer is 1.0-1.5 mm; the second type of ion being BF 2 The injection energy is 60-80 KeV, and the injection dosage is 3E 14-5E 14; BF (BF) 2 The annealing temperature of the injection is 900-1000 ℃ and the annealing time is 20-30 min; the thickness of the AlSiCu metal layer is 4-6 mu m.
Compared with the prior art, the invention has the following beneficial effects:
1. compared with the traditional VDMOS structure, the junction depth of the Shield region in the VDMOS structure is shallower, so that the depth of the JFET region is reduced, and the resistance of the JFET region can be effectively reduced; meanwhile, the Shield region in the linear planar power VDMOS structure based on the graphical ion implantation is defined through a photoetching graph, so that the extra transverse extension length of the Shield region relative to the Base region is of a controllable design, and the method is suitable for improving the Id-Vd linear characteristic of a large-size power MOS device.
2. Compared with the prior art that the barrier shielding structure is formed by high-energy ion implantation and secondary annealing, the preparation method of the linear planar power VDMOS structure provided by the invention has the advantages that the primary photoetching and etching processes are added in the process, and the common low-energy ion implantation and annealing processes are adopted, so that the ion implantation and annealing process parameters do not need to be finely controlled, the process implementation difficulty is greatly reduced, and the structure reliability is improved.
3. Compared with the prior art that the Shield region is formed by high-energy ion implantation, the junction depth of the Shield region is deeper and uncontrollable, and the resistance of the JFET region is overlarge.
4. The preparation method of the linear planar power VDMOS structure provided by the invention adopts the photoetching pattern to define the transverse extension length of the Shield region, and the extra transverse extension length of the Shield region relative to the Base region can be controlled by adjusting the transverse dimension of the photoetching pattern, so that the preparation method is suitable for improving the Id-Vd linear characteristic of a large-size power MOS device.
Drawings
Fig. 1 is a schematic diagram of a linear planar power VDMOS structure according to a first embodiment of the present invention;
fig. 2 is a schematic diagram of an input-output characteristic curve of a conventional VDMOS structure;
FIG. 3 is a schematic diagram of an input/output characteristic curve according to a first embodiment of the present invention;
fig. 4 is a schematic diagram of a linear planar power VDMOS structure according to a second embodiment of the present invention;
FIG. 5-1 is a schematic diagram of step 1 in the first embodiment of the preparation method of the present invention;
FIG. 5-2 is a schematic diagram of step 2 in the first embodiment of the preparation method of the present invention;
FIGS. 5-3 are schematic views showing the process of the present invention in step 3 of the first embodiment;
FIGS. 5-4 are schematic diagrams of step 4 of the first embodiment of the preparation method of the present invention;
FIGS. 5-5 are schematic views of step 5 of the first embodiment of the method of the present invention;
FIGS. 5-6 are schematic diagrams of step 6 in the first embodiment of the preparation method of the present invention;
FIGS. 5-7 are schematic views of step 7 of the first embodiment of the method of the present invention;
FIGS. 5-8 are schematic diagrams of step 8 in the first embodiment of the preparation method of the present invention;
FIGS. 5-9 are schematic diagrams of step 9 "in the first embodiment of the preparation method of the present invention;
FIGS. 5-10 are schematic views of step 10 in the first embodiment of the preparation method of the present invention;
FIGS. 5-11 are schematic views of step 11 in the first embodiment of the preparation method of the present invention;
FIG. 6-1 is a schematic diagram of step 1 in a second embodiment of the preparation method of the present invention;
FIG. 6-2 is a schematic diagram of step 2 "in the second embodiment of the preparation method of the present invention;
FIG. 6-3 is a schematic diagram of step 3 in example II of the preparation method of the present invention. Specific reference numerals are as follows:
1-a silicon substrate; a 2-Drift region; a 3-JFET region, a 3-1-initial JFET region; a 4-Shield region, a 4-1-first implant region, a 4-2-doped region; a 5-gate oxide layer; 7-gate electrode; 8-implanting a shielding oxide layer structure; a 9-Base region, a 9-1-second implant region; 10-Source region, 10-1-third implant region; 11-a dielectric layer; 12-source electrode contact region; 13-a source electrode; 14-drain electrode.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Example 1
A linear planar power VDMOS structure, as shown in fig. 1, includes a silicon substrate 1, a Drift region 2 on the upper surface of the silicon substrate 1, and a drain electrode 18 on the lower surface of the silicon substrate 1.
The JFET region 3 is arranged on the upper surface of the Drift region 2; due to the impurity doping compensation, the doping peak concentration of JFET region 3 is higher than the doping concentration of Drift region 2. The two sides of the JFET region 3 are respectively provided with a Shield region 4 extending from the outside to the inside; the Shield region 4 is provided with a Base region 9 extending laterally from the outside to the inside, and the upper surface of the Base region 9 exceeds the upper surface of the Shield region 4 and is flush with the upper surface of the JFET region 3. Because the Shield region 4 is located at the same depth of the JFET region 3 by using the patterned ion implantation and doping compensation, the doping concentration of the Shield region 4 is higher than that of the Base region 9, and the lateral extension length of the Shield region 4 is longer than that of the Base region 9. Meanwhile, the doping peak concentration corresponding depth of the JFET region 3 and the Shield region 4 is located at the bottom of the Base region 9. Compared with the prior VDMOS structure, the invention has the advantages that the junction depth of the Shield region can be obtained to be shallower because the ion implantation energy required by the Shield region 4 during ion implantation is lower, the depth of the JFET region is further reduced, and the electrical resistance of the JFET region 3 can be obviously reduced; meanwhile, because the Shield region 4 is defined by a photoetching pattern in the preparation process, the extra transverse extension length of the Shield region 4 relative to the Base region 9 is a controllable design, and the method is suitable for improving the Id-Vd linear characteristic of a large-size power MOS device.
A Source region 10 extending transversely from the outside to the inside is arranged in the Base region 9, and the upper surface of the Source region 10 is flush with the upper surface of the Base region 9; the lateral extension of the Base region 9 is greater than the lateral extension of the Source region 10. An active electrode contact region 12 is disposed in the Source region 10 at a position near the edge of the wafer; the upper surface of the JFET region 3 is provided with a gate oxide layer 5, and the gate oxide layer 5 extends to the upper surfaces of a Base region 9 and a Source region 10 towards two sides; the upper surface of the gate oxide layer 5 is provided with a gate electrode 7; injection shielding oxide layers 8 are arranged on the two sides and the upper surface of the gate electrode 7, and the positions of the injection shielding oxide layers 8 corresponding to the two sides of the gate electrode 7 are in contact with the gate electrode 7; the Source region 10 and the upper surface of the injection shielding oxide layer 8 are provided with a dielectric layer, the upper surface of the dielectric layer 11 is provided with an active electrode 13, and the active electrode 13 is respectively contacted with the Source electrode contact region 12 and the Base region 9 for conducting the active electrode 13.
In the linear planar power VDMOS structure provided by the invention, when the silicon substrate 1 is of an N type, the Drift2, the JFET region 3 and the Source region 10 are of an N type, and the Shield region 4 and the Base region 9 are of a P type correspondingly; when the silicon substrate 1 is P-type, the Drift region 2, JFET region 3, and Source region 10 are P-type, and the Shield region 4 and Base region 9 are N-type.
The advantages of the present invention are further illustrated by comparing the input-output characteristics of the conventional VDMOS structure with that of the linear planar VDMOS structure of the present invention.
As shown in fig. 2 and 3, the input-output characteristic curves of the conventional VDMOS structure and the linear planar VDMOS structure of the present invention are respectively shown. The abscissa in fig. 2 and 3 is the drain-source voltage Vds of the device, the ordinate is the drain current Id, the curves in fig. 2 and 3 are the drain current variation curves of the conventional VDMOS structure and the linear planar VDMOS structure of the present invention when the gate voltage Vgs is 4V-10V, respectively, it can be seen that compared with the conventional VDMOS structure, when the linear VDMOS structure of the present invention bears a higher Vds voltage, the potential difference actually borne at two ends of the channel is effectively reduced due to the shielding effect of the shied region on the channel in the base region, and meanwhile, the pinch-off of the channel of the VDMOS structure under a high Vds voltage is relieved, so that the device operates in the linear region in a wider Vds voltage region, and the linear output characteristic is improved.
Example two
The present invention also provides another linear planar power VDMOS structure, as shown in fig. 4, where the difference between the linear planar power VDMOS structure provided in the second embodiment and the first embodiment is that the second embodiment is provided with a Shield region 4 extending laterally from the outside to the inside at the bottom of two sides of the JFET region 3, and the Shield region 4 extends downward into the Drift region 2, and other structures and functions are the same as those of the first embodiment.
Example III
The invention also provides a preparation method of the linear planar power VDMOS structure, which specifically comprises the following steps:
5-1, selecting an N+ type silicon substrate 1 as a wafer, and depositing an N-type epitaxial layer on the N+ type silicon substrate 1 to form an N-type Drift region 2; arsenic ion implantation is carried out on the Drift region 2, the implantation energy is 40-60 KeV, and the implantation dosage is 0.8-1.2E13 cm -2 The method comprises the steps of carrying out a first treatment on the surface of the And annealing the arsenic ion implantation line after implantation, and forming an N-type initial JFET region 3-1 on the upper surface of the Drift region 2 after annealing, wherein the annealing temperature is 900-950 ℃ and the annealing time is 70-80 min.
As shown in fig. 5-2, an implantation masking pattern is formed in the middle of the upper surface of the initial JFET region 3-1 by using a photolithography process,and then, carrying out boron ion implantation on the upper surface of the JFET region 3-1, so that P+ type first implantation regions 4-1 are respectively formed at the two sides of the initial JFET region 3-1 corresponding to the positions where implantation masking patterns are not formed. Wherein the implantation energy of boron ions is 40-50 KeV, and the implantation dosage is 2-4E 13 cm -2 。
5-3, removing the implantation masking pattern on the upper surface of the initial JFET region 3-1, and performing arsenic ion implantation on the upper surface of the initial JFET region 3-1 at an implantation energy of 40-50 KeV and an implantation dose of 1-2E 13 cm -2 The method comprises the steps of carrying out a first treatment on the surface of the The P-type impurity on the upper surface of the first injection region 4-1 is changed into N-type impurity by utilizing the impurity injection compensation effect, and the impurity concentration of the initial JFET region 3-1 is further improved, and the N+ type JFET region 3 integrated with the part of the upper surface of the first injection region 4-1 corresponding to the N-type impurity is formed.
As shown in fig. 5-4, thermally growing an oxide layer on the upper surface of the JFET region 3 by adopting a dry oxygen oxidation process to form a gate oxide layer 5 with the thickness of 50-80 nm; meanwhile, in the process of thermally growing the oxide layer, boron ions injected into the first injection region 4-1 generate thermal diffusion, so that the first injection region 4-1 is changed into a P+ type doped region 4-2.
5, as shown in fig. 5-5, sequentially performing polysilicon deposition and dry-oxygen oxidation processes on the upper surface of the gate oxide layer 5, and forming a gate electrode 7 and an injection shielding oxide layer structure 8 through a photoetching process; and thinning the two sides of the gate oxide layer 5 by adopting a dry etching process, wherein the gate oxide layer 5 of the thinned part is used as a gate injection window.
As shown in fig. 5-6, the JFET region 3 is locally implanted with boron ions through a gate implantation window to form a P-type second implantation region 9-1 with an implantation energy of 30-40 KeV and an implantation dose of 1-1.5e13 cm-2.
5-7, performing a line annealing process on the second injection region 9-1, wherein the second injection region 9-1 becomes a P-type Base region 9 after annealing; the annealing temperature is 1100-1150 ℃ and the annealing time is 70-80 min. Meanwhile, as the annealing process proceeds, ions implanted into the Base region 9 and the doped region 4-2 simultaneously generate thermal diffusion, and the doped region 4-2 generates additional lateral diffusion in the horizontal direction relative to the Base region 9 due to the additional thermal process, thereby forming a p+ type Shield region 4.
5-8, carrying out arsenic ion implantation on the upper surface of the Base region 9 through a gate implantation window to form an N+ type third implantation region 10-1 with implantation energy of 50-60 KeV and implantation dosage of 0.5-1.0E16 cm -2 。
5-9, annealing the third injection region 10-1 to form a Source region 10, wherein the annealing temperature is 950-980 ℃ and the annealing time is 120-150 min.
5-10, a dielectric layer 11 with the thickness of 1.0-1.5 mm is deposited on the upper surface of the wafer for forming a Source region 10; forming a metal electrode contact hole on the dielectric layer 11 through a photoetching process; source electrode contact area BF by metal electrode contact hole 2 An implantation process, annealing after implantation to form a source electrode contact region 12; the implantation energy is 60-80 KeV, the implantation dosage is 3E 14-5E 14, the annealing temperature is 900-1000 ℃, and the annealing time is 20-30 min. An AlSiCu metal layer of 4-6 μm is deposited on the upper surface of the wafer on which the active electrode contact region 12 is formed, and the source electrode 13 is formed by a photolithography and etching process.
And 11. As shown in fig. 5-11, a Ti/Ni/Ag metal layer is evaporated on the lower surface of the silicon substrate 1 to form a drain electrode 14, so that the preparation of the linear planar power VDMOS structure based on the patterned injection and impurity compensation process is completed.
In the preparation method of the linear planar power VDMOS structure, the photoetching and etching processes are added in the process, and the common low-energy ion implantation and annealing processes are adopted, so that the ion implantation and annealing process parameters do not need to be finely controlled, the process implementation difficulty is greatly reduced, and the structure reliability is improved. Meanwhile, compared with the prior art that the Shield region is formed by adopting high-energy ion implantation, the Shield region has lower ion implantation energy, so that shallower junction depth of the Shield region can be obtained, the depth of the JFET region is further reduced, and the resistance of the JFET region is obviously reduced; in addition, the method adopts the photoetching pattern to define the transverse structure size of the Shield region, and the extra transverse extension length of the Shield region relative to the Base region can be controlled by adjusting the transverse size of the photoetching pattern, so that the method is suitable for improving the Id-Vd linear characteristic of the large-size power MOS device.
Example IV
The invention also provides a preparation method of the linear planar power VDMOS structure in the second embodiment, which is different from the preparation method in the third embodiment in the steps 1-3, and the specific process in the steps 1-3 in the embodiment is as follows:
6-1, selecting an N+ type silicon substrate 1 as a wafer, and depositing an N-type epitaxial layer on the silicon substrate 1 to form an N-type Drift region 2; performing boron ion implantation on the Drift region 2, and forming a P+ type first implantation region 4-1 on the upper surface of the Drift region 2, wherein the implantation energy of the boron ion is 40-60 KeV, and the implantation dosage is 4.0-5.0E13 cm -2 。
As shown in fig. 6-2, arsenic ion implantation is performed on the upper surface of the first implantation region 4-1, the implanted arsenic ions are annealed, and an N-type initial JFET region 3-1 is formed on the upper surface of the first implantation region 4-1 by utilizing the implantation compensation effect of the abnormal impurities; wherein the implantation energy of arsenic ions is 60-80 KeV, and the implantation dosage is 3-4E 13 cm -2 The method comprises the steps of carrying out a first treatment on the surface of the Annealing temperature is 950-1000 ℃ and annealing time is 70-80 min.
6-3, forming implantation masking patterns on two sides of the upper surface of the initial JFET region 3-1 by adopting a photoetching process, and then carrying out arsenic ion implantation on the upper surface of the initial JFET region 3-1 to change P-type impurities corresponding to the positions without implantation masking patterns on the first implantation region 4-1 into N-type impurities, and simultaneously improving the impurity concentration of the initial JFET region 3-1, wherein the part which is changed into N-type impurities on the first implantation region 4-1 forms an integrated N+ type JFET region (3); wherein the implantation energy of arsenic ions is 60-80 KeV, and the implantation dosage is 2-3E 13 cm -2 。
In the embodiment, the preparation process and method of the step 4 to the step 11 are the same as those of the step 4 to the step 11 in the third embodiment.
In the third and fourth embodiments, the N-type VDMOS structure is taken as an example to provide the preparation method, and in other embodiments of the present invention, the P-type VDMOS structure may also be prepared by the preparation method, that is, the silicon substrate 1 is selected to be P-type, and correspondingly, in the preparation method, the first type ion is P-type, the second type ion is N-type, and the implanted ion when the source electrode contact region 12 is formed is highly doped N-type.
The linear planar power VDMOS structure and the preparation method thereof provided by the invention can be applied to linear amplifiers/voltage regulators, plug-in and pull-out circuits, battery charging/motor speed regulation, intelligent switches and the like, and meet the application requirements of various power management chips on high-performance and high-reliability linear power MOSFET devices.
It is noted that, in the present invention, the Drift region is represented by the Drift region, the Base region is represented by the Base region, the Source region is represented by the Source region, and the Shield region is represented by the Shield region. The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A linear planar power VDMOS structure characterized by:
comprises a silicon substrate (1), a Drift region (2) positioned on the upper surface of the silicon substrate (1), and a drain electrode (14) positioned on the lower surface of the silicon substrate (1);
the upper surface of the Drift region (2) is provided with a JFET region (3);
the two sides of the JFET region (3) are respectively provided with a Shield region (4) extending from the outer side to the inner side transversely;
a Base region (9) extending transversely from the outer side to the inner side is arranged in the Shield region (4), and the upper surface of the Base region (9) exceeds the upper surface of the Shield region (4) and is flush with the upper surface of the JFET region (3); the transverse extension length of the Shield region (4) is larger than that of the Base region (9);
the doping peak concentration of the JFET region (3) is higher than that of the Drift region (2), the doping concentration of the Shield region (4) is higher than that of the Base region (9), and the doping peak concentrations of the JFET region (3) and the Shield region (4) are both located at the bottom of the Base region (9) at corresponding depths;
a Source region (10) extending transversely from the outer side to the inner side is arranged in the Base region (9), and the upper surface of the Source region (10) is flush with the upper surface of the Base region (9); the lateral extension of the Base region (9) is greater than the lateral extension of the Source region (10);
an active electrode contact region (12) is arranged in the Source region (10) at a position close to the edge of the wafer;
The upper surface of the JFET region (3) is provided with a gate oxide layer (5), and the gate oxide layer (5) extends to the upper surfaces of the Base region (9) and the Source region (10) towards two sides;
a gate electrode (7) is arranged on the upper surface of the gate oxide layer (5);
injection shielding oxide layers (8) are arranged on the two sides and the upper surface of the gate electrode (7), and the positions of the injection shielding oxide layers (8) corresponding to the two sides of the gate electrode (7) are in contact with the gate electrode (7);
the upper surfaces of the Source region (10) and the injection shielding oxide layer (8) are provided with a dielectric layer (11);
an active electrode (13) is arranged on the upper surface of the dielectric layer (11), and the active electrode (13) is respectively contacted with the active electrode contact region (12) and the Base region (9).
2. A linear planar power VDMOS structure as claimed in claim 1, characterized in that:
the silicon substrate (1), the Drift region (2), the JFET region (3) and the Source region (10) are of N type; the Shield region (4) and the Base region (9) are of a P type;
or the silicon substrate (1), the Drift region (2), the JFET region (3) and the Source region (10) are of P type; the Shield region (4) and the Base region (9) are of N type.
3. A linear planar power VDMOS structure characterized by:
comprises a silicon substrate (1), a Drift region (2) positioned on the upper surface of the silicon substrate (1), and a drain electrode (14) positioned on the lower surface of the silicon substrate (1);
The upper surface of the Drift region (2) is provided with a JFET region (3);
the two sides of the JFET region (3) are respectively provided with a Shield region (4) extending from the outer side to the inner side transversely, and the Shield region (4) extends downwards into the Drift region (2);
a Base region (9) extending transversely from the outer side to the inner side is arranged in the Shield region (4), and the upper surface of the Base region (9) exceeds the upper surface of the Shield region (4) and is flush with the upper surface of the JFET region (3); the transverse extension length of the Shield region (4) is larger than that of the Base region (9);
the doping peak concentration of the JFET region (3) is higher than that of the Drift region (2), the doping concentration of the Shield region (4) is higher than that of the Base region (9), and the doping peak concentrations of the JFET region (3) and the Shield region (4) are both located at the bottom of the Base region (9) at corresponding depths;
a Source region (10) extending transversely from the outer side to the inner side is arranged in the Base region (9), and the upper surface of the Source region (10) is flush with the upper surface of the Base region (9); the lateral extension of the Base region (9) is greater than the lateral extension of the Source region (10);
an active electrode contact region (12) is arranged in the Source region (10) at a position close to the edge of the wafer;
the upper surface of the JFET region (3) is provided with a gate oxide layer (5), and the gate oxide layer (5) extends to the upper surfaces of the Base region (9) and the Source region (10) towards two sides;
A gate electrode (7) is arranged on the upper surface of the gate oxide layer (5);
injection shielding oxide layers (8) are arranged on the two sides and the upper surface of the gate electrode (7), and the positions of the injection shielding oxide layers (8) corresponding to the two sides of the gate electrode (7) are in contact with the gate electrode (7);
the upper surfaces of the Source region (10) and the injection shielding oxide layer (8) are provided with a dielectric layer (11);
an active electrode (13) is arranged on the upper surface of the dielectric layer (11), and the active electrode (13) is respectively contacted with the active electrode contact region (12) and the Base region (9).
4. A linear planar power VDMOS structure as claimed in claim 3, characterized in that:
the silicon substrate (1), the Drift region (2), the JFET region (3) and the Source region (10) are of N type; the Shield region (4) and the Base region (9) are of a P type;
or the silicon substrate (1), the Drift region (2), the JFET region (3) and the Source region (10) are of P type; the Shield region (4) and the Base region (9) are of N type.
5. A method of fabricating a linear planar power VDMOS structure according to claim 1 or 2, comprising the steps of:
selecting a silicon substrate (1) as a wafer, and depositing an epitaxial layer on the silicon substrate (1) to form a Drift region (2); performing first type ion implantation on the Drift region (2), annealing the first type ion implantation after the implantation is finished, and forming an initial JFET region (3-1) on the upper surface of the Drift region (2) after the annealing;
Forming an injection masking pattern at the middle position of the upper surface of the initial JFET region (3-1) by adopting a photoetching process, then performing second-type ion injection on the upper surface of the JFET region (3-1), and respectively forming a first injection region (4-1) at the positions, which correspond to the positions at which the injection masking pattern is not formed, at the two sides of the initial JFET region (3-1);
removing an implantation masking pattern on the surface of the initial JFET region (3-1), and performing first type ion implantation on the surface of the initial JFET region (3-1) to change the second type impurity on the upper surface of the first implantation region (4-1) into first type impurity, and simultaneously improving the impurity concentration of the initial JFET region (3-1) and forming an integral JFET region (3) with the part of the upper surface of the first implantation region (4-1) corresponding to the first type impurity;
thermally growing an oxide layer on the upper surface of the JFET region (3) to form a gate oxide layer (5); meanwhile, in the process of thermally growing the oxide layer, the second type ions injected by the first injection region (4-1) generate thermal diffusion, so that the first injection region (4-1) is changed into a doped region (4-2);
sequentially performing polysilicon deposition and dry oxygen oxidation processes on the upper surface of the gate oxide layer (5), and forming a gate electrode (7) and an injection shielding oxide layer structure (8) through a photoetching process; thinning two sides of the gate oxide layer (5), wherein the gate oxide layer (5) of the thinned part is used as a gate injection window;
Performing second-type ion implantation on the local part of the JFET region (3) through a gate implantation window to form a second implantation region (9-1);
performing an annealing process on the second injection region (9-1), and changing the second injection region (9-1) into a Base region (9) after annealing; simultaneously, along with the annealing process, ions injected into the doped region (4-2) generate thermal diffusion to form a Shield region (4);
performing first-type ion implantation on the upper surface of the Base region (9) through a gate implantation window to form a third implantation region (10-1);
performing an annealing process on the third injection region (10-1), and forming a Source region (10) after annealing;
depositing a dielectric layer (11) on the upper surface of a wafer for forming a Source region (10); forming a metal electrode contact hole on the dielectric layer (11) through a photoetching process; performing second-type ion implantation through the metal electrode contact hole, and annealing after implantation to form a source electrode contact region (12); depositing an AlSiCu metal layer on the upper surface of a wafer with an active electrode contact area (12), and forming a source electrode (13) through photoetching and etching processes;
and 11, evaporating a Ti/Ni/Ag metal layer on the lower surface of the silicon substrate (1) to form a drain electrode (14), thereby completing the preparation of the linear planar power VDMOS structure based on the graphical injection and impurity compensation process.
6. The method for manufacturing a linear planar power VDMOS structure of claim 5, wherein:
the silicon substrate (1) is of an N type, the first type of ions are of an N type, and the second type of ions are of a P type;
or the silicon substrate (1) is of a P type, the first type of ions are of a P type, and the second type of ions are of an N type.
7. The method for manufacturing a linear planar power VDMOS structure of claim 5 or 6, characterized by:
in the step 1, the silicon substrate (1) is of an N+ type, the epitaxial layer is of an N-type, the Drift region (2) is of an N-type, and the initial JFET region (3-1) is of an N-type; the first type of ion is arsenic ion with implantation energy of 40-60 KeV and implantation dosage of 0.8-1.2E13 cm -2 The method comprises the steps of carrying out a first treatment on the surface of the The annealing temperature of arsenic ion implantation is 900-950 ℃ and the annealing time is 70-80 min;
in the step 2, the second type of ions are boron ions, the implantation energy is 40-50 KeV, and the implantation dosage is 2-4E 13 cm -2 The method comprises the steps of carrying out a first treatment on the surface of the The first injection region (4-1) is of a P+ type;
in step 3), the first type of ions are arsenic ions,the implantation energy is 40-50 KeV, the implantation dosage is 1-2E 13 cm -2 The method comprises the steps of carrying out a first treatment on the surface of the The P-type impurity on the upper surface of the first injection region (4-1) is changed into N-type impurity, and the JFET region (3) is of N+ type;
In the step 4, the thermal growth process of the oxide layer is a dry-oxygen oxidation process; the thickness of the gate oxide layer (5) is 50-80 nm; the doped region (4-2) is of a P+ type;
in the step 5, the two sides of the gate oxide layer (5) are thinned by adopting a dry etching process;
in the step 6, the second type of ions are boron ions, the implantation energy is 30-40 KeV, and the implantation dosage is 1-1.5E13 cm -2 The method comprises the steps of carrying out a first treatment on the surface of the The second injection region (9-1) is of a P type;
in the step 7, the annealing temperature of the second injection region (9-1) is 1100-1150 ℃ and the annealing time is 70-80 min; the Shield region (4) is of a P+ type;
in the step 8, the first type of ions are arsenic ions, the implantation energy is 50-60 KeV, and the implantation dosage is 0.5-1.0E16 cm -2 The method comprises the steps of carrying out a first treatment on the surface of the The third injection region (10-1) is of an N+ type;
in the step 9, the annealing temperature of the third injection region (10-1) is 950-980 ℃ and the annealing time is 120-150 min; the Source region (10) is of an N+ type;
in the step 10, the thickness of the dielectric layer (11) is 1.0-1.5 mm; the second type of ion being BF 2 The injection energy is 60-80 KeV, and the injection dosage is 3E 14-5E 14; BF (BF) 2 The annealing temperature of the injection is 900-1000 ℃ and the annealing time is 20-30 min; the thickness of the AlSiCu metal layer is 4-6 mu m.
8. A method of fabricating a linear planar power VDMOS structure as claimed in claim 3 or 4, comprising the steps of:
selecting a silicon substrate (1) as a wafer, and depositing an epitaxial layer on the silicon substrate (1) to form a Drift region (2); performing second-type ion implantation on the Drift region (2), and forming a first implantation region (4-1) on the upper surface of the Drift region (2);
performing first-type ion implantation on the upper surface of the first implantation region (4-1), annealing the implanted first-type ions, and forming an initial JFET region (3-1) on the upper surface of the first implantation region (4-1);
forming implantation masking patterns on two sides of the upper surface of the initial JFET region (3-1) by adopting a photoetching process, then carrying out first type ion implantation on the upper surface of the initial JFET region (3-1) to enable second type impurities corresponding to the positions where the implantation masking patterns are not formed on the first implantation region (4-1) to be changed into first type impurities, and simultaneously enabling the impurity concentration of the initial JFET region (3-1) to be increased and forming an integral JFET region (3) with the part of the first implantation region (4-1) which is changed into the first type impurities;
thermally growing an oxide layer on the upper surface of the JFET region (3) to form a gate oxide layer (5); meanwhile, in the process of thermally growing the oxide layer, the second type ions injected by the first injection region (4-1) generate thermal diffusion, so that the first injection region (4-1) is changed into a doped region (4-2);
Sequentially performing polysilicon deposition and dry oxygen oxidation processes on the upper surface of the gate oxide layer (5), and forming a gate electrode (7) and an injection shielding oxide layer structure (8) through a photoetching process; thinning two sides of the gate oxide layer (5), wherein the gate oxide layer (5) of the thinned part is used as a gate injection window;
performing second-type ion implantation on the local part of the JFET region (3) through a gate implantation window to form a second implantation region (9-1);
performing an annealing process on the second injection region (9-1), and changing the second injection region (9-1) into a Base region (9) after annealing; simultaneously, along with the annealing process, ions injected into the doped region (4-2) generate thermal diffusion to form a Shield region (4);
performing first-type ion implantation on the upper surface of the Base region (9) through a gate implantation window to form a third implantation region (10-1);
performing an annealing process on the third injection region (10-1), and forming a Source region (10) after annealing;
depositing a dielectric layer (11) on the upper surface of a wafer to form a Source region (10); forming a metal electrode contact hole on the dielectric layer (11) through a photoetching process; performing second-type ion implantation through the metal electrode contact hole, and annealing after implantation to form a source electrode contact region (12); depositing an AlSiCu metal layer on the upper surface of a wafer with an active electrode contact area (12), and forming a source electrode (13) through photoetching and etching processes;
And 11, evaporating a Ti/Ni/Ag metal layer on the lower surface of the silicon substrate (1) to form a drain electrode (14), thereby completing the preparation of the linear planar power VDMOS structure based on the graphical injection and impurity compensation process.
9. The method for preparing a linear planar power VDMOS structure of claim 8, wherein:
the silicon substrate (1) is of an N type, the first type of ions are of an N type, and the second type of ions are of a P type; or the silicon substrate (1) is of a P type, the first type of ions are of a P type, and the second type of ions are of an N type.
10. The method for manufacturing a linear planar power VDMOS structure of claim 8 or 9, characterized by:
in the step 1, the silicon substrate (1) is of an N+ type, the epitaxial layer is of an N-type, the Drift region (2) is of an N-type, and the first injection region (4-1) is of a P+ type; the second type of ion is boron ion with implantation energy of 40-60 KeV and implantation dosage of 4.0-5.0E13 cm -2 ；
In the step 2, the first type of ions are arsenic ions, the implantation energy is 60-80 KeV, and the implantation dosage is 3-4E 13cm -2 Annealing temperature is 950-1000 ℃ and annealing time is 70-80 min; the initial JFET region (3-1) being N-type;
in the step 3, the first type of ions are arsenic ions, the implantation energy is 60-80 KeV, and the implantation dosage is 2-3E 13cm -2 The method comprises the steps of carrying out a first treatment on the surface of the P-type impurities corresponding to the position where the masking pattern is not implanted on the first implantation region (4-1) are changed into N-type impurities, and the JFET region (3) is of an N+ type;
in the step 4, the thermal growth process of the oxide layer is a dry-oxygen oxidation process; the thickness of the gate oxide layer (5) is 50-80 nm; the doped region (4-2) is of a P+ type;
in the step 5, the two sides of the gate oxide layer (5) are thinned by adopting a dry etching process;
in the step 6, the second type of ions are boron ions, and the implantation energy is 30-40KeV, injection dose of 1-1.5E13 cm -2 The method comprises the steps of carrying out a first treatment on the surface of the The second injection region (9-1) is of a P type;
in the step 7, the annealing temperature of the second injection region (9-1) is 1100-1150 ℃ and the annealing time is 70-80 min; the Shield region (4) is of a P+ type;
in the step 8, the first type of ions are arsenic ions, the implantation energy is 50-60 KeV, and the implantation dosage is 0.5-1.0E16 cm -2 The method comprises the steps of carrying out a first treatment on the surface of the The third injection region (10-1) is of an N+ type;
in the step 9, the annealing temperature of the third injection region (10-1) is 950-980 ℃ and the annealing time is 120-150 min; the Source region (10) is of an N+ type;
in the step 10, the thickness of the dielectric layer (11) is 1.0-1.5 mm; the second type of ion being BF 2 The injection energy is 60-80 KeV, and the injection dosage is 3E 14-5E 14; BF (BF) 2 The annealing temperature of the injection is 900-1000 ℃ and the annealing time is 20-30 min; the thickness of the AlSiCu metal layer is 4-6 mu m.
CN202310761606.6A 2023-06-26 2023-06-26 Linear planar power VDMOS structure and preparation method thereof Pending CN116613215A (en)

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