CN110729196A - Method for reducing on-resistance of groove type metal oxide semiconductor - Google Patents
Method for reducing on-resistance of groove type metal oxide semiconductor Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0856—Source regions
- H01L29/0865—Disposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Abstract
The invention discloses a method for reducing the on-resistance of a groove type metal oxide semiconductor, which comprises the following steps of growing a thermal growth oxide layer on an N type epitaxial layer on a silicon substrate, depositing the oxide layer, and etching a groove; growing a grid oxide layer and depositing doped grid polycrystalline silicon; forming a grid electrode of the device, injecting a P-type impurity and forming a P-type body region; carrying out longitudinal source region photoetching and N-type impurity injection; forming a source region of the trench DMOS; carrying out longitudinal P-type heavily doped region photoetching and P-type heavily doped implantation; depositing a medium isolation layer, depositing titanium/titanium nitride, and depositing a front metal layer to form a source electrode of the device; growing a back metal layer again to form a drain electrode of the device and finish the manufacture of the device; the invention realizes the manufacture of smaller unit cells by changing the structure of the device, realizes the reduction of the on-resistance with the same area or the reduction of the chip area with the same on-resistance, and has good market application value.
Description
Technical Field
The invention relates to the field of semiconductor chip design and manufacture, in particular to a method for reducing on-resistance of a groove type metal oxide semiconductor.
Background
double-Diffused Metal Oxide Semiconductor (DMOS) transistors combine the advantages of bipolar transistors and common MOS devices, and DMOS is an ideal power device for both switching and linear applications. DMOS is mainly used for inverters, electronic switches, hi-fi stereo, automotive appliances, electronic ballasts, and the like.
DMOS is divided into planar DMOS and trench DMOS, planar DMOS is mainly developed towards high voltage, and trench DMOS is mainly developed towards medium and low voltage, and with the continuous development and innovation in the field of semiconductor design and semiconductor process in recent years, the trench DMOS has been developed towards lower cost, higher performance, light weight, and small volume, and especially in ultra-thin electronic products, there are very strict requirements for area and on-resistance, and how to continuously reduce area and on-resistance on the premise of ensuring high performance becomes a main subject of each design company and wafer foundry.
As is known, the longer the channel length of a DMOS under the same area, that is, the larger the number of cells, the smaller the on-resistance, and the current trench DMOS is mainly produced in an 8-inch wafer fabrication plant, and the minimum size of the cell that can be made at present is 0.7 μm, so it is almost impossible to continue to reduce the on-resistance by reducing the cell size, and a great resistance is brought to the development of portable electronic products.
As shown in fig. 1, the limit size of the current trench DMOS device in an 8-inch fab is as follows:
1. the trench opening dimension 25 cannot be less than 0.2 microns, otherwise gate polysilicon material 8 fill is affected;
2. the size 24 of the hole 18 cannot be less than 0.2 microns, otherwise the metal 20 filling in the hole is affected;
3. the hole-to-trench spacing 23 cannot be less than 0.15 microns, otherwise the parametric failure rate would be increased;
from the above data, it can be confirmed that the current minimum cell size is 0.7 μm.
The prior art has defects and needs to be improved.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention provides a method for reducing the on-resistance of a trench metal oxide semiconductor.
The technical scheme provided by the invention is a method for reducing the on-resistance of a groove type metal oxide semiconductor, which comprises the following steps:
s1, growing a thermal growth oxide layer on the N-type epitaxial layer on the silicon substrate, depositing the oxide layer, defining a cell area by adopting a trench photoetching layer, wherein the size of a trench opening is 0.2 micron, the distance between trench openings is 0.15 micron, and then etching the oxide layer and the thermal growth oxide layer until the surface of the N-type epitaxial layer is etched;
s2, after the groove photoetching layer is removed, the remained oxidation layer is used as a hard mask to etch the groove;
s3, removing the oxide layer and thermally growing the oxide layer, growing a grid oxide layer, and depositing doped grid polysilicon;
s4, etching back the doped grid polysilicon, annealing the doped grid polysilicon to form a grid of the device, and then injecting P-type impurities;
s5, driving the injected P-type impurities to form a P-type body region;
s6, switching the original transverse layout into a longitudinal layout, carrying out longitudinal source region photoetching, defining a source region N-type impurity injection region and a source region N-type impurity non-injection region by adopting a source region photoetching layer, and carrying out N-type impurity injection on the source region N-type impurity injection region;
s7, removing the source region photoetching layer, and performing source region annealing to form a source region of the trench DMOS;
s8, switching the original transverse layout into a longitudinal layout, carrying out longitudinal P-type heavily doped region photoetching, defining a P-type heavily doped region by adopting a P-type heavily doped photoetching layer, and carrying out P-type heavily doped implantation;
s9, removing the photoetching layer of the P-type heavily doped region, and performing rapid thermal annealing to form the P-type heavily doped region of the trench DMOS;
s10, depositing a medium isolation layer, carrying out annealing reflux treatment, then carrying out photoetching to etch the medium isolation layer and the grid oxide layer, etching the medium isolation layer and the grid oxide layer above the source region, and simultaneously etching the groove to 200 nanometers below the upper plane of the source region;
s11, depositing titanium/titanium nitride, annealing the titanium/titanium nitride by adopting rapid thermal annealing, depositing a front metal layer to form a source electrode of the device, and thinning the back of the wafer; and growing a back metal layer to form a drain electrode of the device, thereby finishing the manufacture of the device.
Preferably, the etching of the trench in step S2 is performed to a depth of 0.8 microns to 6 microns.
The method of claim 1, wherein the doped gate polysilicon deposited in step S3 has a thickness of 400 nm to 1200 nm.
Preferably, the doped gate polysilicon is etched back in step S4 to 300 nm-450 nm below the plane of the N-type epitaxial layer.
Preferably, in step S4, the P-type impurity implantation is performed under conditions of an energy of 80KeV-200KeV and a dose of 5E12-4E13ion/cm2。
Preferably, in step S5, the driving-in conditions for the implanted P-type impurity are 1000-1150 degrees, 60-150 minutes, preferably 1050 degrees, 90 minutes.
Preferably, in step S6, the N-type impurity implantation is performed under conditions that the impurity is As +, the energy is 40KeV-150KeV, and the dose is 2E15-8E15ion/cm 2.
Preferably, in step S8, the P-type heavily doped implant is performed under conditions of B + as an impurity, 20KeV-50KeV as an energy, and 3E14-2E15ion/cm as a dose2。
Preferably, in step S9, the rapid thermal annealing is performed under an N2 atmosphere at 850-1050 degrees for 15-120 seconds.
Preferably, in step S10, the dielectric isolation layer is deposited by depositing 200 nm of tetraethoxysilane and then 700 nm of borophosphosilicate glass.
Compared with the prior art, the manufacturing method has the advantages that a new device structure is developed under the manufacturing resources of the existing 8-inch wafer processing factory, the size of the unit cell is reduced from 0.7 micrometer to 0.35 micrometer, namely the number of the unit cell is doubled, and the on-resistance in the unit area can be reduced by about 0.8-1 time; or the area of the chip can be reduced by about 0.8-1 time under the requirement of the same on-resistance, the invention realizes the manufacture of smaller unit cells by changing the structure of the device, realizes the reduction of the on-resistance of the same area or the chip area of the same on-resistance, and has good market application value.
Drawings
Fig. 1 is a schematic diagram of a cell structure of a prior art trench DMOS device;
FIG. 2 is a schematic structural view of step 1 of the present invention;
FIG. 3 is a schematic structural view of step 2 of the present invention;
FIG. 4 is a schematic structural view of step 3 of the present invention;
FIG. 5 is a schematic view of the structure of step 4 of the present invention;
FIG. 6 is a schematic view of the structure of step 5 of the present invention;
FIG. 7 is a schematic view of the structure of step 6 of the present invention;
FIG. 8 is a schematic view of the structure of step 7 of the present invention;
FIG. 9 is a schematic structural view of step 8 of the present invention;
FIG. 10 is a schematic view of the structure of step 9 of the present invention;
FIG. 11 is a schematic view of the structure of step 10 of the present invention;
FIG. 12 is a schematic view of the step 11 structure of the present invention.
Detailed Description
The technical features mentioned above are combined with each other to form various embodiments which are not listed above, and all of them are regarded as the scope of the present invention described in the specification; also, modifications and variations may be suggested to those skilled in the art in light of the above teachings, and it is intended to cover all such modifications and variations as fall within the true spirit and scope of the invention as defined by the appended claims.
In order to facilitate an understanding of the invention, the invention is described in more detail below with reference to the accompanying drawings and specific examples. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for descriptive purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
The present invention will be described in detail with reference to the accompanying drawings.
A method for reducing the on-resistance of a trench metal oxide semiconductor comprises the following steps:
as shown in fig. 2, S1, growing a thermal growth oxide layer 3 on the N-type epitaxial layer 2 on the silicon substrate 1, depositing an oxide layer 4, defining a cell region by using a trench lithography layer 5, wherein the trench opening size 25 is 0.2 microns, the trench opening spacing 29 is 0.15 microns, and then etching the oxide layer 4 and the thermal growth oxide layer 3 until the surface of the N-type epitaxial layer 2 is etched;
as shown in fig. 3, after removing the trench photoresist layer 5, S2, etching the trench 6 by using the remaining oxide layer 4 as a hard mask;
as shown in fig. 4, S3, removing the oxide layer 4 and thermally growing the oxide layer 3, growing the gate oxide layer 7, and then depositing the doped gate polysilicon 8;
as shown in fig. 5, S4, etching back the doped gate polysilicon 8, then annealing the doped gate polysilicon 8 to form the gate 27 of the device, and then implanting the P-type impurity 9;
as shown in fig. 6, S5, driving in the implanted P-type impurity 9 to form a P-type body region 10;
as shown in fig. 7, S6, switching the original horizontal layout to the vertical layout, performing vertical source region 13 lithography, defining a source region N-type impurity implantation region and a source region N-type impurity non-implantation region by using the source region lithography layer 11, and performing N-type impurity 12 implantation on the source region N-type impurity implantation region;
as shown in fig. 8, S7, removing the source region photoresist layer 11, and annealing the source region 13 to form the source region 13 of the trench DMOS;
as shown in fig. 9, S8, the original horizontal layout is switched to the vertical layout, the vertical P-type heavily doped region is photo-etched, the P-type heavily doped region 16 is defined by the P-type heavily doped photo-etching layer 14, and the P-type heavily doped layer 15 is implanted;
as shown in fig. 10, S9, removing the P-type heavily doped region photoresist layer 14, and performing rapid thermal annealing to form the P-type heavily doped region 16 of the trench DMOS;
as shown in fig. 11, S10, depositing the dielectric isolation layer 17, performing annealing reflow treatment, and then performing photolithography to etch away the dielectric isolation layer and the gate oxide layer, wherein the dielectric isolation layer and the gate oxide layer above the source region 13 are both etched, and the trench is etched to a depth of 200 nm below the upper plane of the source region 13;
as shown in fig. 12, S11, depositing titanium/titanium nitride 19, annealing the deposited titanium/titanium nitride by rapid thermal annealing, depositing a front metal layer 21 to form a source 26 of the device, and thinning the back of the wafer; and growing the back metal layer 22 to form a drain electrode 28 of the device, thereby completing the manufacture of the device.
As shown in fig. 2, the thickness of the thermally grown oxide layer 3 in step S1 is preferably set to 10 nm to 100 nm, preferably 20 nm.
Preferably, the oxide layer 4 is deposited in step S1 by using a low pressure chemical vapor deposition method.
Preferably, the thickness of the deposited oxide layer 4 in step S1 is set to be 100 nm to 800 nm, preferably 300 nm.
As shown in fig. 3, the etching of the trench 6 in step S2 preferably has an etching depth of 0.8 microns to 6 microns, preferably 1.3 microns.
As shown in fig. 4, the thickness of the gate oxide layer 7 in step S3 is preferably 20 nm to 200 nm.
Preferably, the doped gate polysilicon 8 deposited in step S3 has a thickness of 400 nm to 1200 nm, preferably 600 nm.
As shown in fig. 5, the doped gate polysilicon 8 is etched back in step S4 to a distance of 300 nm to 450 nm, preferably 350 nm, below the plane of the N-type epitaxial layer 2.
Preferably, in step S4, the annealing condition for the gate polysilicon 8 is 1000 degrees for 90 minutes.
Preferably, in step S4, the implantation of the P-type impurity 9 is performed under conditions of an energy of 80KeV-200KeV and a dose of 5E12-4E13ion/cm2Preferably B +,120KeV,8E12ion/cm2。
As shown in fig. 6, the driving-in conditions for the implanted P-type impurity 9 in step S5 are 1000-1150 degrees for 60-150 minutes, preferably 1050 degrees for 90 minutes.
As shown in fig. 7, in step S6, the implantation of the N-type impurity 12 is performed under the conditions that the impurity is As +, the energy is 40KeV to 150KeV, and the dose is 2E15 to 8E15ion/cm2, preferably under the conditions that: AS +,70KeV,4E15 ion/cm2。
In step S6, the ratio of the size of the area not implanted by the source region to the size of the area implanted by the source region is 1-3: 5-7, preferably 1: 5.
As shown in fig. 8, in step S7, the annealing condition of the source region is 850 degrees for 60 minutes at N2The method is carried out under the environment.
As shown in FIG. 9, in step S8, the P-type heavy dopant 15 implantation is performed under conditions of B + as an impurity, 20KeV-50KeV as an energy, and 3E14-2E15ion/cm as a dose2The preferred conditions are: b +,30KeV,8E14 ion/cm2。
In step S8, the layout of the P-type heavily doped region 16 is adjusted by photolithography, and the original transverse layout is changed into a longitudinal layout, so that the P-type heavily doped region 16 and the source region 13 are adjusted from the original transverse short circuit to the longitudinal short circuit, and thus the size of the cell can be reduced by 1 time under the process limit, and the purpose of reducing the on-resistance is achieved; meanwhile, the ratio of the size of the source region P-type impurity non-injection region to the size of the source region P-type impurity injection region is 5-7: 1-3, preferably 5: 1, the size of a source region P-type impurity non-injection region is 10 microns and the size of a source region P-type impurity injection region is 2 microns;
the source region N-type impurity injection region is a source region P-type impurity non-injection region, and the source region N-type impurity non-injection region is a source region P-type impurity injection region.
As shown in fig. 10, in step S9, the rapid thermal annealing is performed under 850 to 1050 degrees celsius, 15 seconds to 120 seconds, N2 atmosphere, preferably 1000 degrees 15 seconds.
As shown in fig. 11, in step S10, a dielectric isolation layer is deposited by depositing 200 nm of tetraethoxysilane and then 700 nm of borophosphosilicate glass.
In step S10, the annealing reflow process is performed under conditions of 850 degrees for 30 minutes.
As shown in FIG. 12, in step S11, titanium/titanium nitride (TI/TIN) is deposited to a thickness of 200-100 nm/200-100 nm, preferably 40 nm/60 nm.
In step S11, the rapid thermal annealing is performed at 650-900 deg.C for 15-60 seconds, N2Ambient, preferably 850 degrees 30 seconds.
In step S11, the front metal layer 21 is deposited to a thickness of 4 microns.
In step S11, the back surface of the wafer is thinned, and the remaining thickness is 50 to 200 micrometers, preferably 90 micrometers.
In step S11, the material of the back metal layer 22 is titanium/nickel/silver (TI/NI/AG), and the thickness is 100 nm/200 nm/1000 nm.
The technical features mentioned above are combined with each other to form various embodiments which are not listed above, and all of them are regarded as the scope of the present invention described in the specification; also, modifications and variations may be suggested to those skilled in the art in light of the above teachings, and it is intended to cover all such modifications and variations as fall within the true spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method for reducing the on-resistance of a trench metal oxide semiconductor is characterized by comprising the following steps:
s1, growing a thermal growth oxide layer on the N-type epitaxial layer on the silicon substrate, depositing the oxide layer, defining a cell area by adopting a trench photoetching layer, wherein the size of a trench opening is 0.2 micron, the distance between trench openings is 0.15 micron, and then etching the oxide layer and the thermal growth oxide layer until the surface of the N-type epitaxial layer is etched;
s2, after the groove photoetching layer is removed, the remained oxidation layer is used as a hard mask to etch the groove;
s3, removing the oxide layer and thermally growing the oxide layer, growing a grid oxide layer, and depositing doped grid polysilicon;
s4, etching back the doped grid polysilicon, annealing the doped grid polysilicon to form a grid of the device, and then injecting P-type impurities;
s5, driving the injected P-type impurities to form a P-type body region;
s6, switching the original transverse layout into a longitudinal layout, carrying out longitudinal source region photoetching, defining a source region N-type impurity injection region and a source region N-type impurity non-injection region by adopting a source region photoetching layer, and carrying out N-type impurity injection on the source region N-type impurity injection region;
s7, removing the source region photoetching layer, and performing source region annealing to form a source region of the trench DMOS;
s8, switching the original transverse layout into a longitudinal layout, carrying out longitudinal P-type heavily doped region photoetching, defining a P-type heavily doped region by adopting a P-type heavily doped photoetching layer, and carrying out P-type heavily doped implantation;
s9, removing the photoetching layer of the P-type heavily doped region, and performing rapid thermal annealing to form the P-type heavily doped region of the trench DMOS;
s10, depositing a medium isolation layer, carrying out annealing reflux treatment, then carrying out photoetching to etch the medium isolation layer and the grid oxide layer, etching the medium isolation layer and the grid oxide layer above the source region, and simultaneously etching the groove to 200 nanometers below the upper plane of the source region;
s11, depositing titanium/titanium nitride, annealing the titanium/titanium nitride by adopting rapid thermal annealing, depositing a front metal layer to form a source electrode of the device, and thinning the back of the wafer; and growing a back metal layer to form a drain electrode of the device, thereby finishing the manufacture of the device.
2. The method of claim 1, wherein the trench is etched in step S2 to a depth of 0.8-6 μm.
3. The method of claim 1, wherein the doped gate polysilicon deposited in step S3 has a thickness of 400 nm to 1200 nm.
4. The method of claim 1, wherein the doped gate polysilicon is etched back to 300 nm-450 nm below the plane of the N-type epitaxial layer in step S4.
5. The method of claim 1, wherein in step S4, P-type impurity is addedThe implantation conditions are set to 80KeV-200KeV energy and 5E12-4E13ion/cm dose2。
6. The method as claimed in claim 1, wherein the conditions for driving in the implanted P-type impurity in step S5 are 1000-1150 degrees for 60-150 minutes, preferably 1050 degrees for 90 minutes.
7. The method of claim 1, wherein in step S6, the N-type impurity implantation is performed under the conditions of As + and energy of 40KeV-150KeV, and the dosage of 2E15-8E15ion/cm 2.
8. The method of claim 1, wherein in step S8, the P-type heavy dopant implantation is performed under conditions of B + as an impurity, 20KeV-50KeV as an energy, and 3E14-2E15ion/cm as a dose2。
9. The method of claim 1, wherein the rapid thermal annealing is performed at 850-1050 ℃ for 15-120 seconds in N2 in step S9.
10. The method as claimed in claim 1, wherein in step S10, the dielectric isolation layer is deposited by first depositing 200 nm ethyl orthosilicate and then depositing 700 nm borophosphosilicate glass.
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