CN114937636A - Three-dimensional complementary field effect transistor and preparation method thereof - Google Patents
Three-dimensional complementary field effect transistor and preparation method thereof Download PDFInfo
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- CN114937636A CN114937636A CN202210346826.8A CN202210346826A CN114937636A CN 114937636 A CN114937636 A CN 114937636A CN 202210346826 A CN202210346826 A CN 202210346826A CN 114937636 A CN114937636 A CN 114937636A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
Abstract
The invention belongs to the technical field of semiconductor devices, and particularly relates to a three-dimensional complementary field effect transistor and a preparation method thereof. The invention carries out three-dimensional stacking on two field effect transistors with different polarities, controls the conduction states of the two transistors through the same common grid electrode simultaneously, and connects drain electrode ends of the two transistors through interconnection metal to construct a three-dimensional complementary field effect transistor; the preparation method comprises the following steps: forming active area silicon on the SOI top layer silicon; forming source-drain contact metal on the active region silicon; depositing a lower dielectric layer; forming a common gate; depositing an upper dielectric layer; forming a two-dimensional semiconductor material on the upper dielectric layer; forming source-drain contact metal on the two-dimensional semiconductor material; and photoetching, etching and metal deposition are carried out on the interconnection through hole to form interconnection metal. The three-dimensional complementary field effect transistor provided by the invention can improve the unit integration density of an integrated circuit, is easy to realize in process, and has wide application prospect in logic circuits and photoelectric integrated systems.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a three-dimensional complementary field effect transistor and a preparation method thereof.
Background
Since the invention of the integrated circuit, the characteristic size of a device taking semiconductor silicon as a carrier is gradually reduced according to the Moore's law so as to reach the maximum number of devices on a unit area, and the performance of the device is improved while the production cost of a chip is reduced. However, as the feature size of the device is reduced to sub-10 nm or less, the problems of short channel effect, quantum effect, hot carrier injection effect, etc. become more and more serious. The solution to this problem can be achieved with new materials and innovations in new devices. In the aspect of materials, the two-dimensional semiconductor material has the thickness of an atomic layer, so that the short channel effect can be effectively inhibited; in the aspect of devices, the gate control capability of the devices can be further improved and the integration density of the devices can be improved by adopting a gate-all-around structure and a three-dimensional multi-bridge channel field effect transistor.
The existing device structure mostly adopts a planar structure, which is not beneficial to further improving the integration density of the device. The existing three-dimensional vertical device based on the all-silicon substrate is difficult to realize in process. Therefore, the novel three-dimensional vertical device is realized by combining a new material and a new device and a process compatible method, and is particularly important in nodes of 1 nanometer and below.
Disclosure of Invention
The invention aims to provide a three-dimensional complementary field effect transistor and a preparation method thereof, and aims to solve the problems that the existing transistor in the background art is low in integration level and difficult to realize in process.
The preparation method of the three-dimensional complementary field effect transistor provided by the invention is characterized in that two field effect transistors with different polarities are three-dimensionally stacked, the conducting states of an upper transistor and a lower transistor are simultaneously controlled by the same common grid, and the drain electrode ends of the upper transistor and the lower transistor are connected through interconnection metal to construct the three-dimensional complementary field effect transistor; the preparation method comprises the following specific steps:
(1) providing an SOI substrate;
(2) forming active area silicon on the SOI top layer silicon;
(3) forming a first source-drain contact metal on the active region silicon;
(4) depositing a lower dielectric layer;
(5) forming a common gate;
(7) depositing an upper dielectric layer;
(7) forming a two-dimensional semiconductor material on the upper dielectric layer;
(8) forming a second source-drain contact metal on the two-dimensional semiconductor material;
(9) and photoetching, etching and metal deposition are carried out on the interconnection through hole to form interconnection metal.
The SOI top layer silicon, the first source-drain contact metal, the lower dielectric layer and the lower grid form a lower field effect transistor, and the two-dimensional semiconductor material, the second source-drain contact metal, the upper dielectric layer and the upper grid form an upper field effect transistor; if the lower field effect transistor is a p-type field effect transistor, the two-dimensional semiconductor material is an n-type semiconductor; if the lower field effect transistor is an n-type field effect transistor, the two-dimensional semiconductor material is a p-type semiconductor.
Preferably, the source electrode, the drain electrode and the channel of the upper field effect transistor are positioned right above the vertical direction of the source electrode, the drain electrode and the channel of the corresponding lower field effect transistor.
Preferably, the drain electrode of the upper field effect transistor is shorter than the drain electrode of the lower field effect transistor by 1 μm to 10 μm.
Preferably, the interconnection metal connects the drain electrode terminal of the upper field effect transistor and the drain electrode terminal of the lower field effect transistor through a metal.
Preferably, the top silicon of the SOI substrate is any one of lightly doped p-type or n-type silicon with a thickness of 1nm to 100 nm.
Preferably, the step of forming the active region silicon is as follows:
selectively removing active region silicon and top layer silicon outside a channel silicon region by using the patterned photoresist as a masking layer and adopting a dry etching process or a wet etching process;
forming heavily doped p-type or n-type silicon in the active region silicon by using the patterned photoresist as a masking layer and adopting an ion implantation method;
and (3) rapidly annealing at 900-1100 ℃ to repair the ion implantation damage.
Preferably, the first source-drain contact metal is any one of metal or metal silicide.
Preferably, the common gate is composed of a stacked structure of a lower gate and an upper gate, and both the lower gate and the upper gate are made of metal materials.
Preferably, the lower dielectric layer and the upper dielectric layer are both made of dielectric materials with high dielectric constants and are both 1nm to 50nm in thickness.
Preferably, the two-dimensional semiconductor material is 1 to 10 layers of a two-dimensional transition metal chalcogenide material.
Preferably, the two-dimensional semiconductor material is formed using any one of a thin film vacuum transfer method or a direct growth method.
Preferably, the second source-drain contact metal and the interconnection metal are both made of metal materials.
Preferably, after the first source-drain contact metal and the second source-drain contact metal are formed, high-temperature thermal annealing treatment is adopted to improve the contact performance of the device.
Preferably, the etching of the interconnection via adopts a dry etching process.
In summary, the three-dimensional complementary field effect transistor prepared by the invention is constructed by three-dimensionally stacking two field effect transistors with different polarities, simultaneously controlling the conduction states of the upper and lower transistors through the same common gate, and connecting the drain electrode terminals of the upper and lower transistors through the interconnection metal. The three-dimensional complementary field effect transistor can improve the unit integration density of an integrated circuit and is easy to realize in process. In addition, the three-dimensional complementary field effect transistor can also be directly used as a logic inverter, and the threshold voltages of the upper transistor and the lower transistor can be respectively regulated and controlled by respectively changing the work functions of the metal of the upper grid and the metal of the lower grid. The three-dimensional complementary field effect transistor provided by the invention has wide application prospect in logic circuits and photoelectric integrated systems.
Drawings
Fig. 1 is a flow chart of a method for manufacturing a three-dimensional complementary field effect transistor according to the present invention.
Fig. 2 to 12 are structural diagrams corresponding to each step of the method for manufacturing a three-dimensional complementary field effect transistor according to the present invention, in which fig. 11 and 12 are a cross-sectional view and a three-dimensional schematic view of the three-dimensional complementary field effect transistor according to the present invention, respectively.
Reference numbers in the figures: the structure comprises a silicon substrate 1, silicon dioxide 2, top layer silicon 3, active region silicon 31, channel silicon 32, a first source-drain contact metal 4, a lower dielectric layer 5, a common gate 6, a lower gate 61, an upper gate 62, an upper dielectric layer 7, a two-dimensional semiconductor material 8, a second source-drain contact metal 9, an interconnection through hole 10 and an interconnection metal 11.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar materials or methods having the same or similar functions throughout. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
The preparation method of the three-dimensional complementary field effect transistor, as shown in figure 1, comprises the following steps:
s1, providing an SOI substrate;
specifically, as shown in fig. 2, the SOI substrate includes a silicon substrate 1, a silicon dioxide 2BOX layer, and a top silicon 3.
Preferably, the top silicon 3 of the SOI substrate is any one of lightly doped p-type or n-type silicon with a thickness of 1nm to 100 nm.
S2, as shown in fig. 2, forming an active region silicon 31 on the SOI top layer silicon 3;
specifically, the steps of forming the active region silicon 31 are as follows:
selectively removing the top silicon 3 outside the active area silicon 31 and the channel silicon 32 area by using the patterned photoresist as a masking layer and adopting a dry etching process or a wet etching process;
forming heavily doped p-type or n-type silicon in the active region silicon 31 by using the patterned photoresist as a masking layer and adopting an ion implantation method;
and (3) rapidly annealing at 900-1100 ℃ to repair the ion implantation damage.
Illustratively, the top silicon 3 of the SOI substrate is lightly doped p-type silicon, and reactive ion etching is used to selectively etch away the top silicon 3 except for the active area silicon 31 and the channel silicon 32 under the patterned photoresist as a masking layer. Under the selective masking action of the photoresist, p-type ion implantation is carried out on the active region silicon 31, wherein the implanted ions are boron difluoride, the energy is 10 KeV, and the implantation dosage is 10 15 cm -2 . And rapidly carrying out thermal annealing to repair the ion implantation damage at 950 ℃ in a nitrogen atmosphere.
S3, as shown in fig. 3, forming a first source-drain contact metal 4 on the active region silicon 31;
specifically, the first source-drain contact metal 4 is any one of a metal or a metal silicide. After the first source-drain contact metal 4 is formed, the contact performance of the device is improved by adopting high-temperature thermal annealing treatment.
For example, gold is used as the first source-drain contact metal 4, and after the first source-drain contact metal 4 region is patterned by using photoresist, 60 nm of gold is evaporated by using an electron beam evaporation apparatus to form the first source-drain contact metal 4. And then putting the silicon wafer into a rapid thermal annealing furnace to anneal at 320 ℃ for 10 minutes in a nitrogen atmosphere so as to improve the contact performance of the device.
S4, as shown in fig. 4, depositing a lower dielectric layer 5;
specifically, the lower dielectric layer 5 is a dielectric material with a high dielectric constant and has a thickness of 1nm to 50 nm.
Illustratively, the lower dielectric layer 5 is made of hafnium oxide by atomic layer deposition and has a thickness of 25 nm.
S5, as shown in fig. 5 and 6, forming a common gate 6;
specifically, the common gate 6 is composed of a stacked structure of a lower gate 61 and an upper gate 62, and both the lower gate 61 and the upper gate 62 are made of a metal material.
For example, after patterning the common gate 6 region by using a photoresist, 20nm titanium and 30 nm gold are sequentially evaporated by using an electron beam evaporation apparatus to form a titanium and gold stacked structure. Wherein, the titanium which is firstly evaporated and positioned below is a lower grid 61, and the gold which is then evaporated and positioned above is an upper grid 62; of course, the lower gate 61 and the upper gate 62 may be made of the same metal material.
It should be noted that, up to now, a bottom field effect transistor composed of the SOI top layer silicon 3, the first source-drain contact metal 4, the bottom dielectric layer 5, and the bottom gate 61 has been formed.
S6, as shown in FIG. 7, depositing an upper dielectric layer 7;
specifically, the upper dielectric layer 7 is a dielectric material with a high dielectric constant and has a thickness of 1nm to 50 nm.
Illustratively, the upper dielectric layer 7 is made of aluminum dioxide by atomic layer deposition and has a thickness of 20 nm.
S7, as shown in fig. 8, forming a two-dimensional semiconductor material 8 on the upper dielectric layer 7;
specifically, the two-dimensional semiconductor material 8 is a two-dimensional transition metal chalcogenide material in 1 to 10 layers. The two-dimensional semiconductor material 8 is formed by any of a thin film vacuum transfer method or a direct growth method.
Illustratively, the two-dimensional semiconductor material 8 is 5 layers of molybdenum disulfide. And transferring the two-dimensional semiconductor material 8 from the other substrate to the upper dielectric layer 7 by adopting a vacuum transfer method.
S8, as shown in fig. 9, forming a second source-drain contact metal 9 on the two-dimensional semiconductor material 8;
specifically, the second source-drain contact metal 9 is made of a metal material. After the second source-drain contact metal 9 is formed, the contact performance of the device is improved by adopting high-temperature thermal annealing treatment.
For example, the second source-drain contact metal 9 is made of gold, and after the second source-drain contact metal 9 region is patterned by using photoresist, the second source-drain contact metal 9 is formed by evaporating 50nm of gold by using an electron beam evaporation apparatus. And defining a two-dimensional semiconductor material channel region by adopting photoetching and etching processes, and then putting the two-dimensional semiconductor material channel region into an annealing furnace to be annealed for 8 minutes at 250 ℃ in a nitrogen atmosphere so as to improve the contact performance of the device.
It should be noted that, up to now, an upper field effect transistor composed of the two-dimensional semiconductor material 8, the second source-drain contact metal 9, the upper dielectric layer 7, and the upper gate 62 has been formed.
Specifically, if the lower field effect transistor is a p-type field effect transistor, the two-dimensional semiconductor material 8 is an n-type semiconductor; if the lower field effect transistor is an n-type field effect transistor, the two-dimensional semiconductor material is a p-type semiconductor.
Illustratively, if the SOI top layer silicon 3 is lightly doped p-type silicon, the active region silicon 31 is boron difluoride p-type ion implantation, and the formed lower field effect transistor is a p-type field effect transistor, the two-dimensional semiconductor material 8 is an n-type semiconductor, preferably, molybdenum disulfide is used as the two-dimensional semiconductor material 8, and the formed upper field effect transistor is an n-type field effect transistor.
Specifically, the source electrode, the drain electrode, and the channel of the upper field effect transistor are located directly above the vertical direction of the source electrode, the drain electrode, and the channel of the corresponding lower field effect transistor. The drain electrode of the upper field effect transistor is shorter than the drain electrode of the lower field effect transistor by 1 μm to 10 μm.
Illustratively, as shown in fig. 9, the first source-drain contact metals 4 on the left and right sides are respectively a drain electrode and a source electrode of the lower field effect transistor, the second source-drain contact metals 9 on the left and right sides are respectively a drain electrode and a source electrode of the upper field effect transistor, and the source electrode, the drain electrode and the channel of the upper field effect transistor are located right above the vertical direction of the source electrode, the drain electrode and the channel of the corresponding lower field effect transistor. Preferably, the drain electrode of the upper field effect transistor is shorter than the drain electrode of the lower field effect transistor by 5 μm.
S9, as shown in fig. 10 to 12, photolithography, etching and metal deposition of the interconnection via 10 are performed to form the interconnection metal 11.
Specifically, the etching of the interconnection through hole 10 adopts a dry etching process; the interconnection metal 11 is made of metal; the interconnection metal 11 connects the drain terminal of the upper field effect transistor and the drain terminal of the lower field effect transistor through a metal.
Illustratively, as shown in fig. 10 to 12, after patterning the region of the interconnection via 10 by using photoresist, the two-dimensional semiconductor material 8, the upper dielectric layer 7 and the lower dielectric layer 5 between the drain electrodes of the upper and lower field effect transistors are etched by using an inductively coupled plasma etching apparatus. Then, 100nm of gold was evaporated with an electron beam evaporation apparatus to form the interconnection metal 11.
In summary, according to the three-dimensional complementary field effect transistor and the manufacturing method thereof provided by the present invention, two field effect transistors with different polarities are three-dimensionally stacked, the conduction states of the upper and lower transistors are simultaneously controlled by the same common gate 6, and the drain electrodes of the upper and lower transistors are connected through the interconnection metal 11, so as to construct the three-dimensional complementary field effect transistor. The three-dimensional complementary field effect transistor can improve the unit integration density of an integrated circuit and is easy to realize in process. In addition, the three-dimensional complementary field effect transistor can also be directly used as a logic inverter, the lower field effect transistor is a p-type field effect transistor, the upper field effect transistor is an n-type field effect transistor for example, the common gate 6 is used as a voltage input end, the drain electrode ends of the upper field effect transistor and the lower field effect transistor which are communicated with each other through the interconnection metal 11 are voltage output ends, the source electrode end of the lower field effect transistor is a power supply voltage end, and the source electrode end of the upper field effect transistor is grounded. By changing the work functions of the metal of the upper gate 62 and the metal of the lower gate 61, the threshold voltages of the upper transistor and the lower transistor can be adjusted and controlled respectively. The three-dimensional complementary field effect transistor provided by the invention has wide application prospect in logic circuits and photoelectric integrated systems.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A method for preparing three-dimensional complementary field effect transistor is characterized in that two field effect transistors with different polarities are three-dimensionally stacked, the conduction states of an upper transistor and a lower transistor are simultaneously controlled by the same common grid, and the drain electrode ends of the upper transistor and the lower transistor are connected through interconnection metal to construct the three-dimensional complementary field effect transistor; the method comprises the following specific steps:
(1) providing an SOI substrate;
(2) forming active area silicon on the SOI top layer silicon;
(3) forming a first source-drain contact metal on the active region silicon;
(4) depositing a lower dielectric layer;
(5) forming a common gate;
(6) depositing an upper dielectric layer;
(7) forming a two-dimensional semiconductor material on the upper dielectric layer;
(8) forming a second source-drain contact metal on the two-dimensional semiconductor material;
(9) photoetching, etching and metal deposition are carried out on the interconnection through hole to form interconnection metal;
the SOI top layer silicon, the first source-drain contact metal, the lower dielectric layer and the lower grid form a lower field effect transistor, and the two-dimensional semiconductor material, the second source-drain contact metal, the upper dielectric layer and the upper grid form an upper field effect transistor; if the lower field effect transistor is a p-type field effect transistor, the two-dimensional semiconductor material is an n-type semiconductor; if the lower field effect transistor is an n-type field effect transistor, the two-dimensional semiconductor material is a p-type semiconductor.
2. The method according to claim 1, wherein the source electrode, the drain electrode, and the channel of the upper field effect transistor are located directly above a vertical direction of the source electrode, the drain electrode, and the channel of the corresponding lower field effect transistor.
3. The manufacturing method according to claim 2, wherein the drain electrode of the upper field effect transistor is shorter than the drain electrode of the lower field effect transistor by 1 μm to 10 μm.
4. The method of claim 3, wherein the interconnection metal connects the drain terminal of the upper field effect transistor and the drain terminal of the lower field effect transistor via a metal.
5. The production method according to any one of claims 1 to 4, wherein the top silicon of the SOI substrate is any one of lightly doped p-type or n-type silicon, and has a thickness of 1nm to 100 nm.
6. The method according to any one of claims 1 to 4, wherein the step of forming the active region silicon is as follows:
selectively removing active region silicon and top layer silicon outside a channel silicon region by using the patterned photoresist as a masking layer and adopting a dry etching process or a wet etching process;
forming heavily doped p-type or n-type silicon in the active region silicon by using the patterned photoresist as a masking layer and adopting an ion implantation method;
and (3) rapidly annealing at 900-1100 ℃ to repair the ion implantation damage.
7. The production method according to any one of claims 1 to 4, characterized in that:
the first source drain contact metal is any one of metal or metal silicide;
the common grid is composed of a laminated structure of a lower grid and an upper grid, and the lower grid and the upper grid are both made of metal materials;
the lower dielectric layer and the upper dielectric layer are both made of dielectric materials with high dielectric constants and are both 1nm to 50nm in thickness.
8. The production method according to any one of claims 1 to 4, characterized in that:
the two-dimensional semiconductor material is a two-dimensional transition metal chalcogenide material with 1-10 layers;
the two-dimensional semiconductor material is formed by adopting any one of a thin film vacuum transfer method or a direct growth method.
9. The production method according to any one of claims 1 to 4, characterized in that:
the second source-drain contact metal and the interconnection metal are both made of metal materials;
after the first source drain contact metal and the second source drain contact metal are formed, the contact performance of the device is improved by adopting high-temperature thermal annealing treatment;
and the etching of the interconnection through hole adopts a dry etching process.
10. A three-dimensional complementary field effect transistor obtained by the manufacturing method according to one of claims 1 to 9.
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| CN117438376A (en) * | 2023-12-20 | 2024-01-23 | 华中科技大学 | Complementary field effect transistor based on two-dimensional material and preparation method thereof |
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| CN117438376A (en) * | 2023-12-20 | 2024-01-23 | 华中科技大学 | Complementary field effect transistor based on two-dimensional material and preparation method thereof |
| CN117438376B (en) * | 2023-12-20 | 2024-03-05 | 华中科技大学 | Complementary field effect transistor based on two-dimensional material and preparation method thereof |
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