KR20040002411A - Trench-gate semiconductor devices and their manufacture - Google Patents

Abstract

Compact trench-gate semiconductor devices, for example cellular power metal oxide semiconductor field effect transistors with ultra fine pitch Yc, self align using sidewall spacers 52 in different ways. Manufactured by technology. The trench-gate 11 is etched through the narrow window 52b defined by the spacer 52 on the sidewall of the larger window 51a of the mask 51 on the body surface 10a. Housed within. The spacer 52 allows the source region 13 adjacent to the trench-gate 11 and the insulating overlayer 18 above the trench-gate 11 to self-align to the narrow trench 20. The overlay layer 18 defining the contact window 18a for the source electrode 33 is simply provided but is a method reproducible by deposition and etch-back after removing the spacer 52. This overlap y4, y4 'by the body surface 10a is well defined, reducing the risk of short circuit between the source electrode 33 and the trench-gate 11. In addition, corrosion of the source region 13 is promoted, and the channel receiving region 15 can be provided using a high energy implant 61 after the insulating overlay layer 18 is provided.

Description

TRENCH-GATE SEMICONDUCTOR DEVICES AND THEIR MANUFACTURE}

Trench-gate semiconductor devices are known which have trench-gates in trenches extending from the source region to the drain region of the first conductive region through the channel receiving region. U. S. Patent No. 6,087, 224 discloses a preferred method of manufacturing such trench-gate semiconductor devices, wherein ⓐ narrow windows are defined by providing sidewall extensions to the sidewalls of wider windows in the first mask on the surface of the semiconductor body, The trench is etched in the body of the narrow window, the gate is provided in the trench, the source region is provided to self-align with the trench-gate by the sidewall extension, and the insulating overlayer is provided on the trench-gate. do.

This method can use a self-aligned masking technique in a flexible device method with good reproducibility. In particular, by using sidewall extensions at different stages, narrow trench-gates can be formed, and the contact window for the source region and the source electrode can be determined in a self-aligning manner for this narrow trench. The entire disclosure of US Pat. No. 6,087,224 is incorporated herein by reference.

U. S. Patent No. 6,087, 224 discloses various forms of this method. Thus, for example, the source region and / or the channel receiving region may be provided before or after the trench-gate forming step, and deep or shallow more heavily doped regions may be provided in the channel receiving region (in a self-aligned manner). Doped semiconductor or metal or silicide materials may be used for the gate, and an oxidized or deposited insulating overlay may be provided over the trench-gates (in a self-aligned manner). In the detailed embodiments described above, an insulating overlay layer is provided in the presence of the sidewall extensions and is inhibited by these sidewall extensions. In addition, when the sidewall extensions are removed to form a doping window for forming the source region, this doping is suppressed by the simultaneous presence of both the pre-supplied overlay layer and the first mask portion above the trench-gate.

Summary of the Invention

It is an object of the present invention to provide an improvement of this method, wherein the present invention comprises a series of novel processing steps, which processing steps are simple and improve the provision of an insulation overlay, and in this regard other desirable device features Can provide.

According to the present invention, there is provided a method of manufacturing a trench-gate semiconductor device, for example an insulated-gate field-effect device, wherein a narrow window is formed in a first mask on the surface of a semiconductor body. Defined by providing sidewall extensions to the wider sidewalls, the trenches are etched in the body of the narrow window, the gates are provided in the trenches, and the source region is provided adjacent to the sidewalls of the trenches (preferably, Self-aligned with the trench-gate by extension), ⓓ insulation overlayer is provided on the trench-gate by using the following series of steps. These series of steps include (1) removing sidewall extensions to remove at least a portion of the first mask by a wider window at the surface of the body, and (2) insulating material sufficient to fill a wider window and the wider window. Depositing to a thickness sufficient to extend over the window and over the first mask portion, and (3) etching back the insulating material to remove the insulating overlay in the wider window in the first mask portion; Removing the first mask portion prior to providing a source electrode in contact with the source region and the adjacent surface region of the body and extending over the insulating overlay layer over the trench-gate.

The inventors of the present invention have shown that the edge quality of the wider window in the first mask portion (after etching the trench to provide the trench-gate) is superior to the edge quality of the sidewall extension, and reworking it (by removing the sidewall extension). It has been found that re-exposure can be provided in a reproducible manner by a simple deposition and etch back process that fills these wider windows. Thus, the ais of the sidewall extension becomes generally tapered and irregular in the etching back, while the first mask portion may have a well defined vertical edge. The profile of this well defined vertical edge can be reproducibly modified to the edge of the contact window formed in the insulating overlay layer by removal of the first mask portion in accordance with the present invention. The resulting edge of the insulation overlay can then be used in a variety of ways as detailed above. In addition, the formation of the insulating overlay layer is not inhibited by the presence of the sidewall extensions, since these sidewall extensions have been removed.

Since the insulating overlay layer is formed by filling the wider window of the first mask portion, it extends from the trench-gate by a well defined transverse distance onto the adjacent body surface. Thus, there is a well defined reproducible space between the edge of the contact window formed in the insulating overlay layer by the removal of the first mask portion and the sidewall of the trench. This well defined reproducible space provides good protection against shorting of the source electrode to the trench-gate at the edge of the contact window. In addition, the resulting insulating overlay can easily be formed over the trench-gate slightly recessed such that the overlay extends inside the top of the gate trench. In this way, reliable insulation can be provided over the edges of the gate trenches to avoid short circuits.

Furthermore, the process sequence according to the present invention provides an opportunity for doping the source region at the stage, where this doping process is not inhibited by the simultaneous presence of both the pre-supplied overlay layer and the first mask portion above the trench-gate.

Thus, the source region is preferably provided by using the following series of steps before depositing the insulating material for the insulating overlay layer. This series of steps eliminates at least a portion of the first mask by a wider window at the surface of the body and removes the sidewall extension to form a doped window in the wider window between the first mask portion and the trench-gate. And introducing impurities of the first conductivity type into the main body through a wider window (including the doped window) to form a source region adjacent to the trench-gate.

Another modification process may provide a source region (or at least its doping) prior to depositing the insulating material for the insulating overlay. Thus, the source region may be implanted into a wider window in the first mask portion prior to providing the sidewall extension, or doping may be implanted as a layer on the body surface prior to providing the first mask. In both cases, however, the trench is etched through the source region doping, which is less desirable (as detailed later on).

Depending on how the other features of the device are formed, the overall width of the insulating overlay layer defined by the filling of the wider window may be suppressed in the device being manufactured. However, it may be modified in a later process. Thus, for example, before removing the first mask portion at stage ⓓ and before providing the source electrode, the insulating material of the insulating overlayer may be etched back isotropically at a distance sufficient to increase the area of the source region not covered by the insulating overlayer. Can be.

The method according to the invention is particularly preferred for producing compact cellular devices such as power MOSFETs. Thus, the first mask and its associated window may have a layout shape defining device cells having a cell pitch of about 1 μm or less.

Preferably, the channel receiving region is provided after the trench-gate, so that a high temperature process that can be used to form the trench-gate structure (such as, for example, thermal oxidation to form a high quality gate dielectric) results. It does not affect the doping profile of the channel receiving region provided by. Sidewall extensions may be used in a variety of ways to self-align the source region with the trench-gate. Preferably, the source doping profile is provided after forming the trench-gate structure so as not to be affected by the trench-gate structure. A simple and convenient way to form the source region is to introduce a doping concentration of the first conductivity type into the body via a window formed by removing the sidewall extension at stage ⓓ.

Thus, in a convenient and preferred method according to the present invention, the trench is etched through the silicon body portion having a doping concentration of the first conductivity type extending from the surface into the lower layer region at stage ⓑ to provide a portion of the drain region. In the case of an insulated gate device, the gate dielectric can be formed by depositing an insulating layer on the walls of the trench. However, the gate dielectric layer may be formed by thermal oxidation of the silicon body portion at the walls of the trench. Thus, these initial steps for forming the trench-gate structure do not interfere with the doping profiles of the source region and the channel receiving region that are subsequently provided. In addition, etching of the trenches and thermal oxidation at the walls thereof to form a high quality gate dielectric can be performed in a uniform body portion and is not affected by the source and channel region doping concentrations (provided later).

The doping profile of the channel receiving region may be provided after providing the insulating overlay in step ⓓ. The transverse width of the overlayer on the body surface adjacent to the trench gate is sufficiently small (as determined by the sidewall extension) so that the impurity supply for the channel receiving region can extend laterally down the trench. In some embodiments, thermal diffusion may be used for impurity supply. However, high energy injection by simple active annealing may be most desirable in accurate control. Such implantation can be carried out with sufficient high energy and sufficiently high doses, where impurity ions implanted in the window in the overlayer are laterally dispersed below the overlayer to reach the sidewalls of the trench. The ion energy is so large that impurity ions evenly penetrate the overlayer and are implanted in the lower portion of the body adjacent to the trench.

These and other features according to the invention are illustrated in the embodiments of the invention described above by way of example with reference to the accompanying drawings.

The present invention has a trench-gate semiconductor device, such as power metal oxide semiconductor field effect transistors (insulated-gate field-effect transistors), and a compact shape. It relates to a method of manufacturing thereof using self-aligned techniques for manufacturing the device.

1 is a cross-sectional view of an effective central portion of one embodiment of a trench-gate semiconductor device fabricated in accordance with the present invention;

2 to 12 are cross-sectional views of the portion of FIG. 1 in a continuous stage in the manufacture according to an embodiment of the method according to the invention,

13 is an enlarged cross-sectional view of a particular embodiment of an insulated gate trench structure of a trench-gate semiconductor device fabricated in accordance with the present invention;

14 is a cross sectional view of an effective center portion of a trench-gate semiconductor device in a trench-etching stage in a modified fabrication method according to the invention, although corresponding to the figures of FIGS.

15 and 16 are cross-sectional views of corresponding effective center portions of trench-gate semiconductor devices at stages 4 and 9 in a modified manufacturing method according to the present invention;

17 and 18 are partial perspective cross-sectional views similar to those of FIG. 10 but showing variations in the provision of the source region;

19-21 are cross-sectional views of an effective central portion of another embodiment of a trench-gate semiconductor device in successive stages in the manufacture by another embodiment of the method according to the invention.

It can be seen that FIGS. 1 through 21 are schematic, relative dimensions and proportions of various parts of these figures, shown in exaggerated or reduced size, for clarity and convenience of the figures. Like reference numerals have been used to indicate corresponding or analogous features in modified and different embodiments.

FIG. 1 shows an exemplary embodiment of a cellular power MOSFET device with insulated trench-gates 11. In the transistor cell region of the present apparatus, the channel receiving region 15 of the second conductive form (i.e., p-type in this embodiment) is the source region 13 of the first conductive form (n-type in this embodiment). ) And drain regions 14 are respectively divided. The drain region 14 is common to all cells. Gate 11 resides in trench 20 extending through regions 13 and 15 into the lower portion of drain region 14. The gate 11 is capacitively connected to the channel receiving region 15 by an intermediate dielectric layer 17 at the wall of the trench 20. Application of the voltage signal to the gate 11 at the stage of the device comprises a conduction channel 12 in the region 15 and a current flow in the conduction channel 12 between the source region 13 and the drain region 14. It works in a known way to control the.

The source region 13 is located adjacent to the upper major surface 10a of the device body 10, where the regions 13, 15 are contacted by the source electrode 33. The trench-gate 11 is insulated from the electrode 33 overlying by the intermediate insulation overlayer 18. 1 illustrates a vertical power device structure. Region 14 is a drain-drift region, which may be formed by a highly resistive epitaxial layer on a higher doped substrate 14a of the same conductivity type. The substrate 14a is in contact with the bottom major surface 10b of the apparatus body 10 by the drain electrode 34.

In general, the device body 10 is monocrystalline silicon, and the gate 11 is generally conductively doped polycrystalline silicon. Generally, the middle gate dielectric layer 17 is thermally grown silicon dioxide or deposited silicon dioxide.

The device of FIG. 1 is manufactured by self-aligned features by the method according to the invention, in which the narrow window 52a has an upper side of the semiconductor wafer body 100 (providing the device body 10). Defined by providing sidewall extensions 52 (commonly referred to as “spacers” 52) in the sidewalls of the wider windows 51a in the first mask 51 (FIG. 3) on the surface 10a. A stage (FIG. 4); The trench 20 is etched into the body 100 in a narrow window 52a, the insulating gate 11 comprising a stage provided in the trench 20 (FIG. 5); A stage in which the source region 13 is provided to be self-aligned with the trench-gate 11 by the spacer 52 (FIG. 7); Ⓓ removing the sidewall extension 52 by the insulating overlay layer 18 to eliminate at least part 51n of the first mask 51 by a wider window 51a at the surface 10a of the body. (FIG. 6), (2) sufficient to insulate the insulating material 18 'and to extend above the window 51a and above the first mask portions 51 and 51n. Deposition to a thickness (FIG. 8) and (3) etching the insulating material 18 'to remove the insulating overlay layer 18 in the wider window 51a in the first mask portions 51, 51n. (etching back) and (4) the source electrode (13) in contact with the source region (13) and the adjacent surface region (13) of the body and extending over the insulating overlay layer (18) over the trench-gates (11). 33) providing on the trench-gate by using the step of removing the first mask portions 51, 51n (FIG. 10) before providing (FIG. 12). It comprises a stage.

This allows the insulating overlay layer 18 (and the definition of the contact window 18a for the source electrode 33) to be provided in a reproducible manner by a simple deposition and etch back process that fills the wider window 51a. This is better than the etch back tapered edge of the spacer 52 after etching the trench to form a trench-gate 11 by etching a good quality edge to the window 51a in the first mask portions 51 and 51n. This is achievable because there are vertical and well defined edges. In addition, the formation of this insulating overlay layer 18 is not suppressed by the presence of the spacer 52 because these spacers 52 have been removed. Thus, this process is more preferred than the specific embodiment disclosed in US Pat. No. 6,087,224.

However, this method is disclosed in US Pat. No. 6,087,224 for forming the narrow trench-gate 11 and for determining the source region 13 and its contacts in a self-aligned manner with respect to the narrow trench 20. The disclosed spacer 52 is still used. Instead, a single masking pattern 45, 51 (photo in FIG. 2) is used to determine all subsequent windows (for etching, planarization, doping, contacting, etc.) within the cell regions shown in FIGS. Photo-lithographically defined] is used. This self alignment simplifies manufacturing and allows the reproducible closed space of the transistor cell to have a cell pitch Yc of, for example, about 1 μm or less.

However, further improvements and advantages in the present invention are obtained by forming the insulating overlay layer 18 in the window 51a of the first mask portions 51, 51n. Thus, the overlayer 18 extends from the top of the trench-gate 11 by a well defined lateral distance y4 onto the adjacent body surface 10a (FIGS. 9 and 10). As such, there is a well defined reproducible spacing y4 or y4 'between the sidewall of trench 20 and the edge of contact window 18a. The well-defined reproducible spacing y4 or y4 'provides good protection against shorting of the source electrode 33 to the trench-gate 11 at the edge of the contact window 18a. Other protection against short circuits can be achieved by doping the cap and plug structure for the insulating overlay layer as detailed below with reference to FIG.

Furthermore, the process sequence according to the present invention provides an opportunity for providing source region doping 63 at the stage, which is not inhibited by the simultaneous presence of the first mask portion 51 and the overlayer 18. . Thus, for example, the source region 13 may be preferably provided in the FIG. 7 stage as detailed below.

The doping profile of the channel receiving region 15 adjacent to the isolation trench-gate 11 is important for determining the gate-control characteristics of the channel 12. After insulating overlay layer 18, it may be provided by using high energy impurity-ion implantation, preferably as indicated by arrow 61 in FIG. 10. This is achievable due to the good reproducibility of the edges and the lateral extensions y4 of the overlayer 18 above the channel region. As described above in order, this doping process is well suited for closely spaced cells having, for example, a cell pitch Yc of about 1 μm or less.

The cell pitch and layout shape of the device are determined by the photolithographic and etching stages shown in FIGS. 2 and 3. The top view of the cellular layout shape is not shown because the method of FIGS. 1 to 12 can be used for very different known cell shapes. Thus, for example, the cells may have a square shape or a tightly filled hexagonal shape, or they may have an elongated stripe shape. In each case, trench 20 (with gate 11) extends around the boundary of each cell. 1 shows only a few cells, but in general the device comprises thousands of these parallel cells between the electrodes 33, 34. The active cellular area of the device may be bounded around the periphery of the device body 10 by various known peripheral termination schemes (also not shown). This technique generally involves forming a thick field-oxide layer in the peripheral region of the body surface 10a prior to the transistor cell fabrication step. In addition, various known circuits (such as gate-control circuitry) may be integrated with the device in the region of the body 10 between the active cellular region and the peripheral termination. In general, circuit elements can be fabricated in their own layout within this circuit area using some of the same masking and doping steps as used for transistor cells.

Successive stages in the manufacture of transistor cells are described above with reference to the sequences of FIGS. 2-12 as examples of specific embodiments.

2 shows the body portion of FIG. 1 at an initial stage in device manufacture. In this particular embodiment, thick silicon nitride layer 51 'is deposited on thin silicon dioxide layer 50 on silicon body surface 10a.

In general, oxide layer 50 may be between 30 nm and 50 nm thick. In the embodiment of FIGS. 1-12, the nitride layer 51 ′ is a desired depth and width ratio of the window 51a for the formation of the spacer 52 in FIG. 4, ⓑ low energy ions 63 of the implant of FIG. 7. ) Is selected according to the desired penetration force by the impurity ions 61 in the high energy implantation stage of FIG. 10 and the desired thickness of the insulating overlay layer 18 formed in the planarization stage of FIG.

In certain embodiments of the device, as a specific embodiment, the nitride layer 51 ′ may be in the range of 0.4 μm to 0.5 μm thick, and the window 51a may have a width of about 0.5 μm.

Window 51a is defined using known photolithography techniques. Photoresist mask 45 with corresponding window 51a 'is provided on nitride layer 51', as shown in FIG. This acts as a corrosion mask for etching the window 51a to the layer 51 'to form the mask 51 shown in FIG. The mask 51 and its associated windows (reference numeral 51a in FIG. 3 and narrow window 52a in FIG. 4) have a layout shape that defines the layout of the device cells and their pitch Yc.

Thus, the windows 51a, 52a define the gate boundaries of the cells, for example a hexagonal network in the case of a full hexagonal cellular shape. Whatever layout shape is selected for the embodiment of FIGS. 1-12, the width y1 of the mask 51 between neighboring windows 51a is the desired contact area of the contact window 18a with respect to the electrode 33. Is selected according to.

In this particular embodiment, oxide layer 52 'is deposited along the contour of the top and sidewalls of nitride mask 51 and the bottom of window 51a. The oxide layer 52 'is then etched back in a known manner using directional etching to remove it from the top of the nitride mask 51 and the bottom of the window 51a, while leaving the spacer 52 on the sidewalls. . The etch back also removes the exposed thin oxide layer 50 from the window 52a. In general, the contour-deposited oxide layer 52 ′ may have a thickness of about 0.2 μm such that the remaining width y2 of the spacer 52 is in the range of 0.1 μm to 0.2 μm. 4 shows the resulting structure with a narrower window 52a of width y3 as defined by spacers 52 of width y2.

Trench 20 is etched into body 100 at window 52a. As shown in FIGS. 2-5, the silicon body portion 14 ′ where the trench 20 is etched has the same conductivity from the surface 10a into the portion of the drain region 14, ie, the region providing the drain drift region. It can have a doping concentration (n) of the form. This doping concentration n may be substantially homogeneous, for example about 2 × 10 ¹⁶ or 3 × 10 ¹⁶ phosphorus or arsenic atoms cm ⁻³ . Optionally, as disclosed in US Pat. No. 5,612,567, 5 × 10 ¹⁶ (eg, 1 × 10 ¹⁶ ) phosphorus at the surface 10a or less than arsenic atoms cm ⁻³ to 10 at the interface with the substrate 14a. It may be at least twice (eg, 3 × 10 ¹⁷ phosphorus or arsenic atoms cm ⁻³ ).

In certain embodiments, the depth at which trench 20 is etched may be, for example, about 1.5 μm. This depth is three times the thickness of the mask 51, so the drawing ratio is shown distorted for convenience in these schematic drawings.

The gate dielectric layer 17 is then formed by, for example, thermal oxidation of the silicon body portion 14 ′ at the wall of the trench 20. In the embodiment of FIGS. 1-11, this dielectric layer 17 is drawn at the bottom as well as the sidewall of the trench 20. Then, in a known manner, this gate 11 deposits gate material 11 'to a thickness sufficient to fill trench 20 and extend above window 52a and above masks 51 and 52, and This gate material 11 'is then removed there to form a trench-gate 11. In general, gate 11 may comprise doped polycrystalline silicon or other semiconductor material. Doping concentration may be provided during or after the material 11 ′ is deposited, for example in the etch back stage shown in FIG. 5. In this embodiment, the gate doping concentration is of the first conductivity type (n-type in this embodiment) and is greater than the doping concentration of the second conductivity type introduced at the stage of FIG. 10 for the channel receiving region 15.

The oxide spacer 52 is etched to reopen the window 51a, thus forming a doped window 51b between the mask 51 and the trench-gate 11. This etching also removes the thin oxide 50 underneath the oxide spacers 52. When the window 51b is used for implantation, the thin oxide 50 'regrows in the window 51a on the exposed area of the silicon body surface 10a (also grows on the exposed silicon gate 11). The resulting structure is shown in FIG.

As shown in FIG. 7, the source region 13 of the doping concentration n + is inserted into the main body 100 via the doping window 51b. The nitride layer 51 acts as a mask. Such source doping is preferably performed by implantation of arsenic ions 63. In general, very high doses are used to provide a doping concentration of 10 ²⁰ to 10 ²² arsenic atoms cm ⁻³ . The ion energy is generally about 30 keV. In this dose and energy, arsenic ions are scattered below the edge of the mask 51. After one or more annealing, eg annealing for 1 hour at a temperature of 900 ° C., the source region 13 extends about 0.1 μm to 0.2 μm laterally beyond the window edge line of the mask 51.

As shown in FIGS. 8 and 9, an insulating overlay layer 18 is provided over the trench-gate 11 in the wider window 51a of the first mask 51. What can be called a planarization process is achieved according to the invention. Insulating material 18 '(eg, silicon dioxide) is deposited to a thickness sufficient to fill the window 51a and extend above the window 51a and above the mask 51. The insulating material 18 'is then etched back to remove it from the body surface 10a, which is the trench-gate 11 and the doped window 51b. The thickness of the resulting overlay layer 18 corresponds to the thickness of the mask 51 at this stage of manufacture. In certain embodiments, overlay layer 18 may be between 0.3 μm and 0.4 μm thick. The lateral width y4 of the overlap with the silicon body surface 10a is reproducibly determined by the width y2 of the spacer.

Mask 51 is then removed to form window 18a in insulating overlay layer 18, as shown in FIG. As determined by the lateral width under the mask 51, the source region 13 extends laterally into the window 18a. The lateral width may be particularly sufficient for good low ohmic contact to the source electrode 33 after the implant annealing of FIGS. 10 and 11. However, the overlay layer 18 of FIG. 10 is isotropically etched back a distance sufficient to reduce overlap (from reference y4 to reference y4 ') and not covered by the layer 18. The area of (13) can be increased. This further etched bag is indicated by dashed line 18c in FIG. 10 and its implantation is detailed below with reference to FIG. 11.

The high energy impurity-ion implantation shown in FIG. 10 is implemented to provide the channel receiving region 15. The impurity ions 61 are implanted at a sufficiently high energy and at a sufficiently high dose, and the impurity ions 61 implanted in the window 18a are scattered below some side of the overlayer 18 on the body surface 10a. The ion energy can be high enough and these impurity ions striking on the overlayer 18 penetrate therein to be implanted into the lower portion of the body 100. In general, the impurity ions may be boron with implantation energy in excess of 200 keV. If the overlay layer 18 does not completely mask the trench-gate 11 for this implantation, the boron doping concentration is not sufficient to overdope a portion of the polycrystalline silicon gate material.

The inventors have discovered, for example, that the dose of 2x10 ¹³ cm ^-2 boron ions at the 260 keV ion energy injected into the window 18a is laterally scattered at least 0.4 mu m below the mask edge. Such scattering can provide the desired boron doping concentration laterally adjacent to trench 20, ie under 0.15 μm or 0.2 μm wide width (y4 or y4 ′) of overlayer 18 on body surface 10a. In addition, due to this high energy, the impurity ions 61 can penetrate the thickness of the overlayer 18 (eg, 0.3 μm to 0.4 μm) to enhance the doping concentration adjacent to the trench 20. In general, the doping concentration may be, for example, about 10 ¹⁷ boron atoms cm ⁻³ . The doping concentration of the region 15 adjacent to the trench 20 is determined to be reproducible, as the precisely reproducible thickness, lateral width and edges for the overlayer 18 are determined by using the method described above according to the invention. Because it can be formed. For example, a heating step of 40 minutes at 1,100 ° C. is carried out to anneal the injection damage and activate the impurities. Some thermal diffusion of the implanted impurities occurs during this heating step, which contributes to achieving homogeneity at the doping concentration of region 15.

After providing the channel receiving region 15 via the contact window 18a, additional impurities of the second conductive form (ie, p-type) are introduced into the body 100 (also via the contact window 18a). Introduced to form a higher doped contact region 35 for the channel receiving region 15. This is preferably accomplished by implanting boron ions 65 as shown in FIG. The resulting boron concentration is not sufficient to overdope the source region area exposed in the window 18a. In general, this doping concentration may be, for example, about 10 ¹⁹ elemental boron cm ⁻³ .

As shown in FIGS. 10 and 11, thin oxide 50 is present in the injection window 18. A short dip etch can be used to remove this oxide layer 50 and thus open the window 18a as a contact window for the source electrode 33. Even with very short etching, an isotropic etch back of the oxide layer 18 occurs (both vertically and horizontally) during removal of the oxide layer 50. Etching at this stage may be extended to affect the etch back of the overlayer 18 as shown by dashed lines 18c in FIG. 10. Thus a wider contact area can be achieved between the source region 13 and the electrode 33. Whether such an etch back is carried out in FIG. 10 or before FIG. 10, implantation is a variable design choice in the art. If the etch back is carried out before the implantation 61 of FIG. 10, the effect on the implanted profile of the channel receiving region 15 needs to be considered.

As shown in FIG. 12, the source electrode 33 is in contact with the source region 13 and the contact region 35 in the contact window 18a and over the insulating overlay layer 18 over the trench-gate 11. Is deposited to extend. Generally, the source electrode includes a thick aluminum layer on the silicide contact layer. Its layout (by known photolithography and etching techniques) is defined within the gate bondpads connected to the trench-gates 11 and the individual metallization regions that form the source electrode 33. Gate bondpad metallization and its connections are outside the plane of FIG. 11. The back surface 10b is then metallized to form the drain electrode 34, after which the wafer body 100 is divided into individual device bodies 10.

It is obvious that many variations and modifications are possible within the scope of the invention. Significant flexibility allows the fabrication of other parts of the device and the formation of spacers 52, narrow trenches 20, trench-gates 11, source regions 13, insulating overlay layers 18 and channel receiving regions 15. For the stages ⓐ to ⓓ of the method and in particular techniques that can be used in between. Thus, other novel features (as well as many features in the prior art) can be used in connection with the present invention.

By way of example, FIG. 5 shows an etch back of the gate material 11 ′ stopping slightly below the body surface 10 a. In this case, the insulating overlay layer 18 of FIG. 1 extends slightly laterally over the adjacent region of the surface 10a as well as in the upper portion of the trench 20. This structure for overlay layer 18 is particularly desirable to provide highly reliable protection against unwanted shorting at the top edge of gate trench 20 as shown in the enlarged view of FIG. 13.

Thus, after the provision of the gate dielectric 17, some corrosion of the gate dielectric 17 may occur at the upper edge of the gate trench 20 during exposure to various process stages. Such corrosion may present a risk of causing undesirable short circuits between the gate 11 and the source region 13 and / or the source electrode 33 in the final device. However, as shown in FIG. 13, the deposited and etched oxide material 18 remains to form an insulating plug on top of the trench 20 and to form trench 20 as an insulating cap at the trench-gate of the source region 13. Extend laterally). This combined plug and cap structure of the overlayer 18 provides very reliable insulation of the top edge of the gate trench 20 to protect it from short circuits.

However, the etch back of the gate material 11 'may be stopped in line with the level of the body surface 10a or may stop when slightly higher than the body surface 10a. In the latter case, the trench-gate 11 slightly protrudes above the level of the body surface 10a, and the overlayer 18 is above the trench-gate 11 protruding instead of descending into the trench 20 [spacer ( Into the space removed by 20).

In the particular embodiment described above with reference to FIGS. 1 through 13, each of the mask 51 and the spacer 52 is made of a separate single material (silicon nitride, silicon oxide). Other embodiments are possible in which composite layers of different materials are used. Thus, for example, a thick composite mask 51 may be used at the initial stage of the process, after which the mask 51 may be thinned by removal of the upper portion. Pending PCT patent applications EP01 / 09330 (and corresponding US patent applications 09/932073 and UK patent applications 0020126.9 and 0101690.6; Applicant reference number PHNL010059) disclose the use of composite sidewall spacers. In particular, a trench-etch mask 51 of oxide is disclosed, the window of which is narrowed by a composite sidewall spacer 52 comprising polysilicon on a thin layer of silicon nitride.

In a variant embodiment of the invention, the mask 51 may be made of silicon nitride and the spacer 52 may be a composite of polysilicon on a thin nitride layer 50 '. Other variations are possible in which oxides are used instead of nitrides. Thus, the spacer may be a composite formed by contouring the polysilicon material 52 'onto the thin layer 50'. In this case, when the trench 20 is etched into the body region 14 ′ as shown in FIG. 14, the etching removes the polysilicon portion 52m (not shown) of the spacer 52. The resulting structure is shown in FIG. 14. The narrowed trench-etching window 52a remains defined by the thin layer 50 '(ie, the lower spacer portion 52n). Thereafter, gate dielectric 17, gate 11 and regions 13 and 15 are provided as described above. A wider window 51a formed by the removal of the upper spacer portion 52m is used to provide an insulating overlay layer 18 on the gate 11 in accordance with the present invention.

With respect to the particular embodiment described above solely as the initial mask 51 of silicon nitride, it can be seen that oxygen-nitride is formed on the mask surface when the mask surface is exposed to an oxidizing atmosphere in the order of the manufacturing process. Thus, for example at the stage of FIGS. 5 and / or 8, nitride mask 51 may include an oxygen-nitride surface that is etched when oxide spacer 52 and / or oxide material 18 ′ is etched. Therefore, the mask 51 is thinned in these stages. This may indicate some uncertainty in the thickness of the mask portion 51 remaining during the implantation stage of FIG. 7 and the oxide planarization stage of FIG. 9. In addition, the use of thick silicon nitride for the mask 51 distorts and deflects the silicon wafer body 100 during manufacturing.

These advantages can be avoided by forming the first mask 51 as a composite comprising an upper layer portion 51m on the lower layer portion 51n in stage ⓐ. The upper layer portion 51m is etchable from the lower layer portion 51n by being made of a material (for example, oxide) different from the lower layer portion 51n (mostly nitride). Such composite masks 51m and 51n are shown in FIG. 15 as a variation of FIG. The upper layer portion 51m may be etched from the lower side portion 51n before or after implanting the impurity ions 63 for the source region 63. By removing the upper layer portion 51m, as shown in FIG. 16, only the lower layer portion 51n of the mask 51 acts to define the insulating overlay layer 18 deposited and etched back in stage ⓓ. The reduced thickness of the nitride layer 51n (compared to the thick nitride layer 51) causes reduced splashing on the silicon wafer body 100 during manufacturing, thereby reducing warpage of the wafer body 100.

In the embodiment of FIG. 10, the impurity ions 61 implanted for the channel receiving region 15 are high energy to be scattered under the overlayer 18 and to penetrate the overlayer 18. Thus, the desired doping profile for the channel receiving region 15 is injected, without long drive-in diffusion. However, drive-in diffusion can be used for some devices, especially devices with very large cell pitch Yc and / or when less energy impurity 61 implantation is used.

1 to 12, the source region 13 is most conveniently formed by implanting the impurity ions 63 in the doped window 51b formed by removing the spacer 52. In the embodiment shown in FIG. However, the spacer 52 can be used in other ways to provide self alignment of the source region with trench-gates.

In one of these alternative embodiments, source region 13 may diffuse into body 100 from arsenic or phosphor that is doped into spacer 52 itself or into a portion of overlayer 18.

In another exemplary method, source region 13 may be formed by n-type layer 13 ′ at surface 10a. This is done by providing a doped layer 13 'before the mask 51, and while using the lateral extension y4 or y4' of the overlayer 18 on the surface 10a as a corrosion mask. By etching through to the lower region 15. This lateral extension of the overlayer 18 is determined by the spacer 52. Etch definition of the source region 13 may be implemented prior to etching back the overlay layer 18 as indicated by dashed line 18c in FIG. 10.

17 and 18 show another variation that provides an additional source region stripe that extends across the transistor cell, along with the etching regime of the source region 13. Thus, in the modified embodiment of FIGS. 17 and 18, the cell is of elongated stripe shape. The individual source region 13 of each cell comprises a self-aligned portion 13a extending along the sidewall of the gate trench 20 and a transverse portion 13b extending laterally relative to the gate trench 20. Structure. The lateral width of the self-aligned portion 13a is defined by the lateral extensions y4 or y4 'of the overlayer 18, and thus the spacer 52. The lateral width of the transverse portion 13b is defined by an additional mask 83 comprising stripes (eg of photoresist) extending laterally relative to the gate trench 20, ie the narrow trench 20. ) Is not important. The composite source region structures 13a and 13b can be formed by implantation rather than by etching rules. Thus, after forming the self-aligned portion 13a in the stage of FIG. 7, another source implantation may occur in the window between stripes of the mask 83 ′ across the elongated stripe shaped cell, for example, in the stage of FIG. 10. Can be implemented.

In another variant, the source impurity 63 may be implanted into the window 51a at the stage of FIG. 3, thus applying the initial source region 13 ′ to the entire window 51a before forming the spacer 52. to provide. Thereafter, a layer 52 'is deposited, a spacer 52 is formed in FIG. 4, and the trench 20 is then etched into the narrow window 52a in FIG. 5. In this case, the trench 20 is etched through the initial region 13 ′ to the body portion 14 ′. The portion of the region 13 ′ remaining under the spacer 52 forms a source region 13 self-aligned with the trench 20. This process sequence for forming the source region 13 is less desirable than the process sequence of FIG. 7, where the highly doped implanted region 13 ′ is typically etched slightly faster than the body portion 14 ′ so that the trench ( This is because the upper portion of 20) is expanded.

Instead of forming the drain-drift region 14 by the epitaxial layer on the highly doped substrate 14a, the highly doped region 14a of some devices may be formed of a highly resistive substrate that provides the drift region 14. It may be formed by diffusion of impurities into the back surface 10b. The device described above is a MOSFET, where the highly doped substrate 14a or region 14a is of the same conductive form (n-type in this embodiment) as the drain drift region 14. However, the highly doped substrate 14a or region 14a may be of opposite conductivity type (p-type in this embodiment) to provide the IGBTs. The electrode 34 is called an anode electrode in the case of IGTB.

The vertical individual device is shown with reference to FIG. 1 and has a second main electrode 34 in contact with the substrate or other region 14a at the back 10b of the body 10. However, an integrated device according to the invention is possible. In this case, region 14a may be a doped buried layer between the device substrate and the lightly doped epitaxial drain region 14. This buried layer region 14a may be contacted by the electrode 34 at the front major surface 10a via a doped peripheral contact region extending from the surface 10a to the depth of the buried layer.

The conductive gate 11 may be formed of doped polycrystalline silicon as described above. However, other known gate techniques may be used in certain devices. Thus, other materials can be used for the gate, for example metal silicides. Optionally, the entire gate 11 may be a heat resistant metal instead of polycrystalline silicide.

In the embodiment of FIGS. 1-18, the gate dielectric layer 17 is located on the sidewalls as well as the bottom of the trench 20. However, in the remaining embodiments trench 20 may be slightly deeper and may have a thick insulating material 17b at its bottom. Thick insulator 17b at the bottom of trench 20 reduces the gate-drain capacity of the device. Such an embodiment is shown in FIGS. 19-21.

In this case, the slightly deeper trench 20 is etched in the narrow window 52a defined by the oxide spacer 52. Thereafter, insulating material 17b ′ is deposited to a sufficient thickness to fill trench 20 and extend over trench 20 and over spacers 52 and mask 51. Material 17b 'may be, for example, silicon dioxide. This stage is shown in FIG.

The material 17b 'is then etched back until it is only at the bottom of the trench 20 to form a thick insulator 17b. This etch back removes the oxide spacers 52 to re-expose the wider window 51a. A thin gate-dielectric layer 17 is then provided to the exposed sidewalls and surface 10a of the trench 20 and the oxide layer 50 is removed along with the spacer 52. The resulting structure is shown in FIG. 20.

The gate material 11 'is then deposited to fill the wide window 51a and the trench 20 therein and extends over the mask 51. As shown in FIG. 21, the gate material 11 ′ is then etched back to remain as a gate 11 in the trench 20. In this case, as shown in FIGS. 20 and 21, the spacer 52 is removed to define the window 52b before the gate 11 is provided in the trench 20. Thus, the structure of FIG. 21 can be compared with the structure of FIG. 14. After the stage of FIG. 21, the regions 13, 15 are formed by impurity implants 61, 63, as in FIGS. 7 and 10, and then subsequent processes as shown, for example, in FIGS. 11 and 12 are performed. Is carried out.

Thermal oxide is preferred as the high quality gate dielectric layer, but layer 17 may be deposited.

The particular embodiment described above is an n-channel device, wherein regions 13 and 14 are n-type conductive, regions 15 and 35 are p-type, and electron inversion channel 12 is Guided into region 15 by gate 11. By using impurities of opposite conductivity type, p-channel devices can be produced by the method according to the invention. In this case, regions 13 and 14 are p-type conductive, regions 15 and 35 are n-type, and hole inversion channel 12 is gated by region 11. Induced to.

Semiconductor materials other than silicon, for example silicon carbide, can be used for the device according to the invention.

The figure shows a general and preferred state of the insulated gate structure, wherein the conductive gate 11 is capacitively connected to the channel receiving region 15 by the dielectric layer 17. However, the so-called Schottky gate technique can optionally be used for some devices, especially accumulation-mode devices, where the channel receiving body region 15 is a highly doped source and drain region 13, 14. The same conductive form as). In this case, the gate dielectric layer 17 is not present and the conductive gate 11 is a metal forming a Schottky barrier having a lightly doped channel accept fraction of the region 15. The Schottky gate 11 is capacitively connected to the channel receiving region 15 by a depletion layer present in the Schottky barrier.

Through the detailed description of the present invention, other changes and modifications will be apparent to those skilled in the art. Such changes and modifications may include equivalents and other features that are already known in the art and may be used in place of or in addition to the features already described herein.

While the claims are contemplated for certain combinations of features in the present application, the scope of the present invention is not all or part of the same technical problems as the present invention or whether the scope relates to the same invention as claimed in the claims. It is to be understood that it includes novel features or novel combinations of features or features described herein, either explicitly or implicitly, regardless of whether or not they solve the problem.

The Applicant noted that the new claims detail these features and / or combinations of these features during the procedure of this application or other applications inferred therefrom.

Thus, no matter how the overlay layer 18 is provided and used, a novel method of fabricating an insulated trench-gate semiconductor device (shown in FIGS. 19-21) has been provided, which

A narrow window is defined by providing sidewall extensions to the sidewalls of the wider window in the first mask on the surface of the semiconductor body,

Ⓑ The trench is etched into the body of the narrow window,

The trench is covered by an insulating material, after which the gate is provided to the trench,

Source region is provided to self-align with the trench-gate by sidewall extensions,

Wherein stage ⓒ includes the use of the following series of steps to provide a first insulating material thicker than that provided for the gate-dielectric at the sidewalls of the trench below the gate,

These series of steps include: 1) filling a trench to deposit a first insulating material to a thickness sufficient to extend over the trench, over the sidewall extensions, and over the first mask;

(2) etching back the first insulating material to remove the first insulating material from the bottom of the trench, wherein the etch back process removes sidewall extensions to re-expose a wider window within the first mask portion. With a hundred steps,

(3) providing a thinner gate dielectric layer on the sidewalls of the trench;

(4) depositing gate material to fill the wider window and isolation trench therein;

Etching the gate material such that the gate material remains over the first insulating material and as a gate adjacent the gate dielectric layer.

Further, a novel method of fabricating a novel trench-gate semiconductor device having an elongated stripe cell and complex source region structure, regardless of how the overlay layer 18 is provided and used, one embodiment of which is shown in FIGS. 17 and 18. Shown in FIG. The elongated cell is bounded by trench-gates 11 in trenches 20 that extend from source region 13 to underlying drain region 14 through channel receiving region 15. The composite source region structure includes a self-aligned portion 13a extending along the sidewall of the gate trench 20 and a transverse portion 13b extending laterally relative to the gate trench 20.

In a novel manufacturing method of the device, the lateral width of the transverse portion 13b is applied to a mask 83 comprising stripes (eg, of photoresist) extending transverse to the gate trench 20. It is prescribed by. The alignment of these stripes to the narrow trench 20 is not critical. In general, mask 83 may be a doping mask (eg, an injection mask) or an etching mask.

The other portion 13a of the source region is self aligned with respect to the gate trench 20. Their lateral width can be determined by the spacers 52, which themselves define the etching of the trench into the semiconductor body in the narrowed etching mask windows 51a, 52a. One embodiment is by doping in windows 51a and / or 51b in trench-etch masks 51 and 52, one embodiment of which is shown in FIG. Another embodiment is by etching using the overlayer 18 as shown in FIGS. 17 and 18. Another embodiment is by doping from the spacer 52 itself. However, even in a manufacturing method that does not include providing a spacer, various other methods of forming the self-aligned portion 13a are possible. Thus, for example, the self-aligned portion 13a may be formed by transverse diffusion from the doped insulating plug in the top of the gate trench, or by inclined implant in the sidewall of the top of the trench.

Claims (18)

A method of manufacturing a trench-gate semiconductor device having a trench-gate in a trench extending through a channel receiving region from a source region to a drain region, the method comprising: A narrow window is defined by providing sidewall extensions to the sidewalls of the wider window in the first mask on the surface of the semiconductor body, A trench is etched in the body of the narrow window, the gate is provided in the trench, Ⓒ the source region is provided adjacent to the sidewall of the trench, Ⓓ The insulation overlayer is a series of steps, i.e. removing the sidewall extension to obviate at least a portion of the first mask by a wider window at the surface of the body, and 2) insulating material to fill the wider window. Depositing a sufficient amount and a thickness sufficient to extend over the wider window and on the first mask portion, e. Etching the insulating material to remove the insulating overlay in the wider window in the first mask portion. Etching back, ④ removing the first mask portion prior to providing a source electrode in contact with the source region and adjacent surface regions of the body and extending over an insulating overlay layer over the trench-gate. Is provided on the trench-gate by using Method of manufacturing a trench-gate semiconductor device. The method of claim 1, The series of stages ⓑ and ⓒ are such that the source region defined in stage ⓒ has a doping concentration of a first conductivity type provided in the body after providing the gate in the trench at stage ⓑ. Method of manufacturing a trench-gate semiconductor device. The method according to claim 1 or 2, The source region is provided at stage © in a self-aligned manner with the trench-gate by sidewall extensions. Method of manufacturing a trench-gate semiconductor device. The method of claim 3, wherein The source region removes at least a portion of the first mask by the wider window at the surface of the body before depositing the insulating material for the insulating overlay layer, and a doping window between the first mask portion and the trench-gate. Removing the sidewall extension to form a wider window within said wider window; (b) introducing impurities of a first conductivity type into said body via said wider window to form a source region adjacent said trench-gate; Provided later after the gate using a laterally extending portion of the first mask portion laterally Method of manufacturing a trench-gate semiconductor device. The method according to any one of claims 1 to 4, The trench is etched through a silicon body portion having a doping concentration of the first conductivity type extending from the surface into the lower region to provide a portion of the drain region at stage ⓑ, and a gate dielectric layer is formed at the wall of the trench. Formed by thermal oxidation of the silicon body portion Method of manufacturing a trench-gate semiconductor device. The method according to any one of claims 1 to 5, The channel receiving region of the second conductivity type may be formed by removing the first mask portion at stage ⓓ to form a doped window in the insulating overlay layer, and forming the doped window to form the channel receiving region in the doped window. Formed adjacent to the trench-gate using a step of introducing impurities of the second conductivity type into the body via extending laterally downward of the insulating overlay layer with respect to the trench Method of manufacturing a trench-gate semiconductor device. The method of claim 6, The channel receiving region is formed at a sufficiently high energy and sufficiently high dose that the impurity ions implanted into the doping window in the insulating overlay layer scatter laterally down the insulating overlay layer to reach the trench after stage ⓓ. 2 formed by ion implantation of impurities in a conductive form Method of manufacturing a trench-gate semiconductor device. The method of claim 7, wherein The impurity ion is boron having an implantation energy exceeding 200 keV. Method of manufacturing a trench-gate semiconductor device. The method according to any one of claims 1 to 8, The gate is provided in a portion of the trench below the level of the body surface, and then the insulating material of stage ⓓ that is deposited and etched back remains on top of the trench and from the trench into the wider window of the first mask portion. Laterally extended Method of manufacturing a trench-gate semiconductor device. The method according to any one of claims 1 to 9, The first mask of stage ⓐ is a composite comprising an upper layer portion on a lower layer portion, wherein the upper layer portion is made of a different material from the lower layer portion to be etchable from the lower layer portion, the upper layer portion Is etched from the lower layer portion prior to providing the insulating overlay in stage ⓓ Method of manufacturing a trench-gate semiconductor device. The method of claim 10, The upper layer portion is made of silicon dioxide, and the lower layer portion is made of silicon nitride Method of manufacturing a trench-gate semiconductor device. The method according to any one of claims 1 to 11, After providing the insulating overlay layer at stage ⓓ, the channel receiving region is ㉠ removing the first mask portion to form a contact window in the insulating overlay layer, and 보다 a higher doped contact for the channel receiving region. Introducing an impurity of the second conductivity type into the body via the contact window to form a region; (b) contacting the source region and the contact region at the contact window and overlying the insulating overlay layer over the trench-gate; Contacting using depositing the source electrode to extend up Method of manufacturing a trench-gate semiconductor device. The method according to any one of claims 1 to 12, After removing the first mask portion at stage ⓓ and before providing the source electrode, the back material is etched isotropically with a distance sufficient to increase the area of the source region that is not covered by the insulating overlay layer. felled Method of manufacturing a trench-gate semiconductor device. The method according to any one of claims 1 to 13, The gate is provided in the trench prior to removing the sidewall extension to re-expose the wider window. Method of manufacturing a trench-gate semiconductor device. The method according to any one of claims 1 to 14, After etching the trench, the sidewall extension is removed to re-expose the wider window, and then gate material is deposited to fill the wider window and the trench therein and remains as the gate in the trench. Etched back to Method of manufacturing a trench-gate semiconductor device. The method of claim 15, Prior to removing the sidewall extension, an insulating material is deposited to a thickness sufficient to fill the trench and extend over the trench, over the sidewall extension, and on the first mask, after which the sidewall extension is formed of the insulating material. Is removed in the etching step of etching back the insulating material until only the bottom portion of the trench remains, and the gate is then provided to a portion of the trench over the insulating material in the lower portion. Method of manufacturing a trench-gate semiconductor device. The method according to any one of claims 1 to 16, The first mask includes silicon nitride, the sidewall extension includes silicon dioxide, and the insulating overlayer comprises silicon dioxide. Method of manufacturing a trench-gate semiconductor device. The method according to any one of claims 1 to 16, The sidewall extension includes polysilicon material on a thin insulating layer, and the polysilicon material of the sidewall extension is removed at the etching stage ⓑ providing the trench. Method of manufacturing a trench-gate semiconductor device.