CN213519864U - Super junction - Google Patents

Super junction Download PDF

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Publication number
CN213519864U
CN213519864U CN202023002477.3U CN202023002477U CN213519864U CN 213519864 U CN213519864 U CN 213519864U CN 202023002477 U CN202023002477 U CN 202023002477U CN 213519864 U CN213519864 U CN 213519864U
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epitaxial layer
conductive type
type doping
semiconductor substrate
super junction
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顾冬梅
黄继颇
杨维
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Shanghai Saiying Microelectronics Co ltd
Anhui Saiteng Microelectronics Co ltd
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Shanghai Saiying Microelectronics Co ltd
Anhui Saiteng Microelectronics Co ltd
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Abstract

The utility model provides a super knot, this super knot includes: the semiconductor substrate comprises a semiconductor substrate, a second conductive type doping region and a second epitaxial layer, wherein the surface of the semiconductor substrate is provided with a first epitaxial layer doped with a first conductive type, the second conductive type doping region and the second epitaxial layer are doped with a second conductive type, the second conductive type doping region is located between the second epitaxial layer and the semiconductor substrate, the second conductive type doping region and the second epitaxial layer are vertically aligned, and regions formed by the second conductive type doping region and the second epitaxial layer are staggered with the first epitaxial layer. Through the utility model provides a super junction can reduce the technology cost, weakens the technology degree of difficulty, improves the reliability of device.

Description

Super junction
Technical Field
The utility model relates to a semiconductor device makes technical field, specifically relates to a super junction.
Background
A super junction is a structure that is widely used in semiconductor devices. The super junction structure is composed of P-type and N-type doped columns which are alternately arranged in a drift region. The super junction MOSFET manufactured on the basis of the super junction can obtain very low on-resistance while maintaining very high breakdown voltage in an off state. In the off state of the MOSFET, the pillars are fully depleted at a relatively low voltage, so that a high breakdown voltage can be maintained. For a super junction MOSFET, the on-resistance increases in proportion to the breakdown voltage BV, more slowly than in a conventional semiconductor structure. Therefore, for a given on-resistance, a super junction device has a higher breakdown voltage than a conventional MOSFET.
In the prior art, the preparation processes of the super junction are mainly divided into two main categories, namely a multi-layer epitaxy process, and a deep trench and epitaxy filling process. The multilayer epitaxy process needs 6-7 times of epitaxy growth and photoetching, and the cost is high. The deep trench and epitaxial filling technology has low cost, but needs to etch the deep trench with the thickness of about 50um, and has high requirements on the process and poor reliability.
SUMMERY OF THE UTILITY MODEL
To super junction preparation technology among the prior art requirement very high, the reliability is poor, the higher technical problem of cost, the utility model provides a super junction adopts this super junction preparation method can reduce the processing cost, weakens the technology degree of difficulty to improve the reliability of device.
In order to achieve the above object, the present invention provides a super junction, the super junction includes: the semiconductor substrate comprises a semiconductor substrate, a second conductive type doping region and a second epitaxial layer, wherein the surface of the semiconductor substrate is provided with a first epitaxial layer doped with a first conductive type, the second conductive type doping region and the second epitaxial layer are doped with a second conductive type, the second conductive type doping region is located between the second epitaxial layer and the semiconductor substrate, the second conductive type doping region and the second epitaxial layer are vertically aligned, and regions formed by the second conductive type doping region and the second epitaxial layer are staggered with the first epitaxial layer.
Further, the thickness of the first epitaxial layer is between 10um and 100 um.
Further, the thickness ratio of the first epitaxial layer, the second conductive type doped region and the second epitaxial layer is 2:1: 1.
Through the technical scheme provided by the utility model, the utility model discloses following technological effect has at least:
the utility model discloses a super junction preparation method, form the mask layer that has the sculpture window on the first epitaxial layer that has the doping of first conductivity type, form the vertically shallow ditch groove in first epitaxial layer through the mask layer, then utilize the self-alignment of shallow ditch groove, the first epitaxial layer bottom the shallow ditch groove carries out the ion implantation of a lot of second conductivity type, then get rid of the mask layer, carry out the heat propulsion, mix the doping of second conductivity type and spread, form second conductivity type doping area between shallow ditch groove and semiconductor substrate, second conductivity type doping area and shallow ditch groove vertical alignment, then the ditch inslot intussuseption in the front has the second epitaxial layer that the doping of second conductivity type, form super junction, this super junction second epitaxial layer and the region and the first epitaxial layer staggered arrangement that the doping of second conductivity type formed. The depth of the etched shallow groove is shallow, the process requirement is low, and only one time of epitaxial growth is needed in the process of manufacturing the super junction, so that the technical effects of reducing the process cost, weakening the process difficulty and improving the reliability of the device are realized.
Other features and advantages of the present invention will be described in detail in the detailed description which follows.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a super junction according to an embodiment of the present invention;
fig. 2 is a cross-sectional view of a semiconductor substrate prepared by a super junction manufacturing method according to an embodiment of the present invention;
fig. 3 is a cross-sectional view of a mask layer formed according to a method for fabricating a super junction provided in an embodiment of the present invention;
fig. 4 is a cross-sectional view of a shallow trench formed by a super junction manufacturing method according to an embodiment of the present invention;
fig. 5 is a cross-sectional view illustrating a second conductivity type ion implantation performed according to an embodiment of the present invention;
fig. 6 is a cross-sectional view of a second conductivity type doped region formed according to a super junction fabrication method provided in an embodiment of the present invention;
fig. 7 is a cross-sectional view of a second epitaxial layer formed according to a super junction fabrication method provided by an embodiment of the present invention;
fig. 8 is a cross-sectional view of a super junction formed by a super junction manufacturing method according to an embodiment of the present invention.
Description of the reference numerals
100 semiconductor substrate 200 first epitaxial layer
300 mask layer 400 second conductivity type doped region
500 second epitaxial layer 210 shallow trench
Detailed Description
The following describes in detail embodiments of the present invention with reference to the accompanying drawings. It is to be understood that the description herein is only intended to illustrate and explain embodiments of the present invention, and is not intended to limit embodiments of the present invention.
It should be noted that, in the present invention, the embodiments and features of the embodiments may be combined with each other without conflict.
In the present invention, unless otherwise specified, the use of directional terms such as "upper, lower, top, bottom" and "upper" are generally used with respect to the orientation shown in the drawings or the positional relationship of the components with respect to each other in the vertical, vertical or gravitational direction.
The present invention will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Referring to fig. 8, the present invention provides a super junction, including: the semiconductor device comprises a semiconductor substrate 100, a second conductive type doping region 400 and a second epitaxial layer 500, wherein a first epitaxial layer 200 with first conductive type doping is formed on the surface of the semiconductor substrate 100, the second conductive type doping region 400 and the second epitaxial layer 500 are doped with second conductive type doping, the second conductive type doping region 400 is located between the second epitaxial layer 500 and the semiconductor substrate 100, the second conductive type doping region 400 is vertically aligned with the second epitaxial layer 500, and regions formed by the second conductive type doping region 400 and the second epitaxial layer 500 are staggered with the first epitaxial layer 200.
Further, the thickness of the first epitaxial layer 200 is between 10um and 100 um.
Further, the thickness ratio of the first epitaxial layer 200, the second conductive type doped region 400 and the second epitaxial layer 300 is 2:1: 1.
Referring to fig. 1, an embodiment of the present invention provides a method for manufacturing a super junction, including the following steps:
s101: providing a semiconductor substrate, wherein a first epitaxial layer with first conductive type doping is formed on the surface of the semiconductor substrate;
s102: forming a mask layer on the surface of the first epitaxial layer, wherein the mask layer is provided with an etching window, and the shape and the position of a shallow groove are defined by the etching window;
s103: etching the first epitaxial layer through the etching window to form a vertical shallow trench in the first epitaxial layer 200;
s104: performing multiple times of ion implantation of a second conductive type on the first epitaxial layer at the bottom of the shallow trench by utilizing the self-alignment of the shallow trench, wherein the second conductive type is different from the first conductive type;
s105: removing the mask layer;
s106: performing thermal drive to diffuse the second conductive type doping to form a second conductive type doping region, wherein the second conductive type doping region is located between the bottom of the trench and the surface of the semiconductor substrate 100, and the second conductive type doping region is vertically aligned with the shallow trench;
s106: and filling a second epitaxial layer doped with a second conductive type in the shallow trench to form the super junction, wherein the regions formed by the second epitaxial layer and the second conductive type doped region are staggered with the first epitaxial layer.
The super junction manufacturing method provided by the present application will be described in detail below with reference to the accompanying drawings.
Step S101 is first executed: a semiconductor substrate 100 is provided having a first epitaxial layer 200 formed with a first conductivity type doping on the surface of the semiconductor substrate, as shown in fig. 2.
Specifically, the material of the semiconductor substrate 100 includes, but is not limited to, a single crystal or polycrystalline semiconductor material, and may be an intrinsic single crystal silicon substrate or a lightly doped silicon substrate, and further may be an N-type polycrystalline silicon substrate or a P-type polycrystalline silicon substrate.
Further, the thickness of the first epitaxial layer 200 is between 10um and 100 um.
Step S102 is performed next: a mask layer 300 is formed on the surface of the first epitaxial layer 200, and the mask layer 300 has an etching window, and the etching window defines the shape and the position of the shallow trench 210, as shown in fig. 3.
Specifically, the mask layer 300 includes photoresist, the mask layer 300 can be formed on the surface of the first epitaxial layer 200 by a spin coating method, and an etching window is formed on the mask layer 300 by an exposure lithography process, and the etching window can define the shape and position of the shallow trench 210.
Step S103 is performed next: etching the first epitaxial layer 200 through the etching window, and forming a vertical shallow trench 210 in the first epitaxial layer 200, as shown in fig. 4.
Specifically, the utility model discloses in the real-time mode of execution, carry out the sculpture to first epitaxial layer 200 through the etching window, form vertically shallow trench 210 in first epitaxial layer 200, the depth of shallow trench 210 is 1 with the ratio of the thickness of first epitaxial layer 200: 2.
further, the etching the first epitaxial layer 200 through the etching window includes: and performing plasma dry etching on the first epitaxial layer 200 through the etching window.
Specifically, the utility model discloses in the embodiment, can form vertically shallow trench 210 at first epitaxial layer 200 through plasma dry etching, guarantee the homogeneity of shallow trench 210 vertical morphology and interior appearance, avoid horizontal sculpture, guarantee the reliability of super junction.
Step S104 is performed next: with the self-alignment of the shallow trench 210, a plurality of ion implantations of a second conductivity type, different from the first conductivity type, are performed on the first epitaxial layer 200 at the bottom of the shallow trench 210, as shown in fig. 5.
Specifically, in the embodiment of the present invention, the photoresist is formed on the surface of the first epitaxial layer 200, and the self-alignment of the shallow trench 210 is utilized to perform a plurality of ion implantations of the second conductivity type, so as to implant the second conductivity type doping into the bottom of the shallow trench 210, wherein the second conductivity type doping is different from the first conductivity type doping of the first epitaxial layer 200.
Furthermore, the ion implantation times are four times, and the energy of each ion implantation is 4Mkev, 3Mkev, 1.5Mkev and 500Kev in sequence.
According to the utility model provides a super junction preparation method, it can make the perpendicular of the ion in first epitaxial layer 200 distribute more evenly to carry out ion implantation with different energies many times.
Step S105 is performed next: the mask layer 300 is removed as shown in fig. 6.
Step S106 is performed next: performing thermal drive to diffuse the second-conductivity-type dopant to form a second-conductivity-type dopant region 400, wherein the second-conductivity-type dopant region 400 is located between the bottom of the trench 210 and the surface of the semiconductor substrate 100, and the second-conductivity-type dopant region 400 is vertically aligned with the shallow trench 210, as shown in fig. 7.
Specifically, in the embodiment of the present invention, after the mask layer 300 is removed, thermal drive is performed, so that the implanted second conductive type dopant is activated and diffused, and the second conductive type dopant region 400 is formed at the bottom of the trench 210. The second-conductivity-type-doped region 400 is vertically aligned with the shallow trench 210 and is located between the shallow trench 210 and the surface of the semiconductor substrate 100.
Further, the temperature of the thermal propulsion is between 1000 ℃ and 1100 ℃, and the time of the thermal propulsion is between 30min and 60 min.
According to the utility model provides a super knot manufacturing method can improve the withstand voltage of super knot through the propulsion temperature and the propulsion time of choosing.
Step S107 is performed next: the shallow trench 210 is filled with a second epitaxial layer 500 doped with a second conductive type to form the super junction, and the regions formed by the second epitaxial layer 500 and the second conductive type doped region 400 are staggered with the first epitaxial layer 200, as shown in fig. 8.
Specifically, the shallow trench 210 is filled with a second epitaxial layer 500, and the second epitaxial layer 500 has the same second conductive type doping as the second conductive type doping region 400, so as to form staggered P-type and N-type super junctions.
Further, the thickness ratio of the first epitaxial layer 200, the second conductive type doped region 400 and the second epitaxial layer 500 is 2:1: 1.
According to the utility model provides a super knot manufacturing method can improve the withstand voltage of super knot, improves the withstand voltage of super knot to 150 volts to 1500 volts.
Further, the first conductive type is an N type, and the second conductive type is a P type; or the first conduction type is a P type, and the second conduction type is an N type.
Specifically, in the embodiment of the present invention, the semiconductor substrate 100 is doped N-type, the first epitaxial layer 200 is doped N-type, the second conductive type doped region 400 and the second epitaxial layer 500 are doped P-type, and the ion implanted impurity is boron.
Through the utility model provides a super knot manufacturing approach, in the manufacturing process, the degree of depth of shallow trench sculpture is shallower, and the technological requirement is low, only needs to carry out once epitaxial growth in the super knot in-process of preparation moreover, has realized reduction technology cost, weakens the technology degree of difficulty, improves the technological effect of the reliability of device.
The preferred embodiments of the present invention have been described in detail with reference to the accompanying drawings, however, the present invention is not limited to the details of the above embodiments, and the technical concept of the present invention can be within the scope of the present invention to perform various simple modifications to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.
It should be noted that the various technical features described in the above embodiments can be combined in any suitable manner without contradiction, and in order to avoid unnecessary repetition, the present invention does not need to describe any combination of the features.
In addition, various embodiments of the present invention can be combined arbitrarily, and the disclosed content should be regarded as the present invention as long as it does not violate the idea of the present invention.

Claims (3)

1. A super-junction, comprising:
the semiconductor device comprises a semiconductor substrate (100), a second conductive type doping region (400) and a second epitaxial layer (500), wherein a first epitaxial layer (200) with first conductive type doping is formed on the surface of the semiconductor substrate (100), the second conductive type doping region (400) and the second epitaxial layer (500) are doped with second conductive type doping, the second conductive type doping region (400) is located between the second epitaxial layer (500) and the semiconductor substrate (100), the second conductive type doping region (400) and the second epitaxial layer (500) are vertically aligned, and regions formed by the second conductive type doping region (400) and the second epitaxial layer (500) are staggered with the first epitaxial layer (200).
2. The super-junction according to claim 1, wherein the thickness of the first epitaxial layer (200) is between 10um and 100 um.
3. The super junction according to claim 1, wherein a thickness ratio of the first epitaxial layer (200), the second conductivity type doped region (400), and the second epitaxial layer (500) is 2:1: 1.
CN202023002477.3U 2020-12-11 2020-12-11 Super junction Active CN213519864U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202023002477.3U CN213519864U (en) 2020-12-11 2020-12-11 Super junction

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202023002477.3U CN213519864U (en) 2020-12-11 2020-12-11 Super junction

Publications (1)

Publication Number Publication Date
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Country Status (1)

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CN (1) CN213519864U (en)

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