CN109037310B - Super junction power device terminal structure and preparation method thereof - Google Patents
Super junction power device terminal structure and preparation method thereof Download PDFInfo
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Abstract
A super junction power device terminal structure and a manufacturing method thereof belong to the technical field of power semiconductors. The invention comprises a substrate, an epitaxial layer, a stop ring and a multi-layer gradient doped region; a plurality of layers of gradient doped regions are arranged in the epitaxial layer of the terminal region from top to bottom along the transverse direction, and the doping concentration and the extension depth of the gradient doped regions are gradually changed. Along the transverse direction of the device, the surface doping concentration reaches the lowest in the direction close to the channel stop ring, the electric field peak value of the junction edge is effectively reduced, and meanwhile, the extension depth of the gradually-changed doping region from the inside of the device to the surface along the transverse direction is increased progressively, so that the influence of the junction edge curvature effect on the breakdown voltage is favorably relieved; along the longitudinal direction of the device, the doping concentration in the silicon body is smaller than that on the surface, which is beneficial to the expansion of the space charge area in the body to one side of the gradual doping area. The invention improves the sensitivity of the breakdown voltage of the terminal area to charge imbalance and improves the voltage endurance of the terminal.
Description
Technical Field
The invention belongs to the technical field of power semiconductors, and particularly relates to a super junction power device terminal structure and a preparation method thereof.
Background
The power semiconductor device is a semiconductor device for power processing, and combines a microelectronic technology and a power electronic technology to form the foundation and the core of the power electronic technology. The main development of power devices has been along both frequency and power enhancement. The super junction device is an important power device in the medium-high voltage field, the basic structure of the super junction device is composed of p columns and n columns which are alternately arranged, and the p columns and the n columns follow the basic principle of charge balance. The proposed structure breaks through the "silicon limit" and thus becomes a significant milestone in the power device development history. The super junction MOSFET is widely used in a power system by introducing a super junction structure in a drift region of a conventional power MOSFET because it significantly improves a trade-off relationship between a breakdown voltage and an on-resistance in the power MOSFET. Under the blocking state of the device, the p column and the n column in the super junction structure are completely depleted, and under the modulation of the transverse electric field of the drift region, the longitudinal electric field of the device tends to be uniformly distributed. Therefore, the p column and the n column in the super junction structure are completely depleted, the drift region is equivalent to an intrinsic layer, and theoretically, the breakdown voltage (withstand voltage capability) of the super junction device only depends on the thickness of the drift region and is not related to the doping concentration of the drift region. Therefore, under the same breakdown voltage, the doping concentration of the drift region can be properly increased, and the on-resistance of the device is effectively reduced.
In the practical application process, the electric field intensity is increased due to the fact that the pn junction bends in the terminal region of the device (namely, the electric field is concentrated near the junction), fixed charges are introduced into the surface of the device in the process, so that the breakdown voltage is influenced, and the actual breakdown voltage of the device is lower than that of the ideal plane pn junction. Therefore, the design of the terminal structure of the device is always a key technology for improving the breakdown voltage of the device. High voltage termination structures have been developed including electric field confinement ring techniques, field plate techniques, surface shaping techniques, and the like. The electric field limiting ring technology improves the breakdown voltage of the device by reducing the surface electric field at the main junction, the preparation process is compatible with the cell manufacturing, redundant process steps are not required to be added, and the terminal area of the electric field limiting ring structure occupies a larger area. For this reason, researchers have proposed many improved structures on the basis of the electric field limiting ring, such as a lightly doped field limiting ring having a P + offset region, a shallow trench field limiting ring, a 3D RESURF field limiting ring, and the like. In 1977, a JTE (junction Termination extension) structure was proposed by Temple, which is a method for obtaining a lightly doped P-type region by performing ion implantation near a heavily doped main junction, but actually JTE requires precise control of ion implantation dose. For the purpose of reducing sensitivity to implantation dose, in 1985 r.stenl et al proposed a Lateral Varied Doping (VLD) termination structure, VLD was implanted at one time by gradually reducing mask window password ions, and then annealed to form a controlled graded impurity distribution region. Compared with a field limiting ring structure, the VLD terminal structure can occupy a smaller terminal area and obtain higher planar junction breakdown voltage at the same time, so that the breakdown voltage of the terminal is improved.
Because the super junction device has a special cellular structure and a special manufacturing process, and has the characteristics of small drift region thickness and high doping concentration, the terminal structure of the common high-voltage power device cannot be suitable for the super junction device. The terminal structure of the super junction device which is widely applied at present is the same as the cellular structure of the super junction device, p columns and n columns are alternately arranged, and the basic principle of charge balance is also followed. However, the breakdown voltage of the super junction device is very sensitive to charge imbalance, and the process deviations such as the width, the spacing, the concentration and the like of the doped columns in the terminal region may cause the electric field on the surface of the terminal to be increased, so that the phenomenon that the terminal of the device is broken down in advance and damaged occurs. In summary, the conventional terminal structure not only has a large difficulty in the manufacturing process, but also has a large influence on the reliability of the terminal due to the unbalanced charge, so that it is necessary to develop a super junction power device terminal structure which can reduce the influence of the unbalanced charge and is simple to manufacture.
Disclosure of Invention
In view of the above, the present invention provides a super junction power device terminal structure, which aims at the problems that the reliability of the conventional super terminal structure is greatly affected by charge imbalance and the manufacturing difficulty is high, by arranging a plurality of graded doping regions with sequentially decreasing doping concentrations and being transversely arranged in an epitaxial layer of a terminal region from top to bottom, and sequentially decreasing the doping concentrations of the graded doping regions from top to bottom along the transverse extension depth of the device, and sequentially decreasing the doping concentrations of the graded doping regions from top to bottom along the positions with the same transverse extension depth of the device. Therefore, the sensitivity of the breakdown voltage of the terminal area to charge imbalance is improved, and the voltage withstanding capability of the terminal is improved; in addition, the invention also provides a preparation method of the terminal structure, the preparation process is simple and controllable, the compatibility is strong, and the realization of industrial production is facilitated.
In order to achieve the purpose, the invention adopts the following technical scheme:
the invention provides a super junction power device terminal structure, which comprises a first conductive type semiconductor substrate 1 and a first conductive type semiconductor epitaxial layer 2 positioned on the upper surface of the first conductive type semiconductor substrate 1; first conductivity type semiconductor stop ring 3 is provided with to 2 top layers one end of first conductivity type semiconductor epitaxial layer, its characterized in that: the other end of the top layer of the first conductive type semiconductor epitaxial layer 2 is provided with a plurality of layers of second conductive type semiconductor gradient doped regions 4 from top to bottom, the plurality of layers of second conductive type semiconductor gradient doped regions 4 are sequentially decreased from top to bottom along the extension depth of the device in the transverse direction, the doping concentration of the second conductive type semiconductor gradient doped regions 4 is sequentially decreased along with the decrease of the transverse distance from the first conductive type semiconductor stop ring 3, and the doping concentration of the positions, at which the vertical distances between the plurality of layers of second conductive type semiconductor gradient doped regions 4 and the first conductive type semiconductor stop ring 3 are the same, is sequentially decreased from top to bottom; by adjusting the doping distribution of the multi-layer second conductive type semiconductor gradient doping area 4, the multi-layer second conductive type semiconductor gradient doping area 4 is completely depleted when the reverse withstand voltage reaches the breakdown voltage.
Further, any two adjacent second conductivity type semiconductor graded doping regions 4 are in contact with each other or are isolated by the first conductivity type semiconductor epitaxial layer 2.
Furthermore, in the present invention, each second conductive type semiconductor graded doping region 4 has a first conductive type semiconductor graded doping adjusting region 5 inside, and the doping concentration of the first conductive type semiconductor graded doping adjusting region 5 is less than the doping concentration of the corresponding second conductive type semiconductor graded doping region 4.
Further, the first conductivity type semiconductor is an N-type semiconductor, and the second conductivity type semiconductor is a P-type semiconductor, so that the terminal structure is used as a terminal structure of the N-channel super junction device; or the first conductivity type semiconductor is a P-type semiconductor and the second conductivity type semiconductor is an N-type semiconductor, so that the terminal structure is used as a terminal structure of the P-channel super junction device.
On the other hand, the invention provides a preparation method of a super junction power device terminal structure, which is characterized by comprising the following steps:
selecting a first conductive type semiconductor substrate 1, and epitaxially growing a first conductive type semiconductor epitaxial layer 2 on the first conductive type semiconductor substrate 1; using a mask plate on the first conductive type semiconductor epitaxial layer 2 of the terminal region, wherein the mask plate comprises a plurality of windows, and injecting second conductive type semiconductor impurity ions into the first conductive type semiconductor epitaxial layer 2 through the windows of the mask plate to form a doped region; repeating the steps, reasonably adjusting the number and size of the windows of the mask plate, the ion implantation energy and dosage through multiple times of epitaxy and ion implantation, and finally forming a plurality of layers of second conductive type semiconductor gradient doped regions 4 on the top layer of the first conductive type semiconductor epitaxial layer 2 from top to bottom through an annealing process; the extension depth of the multiple layers of second conductive type semiconductor gradient doped regions 4 along the transverse direction of the device is sequentially reduced from top to bottom, the doping concentration of each layer of second conductive type semiconductor gradient doped region 4 is gradually reduced along with the transverse extension of the second conductive type semiconductor gradient doped region, and the doping concentration of the second conductive type semiconductor gradient doped regions 4 with the same transverse extension depth is sequentially reduced from the surface of the device to the inside of the device; and finally, forming a first conductive type semiconductor stop ring 3 at the other end of the top layer of the first conductive type semiconductor epitaxial layer 2 by using a mask plate through ion implantation and annealing process.
Compared with the prior art, the invention has the beneficial effects that:
according to the invention, the gradient doped region of the multilayer structure is designed in the epitaxial layer of the terminal region of the super junction power device, so that a three-dimensional gradient doped terminal structure with gradient concentration and gradient depth along the transverse direction of the device is formed in the transverse direction and the longitudinal direction of the device. The super-junction device improves the sensitivity of the breakdown voltage of the terminal area to charge imbalance, reduces the process difficulty of manufacturing the terminal structure and improves the reliability of the terminal structure while not influencing the electrical performance of the super-junction device.
Drawings
Fig. 1 is a schematic diagram of a terminal structure of a super junction power device provided in embodiment 1 of the present invention;
fig. 2 is a schematic diagram of transverse and longitudinal concentration distributions of a super junction power device termination structure provided in embodiment 1 of the present invention;
fig. 3 is a schematic diagram of a terminal structure of a super junction power device of embodiment 2 provided in embodiment 2 of the present invention;
fig. 4 is a schematic diagram of a terminal structure of a super junction power device of embodiment 3 provided in embodiment 3 of the present invention;
fig. 5 is an application example of the terminal structure of the super junction power device in the super junction planar gate device.
Fig. 6 to fig. 14 are schematic structural diagrams of a process manufacturing flow of a termination structure of a super junction power device provided in this embodiment 5.
In the figure, 1 is a first conductive type semiconductor substrate, 2 is a first conductive type semiconductor epitaxial layer, 3 is a stop ring, 41 is a first second conductive type semiconductor gradient doping area, 42 is a second conductive type semiconductor gradient doping area, 43 is a third second conductive type semiconductor gradient doping area, 4n is a second conductive type semiconductor gradient doping area n, 51 is a first conductive type semiconductor gradient doping adjusting area, 52 is a second first conductive type semiconductor gradient doping adjusting area, 53 is a third first conductive type semiconductor gradient doping adjusting area, 5n is a first conductive type semiconductor gradient doping adjusting area n, 6 is a second conductive type semiconductor column area, 7 is a second conductive type semiconductor body area, 8 is a first conductive type semiconductor heavy doping source area, 9 is a gate oxide layer, and 10 is a polysilicon gate.
Detailed Description
In order to make the content and principle of the present invention clearer, the following detailed description of the technical solution of the present invention is made with reference to the accompanying drawings and the specific embodiments.
Example 1:
the present embodiment provides a super junction power device termination structure as shown in fig. 1, including a first conductivity type semiconductor substrate 1 and a first conductivity type semiconductor epitaxial layer 2 located on the upper surface of the first conductivity type semiconductor substrate 1; one end of the top layer of the first conductive type semiconductor epitaxial layer 2 is provided with a heavily doped first conductive type semiconductor stopping ring 3, and the semiconductor epitaxial growth device is characterized in that: the other end of the top layer of the first conductive type semiconductor epitaxial layer 2 is sequentially provided with a first conductive type semiconductor gradient doped region 41, a second conductive type semiconductor gradient doped region 42 and a third conductive type semiconductor gradient doped region 43 … … from top to bottom, and a second conductive type semiconductor gradient doped region 4 n; the n second conductive type semiconductor graded doping regions 41, 42, 43 … … 4n are sequentially decreased from top to bottom along the extension depth of the device transverse direction, the doping concentrations of the n second conductive type semiconductor graded doping regions are sequentially decreased along with the decrease of the transverse distance from the first conductive type semiconductor stopping ring 3, and the doping concentrations of the n second conductive type semiconductor graded doping regions 41, 42, 43 … … 4n and the position with the same vertical distance from the first conductive type semiconductor stopping ring 3 are sequentially decreased from top to bottom; by adjusting the doping distribution of the n second-conductivity-type semiconductor graded doping regions 41, 42, 43 … … 4n, when the reverse withstand voltage applied to the termination structure reaches the breakdown voltage, the n second-conductivity-type semiconductor graded doping regions 41, 42, 43 … … 4n are completely depleted.
The principle is further explained by taking the terminal structure of the N-channel super junction power device as an example and combining with embodiment 1, and those skilled in the art can obtain the principle of the terminal structure of the N-channel super junction power device according to the following disclosure.
The traditional super junction power device terminal structure adopts a p column and n column alternate arrangement mode to achieve rated breakdown voltage, however, as the breakdown voltage is sensitive to charge balance, slight deviations of the process such as the width, the distance, the doping concentration and the like of the p column in the terminal area can cause charge imbalance, so that the electric field on the surface of the terminal structure is increased, and the phenomenon that the device terminal structure is broken down in advance and damaged occurs. It is also because the breakdown voltage is sensitive to charge balance, so that the requirement of the conventional super junction power device termination structure on the process level is very high, and the reliability of the termination structure is also limited due to the charge imbalance effect. Therefore, in the invention, N layers of P-type gradient doped regions 41, 42, 43 … … 4N are arranged in the N-type epitaxial layer 2 of the super junction device termination region, the N layers of P-type gradient doped regions are in gradient doping in the transverse direction and the longitudinal direction of the device, and the extension depth along the transverse direction of the device is gradually changed, so that a three-dimensional gradient structure is formed. The doping concentrations of the n layers of P-type gradually-changed doping regions 41, 42 and 43 … … 4n are gradually reduced from left to right on the same horizontal line, and the doping concentrations of the n layers of P-type gradually-changed doping regions 41, 42 and 43 … … 4n are gradually reduced from top to bottom on the same vertical line; and the extension depth of the n-layer P-type graded doping regions 41, 42, 43 … … 4n along the transverse direction of the device is gradually reduced from top to bottom. The concentration distribution diagram of the three-dimensional gradient structure is shown in FIG. 2, AA 'represents the transverse direction (from the transition region to the terminal region), BB' represents the longitudinal direction (from the silicon surface to the body), and the surface doping concentration is the lowest in the direction close to the channel stop ring 3 in the transverse direction, so that the electric field peak value of the junction edge is effectively reduced; furthermore, the extension depth of the P-type gradient doped region from the inside of the device to the surface along the transverse direction of the device is gradually increased, so that the boundary of the surface depletion layer is widened to one side of the stop ring 3, and the influence of the curvature effect of the junction edge on the breakdown voltage is favorably relieved; in the longitudinal direction, the doping concentration in the semiconductor body at the same vertical distance with the stop ring 3 is smaller than that of the semiconductor surface, so that the extension of the space charge region in the semiconductor body to one side of the gradual-change doping region is facilitated. When the reverse withstand voltage applied to the termination structure approaches the breakdown voltage, the n-layer P-type graded doped regions 41, 42, 43 … … 4n will be fully depleted, forming a large depletion region to withstand the higher reverse withstand voltage. Compared with the traditional super junction device terminal structure with alternately arranged p columns and n columns, the super junction power terminal with three-dimensional gradient doping provided by the invention relieves the influence of charge imbalance caused by process deviation on breakdown voltage. Therefore, the three-dimensional gradient terminal structure provided by the invention improves the sensitivity of the breakdown voltage of the terminal area to charge imbalance and improves the withstand voltage of the terminal without affecting the electrical performance of the super junction device.
Example 2:
the difference between the embodiment of the present invention and embodiment 1 is that n second conductivity type semiconductor graded doping regions 41, 42, 43 … … 4n in contact with each other are replaced by n second conductivity type semiconductor graded doping regions 41, 42, 43 … … 4n which are isolated from each other, i.e. a termination structure having discontinuous graded doping regions as shown in fig. 3 is provided. In this embodiment, the first conductive type semiconductor epitaxial layer 2 is provided between any two adjacent second conductive type semiconductor graded doped regions, and the rest of the structure is the same as that of embodiment 1.
As in embodiment 1, the doping concentrations of the n second conductivity type semiconductor graded doping regions 41, 42, 43 … … 4n which are isolated from each other are gradually reduced from left to right on the same horizontal line, and the graded doping can be realized by controlling the ion implantation window.
Example 3:
this embodiment provides a terminal structure of two times of ion implantation as shown in fig. 4, by introducing a plurality of graded doping adjustment regions 51, 52, 53 … … 5n of first conductivity type semiconductor inside a plurality of graded doping regions 41, 42, 43 … … 4n of second conductivity type semiconductor which are in contact with each other, the rest of the structure is the same as that of embodiment 1.
Each of the second-conductivity-type semiconductor graded doping regions 41, 42, 43 … … 4n is formed by a single epitaxial growth and ion implantation, followed by thermal diffusion through an annealing process, and this embodiment also requires an additional single ion implantation step, so that the first-conductivity-type semiconductor impurity is doped into each of the second-conductivity-type semiconductor graded doping regions, and the first-conductivity-type semiconductor doping adjustment regions 51, 52, 53 … … 5n are formed through thermal diffusion through an annealing process. Compared with embodiment 1, the doping concentration of the structure after two times of implantation can be well adjusted, and the flexibility of device design is increased while the process complexity and cost are not increased.
Example 4:
the present invention can be used as a terminal structure of many kinds of super junction power devices, and this embodiment provides an application example of a planar gate super junction device, as shown in fig. 5, which includes a first conductivity type semiconductor substrate 1 and a first conductivity type semiconductor epitaxial layer 2 disposed on the first conductivity type semiconductor substrate 1, where the first conductivity type semiconductor epitaxial layer 2 includes an active region (i.e., a cell region) and a terminal region, where the structure of the terminal region is the structure provided in this embodiment 1, and the active region includes: the structure of the semiconductor device comprises a first conductive type semiconductor substrate 1, a first conductive type semiconductor epitaxial layer 2, a second conductive type semiconductor column region 6, a second conductive type semiconductor body region 7, a first conductive type semiconductor heavily doped source region 8, a gate oxide layer 9 and a polysilicon gate 10, wherein the active region is set in the prior art, and the detailed description of the embodiment is omitted.
Example 5:
the present embodiment provides a process manufacturing flow of a super junction power device terminal structure, which is described in embodiment 1 (taking a terminal structure of an N-channel super junction device as an example), and the specific process steps are as follows:
the first step is as follows: monocrystalline silicon substrate preparation and epitaxial layer growth:
as shown in fig. 6, an N-type heavily doped single crystal silicon substrate 1 is used, and an N-type epitaxial layer 2 having a certain thickness and doping concentration is vapor phase epitaxially grown on the upper surface of the substrate.
The second step is that: ion implantation:
as shown in fig. 7, a mask is used on the surface of the N-type epitaxial layer 2, P-type impurity ions are implanted into the left side of the top layer of the N-type epitaxial layer 2, and the size of a mask window, the energy and the dose of the ion implantation can be adjusted according to the requirements;
the third step: secondary epitaxial growth and ion implantation:
as shown in fig. 8, the steps of growing epitaxy and implanting P-type impurities in the two steps are repeated, the size of the mask window and the energy and dose of ion implantation can be adjusted as required, it is ensured that the P-type doped region formed in the step after annealing is laterally graded doped, the doping concentration of the P-type doped region is sequentially reduced from left to right, the extension depth of the P-type doped region along the lateral direction of the device is larger than that of the P-type doped region formed in the second step, and the doping concentration of the P-type impurities at the same position along the lateral extension depth of the device is higher than that of the P-type doped region formed in the second step;
the fourth step: multiple times of epitaxial growth and ion implantation:
as shown in fig. 9 to 12, the third step is repeated for a plurality of times, each time of epitaxial growth is followed by ion implantation, the size of the mask window and the energy and dose of the ion implantation can be adjusted as required, it is ensured that the P-type doped region formed in the step after annealing is not only laterally graded doped, but also has a greater extension depth along the lateral direction of the device than the P-type doped region formed in the second step, the P-type impurity doping concentration at the same position along the lateral direction of the device is higher than the P-type doped region formed in the second step, and finally, a plurality of layers of P-type graded doped regions 41, 42, 43 … … 4n are formed;
the fifth step: high-temperature annealing:
as shown in fig. 13, the silicon wafer after multiple epitaxial growth and ion implantation is annealed at high temperature, so that the discontinuous P-type region tends to be continuous and the concentration distribution is more uniform while the impurities are activated, thereby forming a terminal structure with gradually-changed doping in both the transverse direction and the longitudinal direction;
the fifth step: forming the channel stopper ring 3:
as shown in fig. 14, N-type impurities with low dose and high dose are ion-implanted using a mask, and a channel stopper ring 3 is formed at one end of the upper layer of the N-type epitaxial layer 2 after rapid thermal annealing. This step may be formed together with the N + source contact region of the cell region.
The process manufacturing process of the super junction power device terminal structure provided by the invention is compatible with the process of the super junction device cell, the three-dimensional gradient doped structure in the terminal area can be formed together with the doped column area of the cell area, and the channel stop ring 3 can be formed together with the cell source contact area. The manufacturing process is compatible with the existing cellular area manufacturing process, additional process steps are not needed, and the process difficulty of terminal manufacturing is reduced.
While the present invention has been particularly shown and described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (7)
1. A terminal structure of a super junction power device comprises a first conduction type semiconductor substrate (1) and a first conduction type semiconductor epitaxial layer (2) located on the upper surface of the first conduction type semiconductor substrate (1); first conductivity type semiconductor stop ring (3) is provided with to first conductivity type semiconductor epitaxial layer (2) top layer one end, its characterized in that: the other end of the top layer of the first conductive type semiconductor epitaxial layer (2) is provided with a plurality of layers of second conductive type semiconductor gradient doped regions from top to bottom, the plurality of layers of second conductive type semiconductor gradient doped regions are sequentially decreased from top to bottom along the extension depth of the device in the transverse direction, the doping concentrations of the plurality of layers of second conductive type semiconductor gradient doped regions are sequentially decreased along with the decrease of the transverse distance from the first conductive type semiconductor stop ring (3), and the doping concentrations of the positions, at which the transverse distances between the plurality of layers of second conductive type semiconductor gradient doped regions and the first conductive type semiconductor stop ring (3) are the same, are sequentially decreased from top to bottom; the doping distribution of the multiple layers of second conductive type semiconductor gradient doping areas is adjusted, so that the multiple layers of second conductive type semiconductor gradient doping areas are completely exhausted when the reverse withstand voltage reaches the breakdown voltage, a first conductive type semiconductor gradient doping adjusting area is arranged inside each second conductive type semiconductor gradient doping area, and the doping concentration of the first conductive type semiconductor gradient doping adjusting area is smaller than that of the corresponding second conductive type semiconductor gradient doping area.
2. The termination structure of the super junction power device according to claim 1, wherein any two adjacent second conductivity type semiconductor graded doping regions are in contact with each other or are separated by a first conductivity type semiconductor epitaxial layer (2).
3. The termination structure of claim 1, wherein the first conductivity type semiconductor is an N-type semiconductor and the second conductivity type semiconductor is a P-type semiconductor.
4. The termination structure of claim 1, wherein the first conductivity type semiconductor is a P-type semiconductor and the second conductivity type semiconductor is an N-type semiconductor.
5. A method for preparing a super junction power device terminal structure is characterized by comprising the following steps:
selecting a first conductive type semiconductor substrate (1), and epitaxially growing a first conductive type semiconductor epitaxial layer (2) on the first conductive type semiconductor substrate (1); using a mask plate on a first conductive type semiconductor epitaxial layer (2) of a terminal region, wherein the mask plate comprises a plurality of windows, and injecting second conductive type semiconductor impurity ions into the first conductive type semiconductor epitaxial layer (2) through the mask plate windows to form a doped region; repeating the steps, reasonably adjusting the number and size of the windows of the mask plate, the ion implantation energy and dosage through multiple times of epitaxy and ion implantation, and forming a plurality of layers of second conductivity type semiconductor gradient doped regions on the top layer of the first conductivity type semiconductor epitaxial layer (2) from top to bottom through an annealing process; the extension depth of the multiple layers of second conductive type semiconductor gradient doped regions along the transverse direction of the device is sequentially reduced from top to bottom, the doping concentration of each layer of second conductive type semiconductor gradient doped region is gradually reduced along with the transverse extension of the second conductive type semiconductor gradient doped region, and the doping concentration of the second conductive type semiconductor gradient doped regions with the same transverse extension depth is sequentially reduced from the surface of the device to the inside of the device; and finally, forming a first conductive type semiconductor stopping ring (3) at the other end of the top layer of the first conductive type semiconductor epitaxial layer (2) by using a mask plate through ion implantation and annealing process, wherein a first conductive type semiconductor gradient doping adjusting region is arranged in each second conductive type semiconductor gradient doping region, and the doping concentration of the first conductive type semiconductor gradient doping adjusting region is smaller than that of the corresponding second conductive type semiconductor gradient doping region.
6. The method for manufacturing a termination structure of a super junction power device according to claim 5, wherein the first conductivity type semiconductor is an N-type semiconductor, and the second conductivity type semiconductor is a P-type semiconductor.
7. The method for manufacturing a termination structure of a super junction power device according to claim 5, wherein the first conductivity type semiconductor is a P-type semiconductor and the second conductivity type semiconductor is an N-type semiconductor.
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| CN112820628A (en) * | 2020-12-31 | 2021-05-18 | 广州粤芯半导体技术有限公司 | Method for preparing epitaxial layer |
| CN113078206A (en) * | 2021-03-30 | 2021-07-06 | 电子科技大学 | Power semiconductor device |
| CN113517336A (en) * | 2021-07-13 | 2021-10-19 | 电子科技大学 | Terminal structure of MOS type super junction power device |
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