CN102130013B - Method for manufacturing SOI (silicon on insulator) super junction LDMOS (lateral double-diffused metal oxide semiconductor) device with buffer layer - Google Patents
Method for manufacturing SOI (silicon on insulator) super junction LDMOS (lateral double-diffused metal oxide semiconductor) device with buffer layer Download PDFInfo
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- CN102130013B CN102130013B CN2010106195081A CN201010619508A CN102130013B CN 102130013 B CN102130013 B CN 102130013B CN 2010106195081 A CN2010106195081 A CN 2010106195081A CN 201010619508 A CN201010619508 A CN 201010619508A CN 102130013 B CN102130013 B CN 102130013B
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Abstract
The invention discloses a method for manufacturing an SOI (silicon on insulator) super junction LDMOS (lateral double-diffused metal oxide semiconductor) device with a buffer layer. The method comprises the following steps: firstly implanting N-type ions into top silicon of an SOI substrate to ensure the region below a whole drift region to become an N-type region; secondly implanting shallowly doped N-type ions into the drift region and forming a shallowly doped N-type buffer layer on the surface layer of the drift region; and thirdly implanting P-type ions into the formed N-type region via a layout and forming a plurality of equally spaced lateral P-type column regions in the N-type region to divide the N-type region into a plurality of lateral N-type column regions, wherein the alternately arranged P-type column regions and N-type column regions form a lateral super junction structure. The method has the following beneficial effects: the buffer layer is arranged on the drift region, thus inhibiting the impact of the substrate-assisted depletion effect on the balance of the charges in the SOI super junction LDMOS drift region and improving the breakdown voltage of the device; and by skillfully adjusting the step of implanting N/P ions and designing the layout and ion implantation concentration, the process is further simplified and the production cost is lowered.
Description
Technical field
The present invention relates to a kind of lateral double diffusion metal oxide semiconductor (LDMOS; LateralDouble-diffused MOSFET) manufacture method of device architecture; Especially a kind of manufacture method with SOI super junction LDMOS device of resilient coating belongs to microelectronics and solid-state electronic techniques field.
Background technology
Lateral double diffusion metal oxide semiconductor (LDMOS, Lateral Double-diffused MOSFET) is the key technology of high voltage integrated circuit HVIC (High Voltage Integrated Circuit) and power integrated circuit PIC (Power Integrated Circuit).Be primarily characterized in that to add one section relatively long light dope drift region between channel region and the drain region, this drift region doping type is consistent with drain terminal, through adding the drift region, can play the effect of sharing puncture voltage.
So-called super junction LDMOS is a kind of modified model LDMOS, and promptly the low-doped N type drift region of traditional LDMOST is replaced by one group of N type post district that alternately arranges and P type post district.In theory; If the electric charge between the P/N post district can perfect compensate; The drift region reaches fully and exhausts, and then super junction LDMOS can obtain the puncture voltage higher than traditional LDMOS, and highly doped N type post district then can obtain very low conducting resistance; Therefore, ultra junction device can be obtained a good balance between puncture voltage and two key parameters of conducting resistance.But, owing to the existence of substrate-assisted depletion effect (substrate-assisteddepletion effects), reduced the puncture voltage of super junction LDMOS device.
So-called substrate-assisted depletion effect is meant horizontal ultra knot owing to receive the influence of longitudinal electric field, and the P/N post district of symmetry in the ultra knot can not be exhausted simultaneously fully, and its essence is that the charge balance between the P/N post district is broken.For the SOI substrate; Because the back of the body grid effect of substrate; The electric charge of non-uniform Distribution is accumulated in the upper and lower interface place of oxygen buried layer and silicon under the effect of longitudinal electric field, strengthened the charge difference between the P/N post district, causes P/N post district under the puncture voltage that theory is calculated, to exhaust fully simultaneously.
In order to solve the unbalance problem of P/N post district electric charge that the laterally ultra junction device of SOI brings owing to substrate-assisted depletion effect; It is that one deck resilient coating is introduced in the zone near oxygen buried layer below the drift region that a kind of solution is arranged; Electric charge difference with between the compensation P/N post district reaches the purpose that exhausts fully between the P/N post district.
Yet,, must use thick film SOI (thickness t if from design demand
Si＞1.5um); Can alleviate the laterally substrate-assisted depletion effect of ultra junction device of SOI though then introduce resilient coating, be positioned at owing to resilient coating on the oxygen buried layer of below, drift region, when carrying out the ion injection; Reach the injection degree of depth like this; It is very big not only to inject energy, and will accurately control its Impurity Distribution, and technology realizes very difficulty.
Given this, the present invention proposes a kind of novel SOI super junction LDMOS device manufacture method, through the position and the making step of change resilient coating, thereby reduces its technology difficulty greatly.
Summary of the invention
The technical problem that the present invention will solve is to provide a kind of manufacture method with SOI super junction LDMOS device of resilient coating, can alleviate the laterally substrate-assisted depletion effect of ultra junction device of SOI, and can reduce its technology difficulty greatly.
In order to solve the problems of the technologies described above, the present invention adopts following technical scheme:
A kind of manufacture method with SOI super junction LDMOS device of resilient coating may further comprise the steps:
(A) adopt the SOI substrate, its top layer silicon is carried out N type ion inject, make below, whole drift region become N type zone;
(B) shallow doped N-type ion is carried out in said drift region and inject, form shallow doped N-type resilient coating on the top layer of drift region;
(C) the N type zone that through domain step (A) is formed is carried out P type ion and is injected; In said N type zone, form equally spaced a plurality of transverse P-type posts district; Said a plurality of transverse P-type posts district is a plurality of horizontal N type posts districts with said N type area dividing, and the P type post district and the N type post district of alternately arranging each other form horizontal super-junction structure;
(D) utilize shallow trench isolation to leave the fabrication techniques groove isolation construction, the part silicon materials that will comprise the drift region isolate out;
(E) utilize repeatedly the ion injection mode that the part except that the drift region in the said part silicon materials is mixed, form the P trap body area;
(F) end near the drift region is produced the grid region on the P trap body area;
(G) in a side in said grid region, be infused in organizator contact zone and source region on the P trap body area through ion;
(H), be infused in through ion that the end away from the grid region forms the drain region on the horizontal super-junction structure, thereby obtain the core texture of LDMOS device at the opposite side in said grid region.
As preferred version of the present invention, step (A) adopts the phosphonium ion injection to inject as N type ion.
As preferred version of the present invention; Step (B) is carried out injection energy that shallow doped N-type ion injects and implantation dosage and is as the criterion with the actual needs that shallow doped N-type resilient coating is used to compensate the unnecessary electric charge that substrate-assisted depletion effect brings, and confirms through device is carried out emulation.
As preferred version of the present invention, step (B) adopts shallow Doping Phosphorus ion to inject as shallow doped N-type ion injection, injects energy＜50kev, and implantation dosage is 1 * 10
15Cm
-3～7 * 10
15Cm
-3
As preferred version of the present invention, the doping content that step (C) is carried out the injection of P type ion is 2 times that step (A) is carried out N type ion implantation doping concentration.
As preferred version of the present invention, step (C) equates the P type post district of formation and N type post sector width through regulating territory pattern.
As preferred version of the present invention, step (C) adopts the injection of boron ion to inject as P type ion.
As preferred version of the present invention; When step (F) is made the grid region; Prepare one deck gate dielectric material earlier; On said gate dielectric material, prepare grid material again, produce the grid region through photoetching end near said drift region on said P trap body area then, make said grid region comprise gate dielectric material and grid material.
Further preferably, utilize thermal oxidation method to form said gate dielectric material.
Further preferably, said grid material is a polycrystalline silicon material.
Beneficial effect of the present invention is:
The present invention is on the basis of using for reference traditional super junction LDMOS resilient coating; Through changing the position of resilient coating; It is shifted in drift region surface, can plays the effect of the unnecessary electric charge that the compensation substrate-assisted depletion effect brings equally, the electric charge of drift region, top resilient coating is through from top to bottom progressively displacement; Can compensate the unnecessary electric charge of oxygen buried layer top accumulation; As shown in Figure 1, and then can alleviate the influence of substrate-assisted depletion effect to SOI LDMOS drift region charge balance, improve the puncture voltage of device.
Resilient coating is owing to be in the top, drift region, and doping depth significantly shoals during making, has not only reduced the injection energy of impurity; And realize the even distribution of drift region impurity more easily; Technology difficulty reduces greatly, and through adjusting the step that the N/P ion injects dexterously, territory pattern that design is fit to and ion implantation concentration etc.; Can further simplify technology, reduce production costs.
Description of drawings
Fig. 1 is for having the principle schematic of the SOI super junction LDMOS device of resilient coating among the embodiment;
Fig. 2 is for having the schematic three dimensional views of the SOI super junction LDMOS device of resilient coating among the embodiment;
Fig. 3 is the domain of drift region P/N type post district and resilient coating among the embodiment;
Fig. 4 is for having the final packaging structural representation of the SOI LDMOS device of resilient coating among the embodiment.
Wherein each description of reference numerals is following:
10, the bottom semiconductor of SOI substrate
11, the insulating buried layer of SOI substrate
21, gate material layer
22, gate dielectric layer
23, source region
24, drain region
25, tagma
26, horizontal super-junction structure
261, P type post district
262, N type post district
27, resilient coating
28, body contact zone
31, source electrode
32, grid
33, drain electrode
Embodiment
Further specify the present invention below in conjunction with accompanying drawing, for the accompanying drawing that makes things convenient for that illustrates is not proportionally drawn.
Through the further investigation to the super junction LDMOS device that adopts SOI (Silicon On Insulator) substrate, inventor of the present invention finds to be provided with on the top layer, drift region the effect that resilient coating can play the unnecessary electric charge that the compensation substrate-assisted depletion effect brings.As shown in Figure 1; The electric charge (electronics shown in the figure) of drift region, top resilient coating can be through from top to bottom progressively displacement; Thereby the unnecessary electric charge (hole shown in the figure) of compensation insulating buried layer top accumulation; And then can eliminate the influence that substrate-assisted depletion effect distributes to SOI LDMOS drift region charge, improve the puncture voltage of device.Therefore, the inventor has proposed this SOI LDMOS device that is provided with resilient coating on the top layer, drift region.
Fig. 2 is the structural representation of a preferred embodiment of this kind SOI super junction LDMOS device.This SOI super junction LDMOS device comprises the SOI substrate and is positioned at the active area on the said SOI substrate; The SOI substrate is made up of bottom semiconductor 10, insulating buried layer 11 and top layer silicon; Said active area comprises: grid region, the source region 23 that lays respectively at both sides, said grid region and drain region 24, the drift region in the tagma under the said grid region 25, between said tagma 25 and said drain region 24; Said drift region comprises horizontal super-junction structure 26 and the resilient coating 27 that is positioned at said horizontal super-junction structure 26 tops.Said grid region comprises gate dielectric layer 22 and is positioned at the gate material layer 21 on the gate dielectric layer 22.Said horizontal super-junction structure 26 comprises the P type post district 261 and N type post district 262 of laterally alternately arranging, and is used to share puncture voltage.The N type resilient coating that said resilient coating 27 is shallow doping can compensate the unnecessary electric charge that substrate-assisted depletion effect brings.In the present embodiment preferably; Said resilient coating 27 is arranged at the top layer of said drift region, and when adopting the method for mixing to make resilient coating 27 like this, doping depth significantly shoals; Not only reduce the injection energy of impurity, and realized the even distribution of drift region impurity more easily.
In addition, because employing is the SOI substrate, this SOI super junction LDMOS device also comprises body contact zone 28, and said body contact zone 28 is positioned at 23 sides, said source region, contacts with said tagma 25, is used to draw the unnecessary electric charge that assemble in tagma 25, avoids floater effect.
When preparing above-mentioned SOI super junction LDMOS device; The inventor finds to adopt the sequence of steps of routine to carry out the ion injection, needs to adopt a plurality of domains to carry out N type ion injects and the injection of P type ion is alternately arranged with formation N type post district 262 and P type post district 261 respectively, and then carries out the N type resilient coating 27 of the shallow doping of N type ion injection formation of low energy; The complicated steps of whole making drift region; Domain switches loaded down with trivial details, expends more manpower and materials, and production cost is higher.Therefore; The inventor improves and adjusts this manufacture craft; At first utilizing ion implantation device to carry out N type ion injects; Employing forms N type post district 262 required injection energy and dopant doses and forms a N type zone in the doping of whole drift region, continues to utilize this domain then, only need adjust injection energy and dopant dose and can above N type zone, form resilient coating 27; Switch a domain afterwards again and carry out the injection of P type ion, thereby energy is injected in adjustment and dopant dose forms required horizontal super-junction structure 26.This method not only can be saved domain with respect to conventional method, has simplified technology, and promptly resilient coating and N post district share a domain, and P/N post regional boundary face dopant profiles is even more ideal with respect to conventional method simultaneously.
The detailed process of this manufacture method is following:
(1) adopts SO I substrate, its top layer silicon is carried out N type ion inject, make below, whole drift region become N type zone.Wherein, the injection energy and the dopant dose that are adopted in the time of can adopting conventional method to form N type post district 262.For example, adopting phosphonium ion to inject injects as N type ion.Can divide and carry out the phosphorus injection for three times, inject energy 75kev, implantation dosage 5.2 * 10 for the first time
12Cm
-2Inject for the second time energy 180kev, implantation dosage 5.8 * 10
12Cm
-2Inject energy 350kev for the third time, implantation dosage 6.4 * 10
12Cm
-2
(2) shallow doped N-type ion is carried out in said drift region and inject, form shallow doped N-type resilient coating 27 on the top layer of drift region.For example can adopt the shallow Doping Phosphorus ion of low energy to inject as shallow doped N-type ion injects.Inject energy and implantation dosage and be as the criterion, confirm through device is carried out emulation with the actual needs that shallow doped N-type resilient coating is used to compensate the unnecessary electric charge that substrate-assisted depletion effect brings.Generally speaking, inject energy＜50kev, implantation dosage is 1 * 10
15Cm
-3～7 * 10
15Cm
-3
(3) the N type zone that through domain step (A) is formed is carried out P type ion and is injected; In said N type zone, form equally spaced a plurality of transverse P-type posts district 261; Said a plurality of transverse P-type posts district 261 is a plurality of horizontal N type posts district 262 with said N type area dividing; P type post district 261 of alternately arranging each other and N type post district 262 form horizontal super-junction structure 26, and be as shown in Figure 3.To make the doping content of P type ion injection be 2 times of step (1) N type ion implantation doping concentration through regulate injecting energy and dosage.For example, adopt the boron ion to inject and inject, can divide three injections, inject energy 100kev, implantation dosage 7.5 * 10 for the first time as P type ion
12Cm
-2Inject for the second time energy 150kev, implantation dosage 8.5 * 10
12Cm
-2Inject energy 200kev for the third time, implantation dosage 9.5 * 10
12Cm
-2Through regulating territory pattern the P type post district 261 of formation and N type post district 262 width are equated.
(4) utilize shallow trench isolation to leave (STI) fabrication techniques groove isolation construction, the part silicon materials that will comprise the drift region isolate out, and these part silicon materials are used for the active area of fabricate devices.
(5) form one deck gate oxidation material at above-mentioned segregate part silicon materials surface by utilizing thermal oxidation method.
(6) utilize repeatedly the ion injection mode that the part except that the drift region in the said part silicon materials is mixed, form the tagma 25 of P trap.
(7) deposit polysilicon, doping form the polysilicon gate material on the gate oxidation material, and produce the grid region through photoetching end near horizontal super-junction structure 26 on P trap body area 25.The grid region is made up of gate dielectric layer 22 (gate oxidation material) and gate material layer 21 (polysilicon gate material).
(8) in a side in said grid region, be infused in organizator contact zone 28 and source region 23 on the P trap body area 25 through ion.
(9) at the opposite side in said grid region, be infused in through ion that the end away from the grid region forms drain region 24 on the horizontal super-junction structure 26, thereby accomplish the making of active area, obtain the core texture of device.
Wherein, make tagma 25, grid region, source region 23, body contact zone 28 and drain region 24 and adopt conventional semiconductor technologies such as ion injection, etching, present embodiment only is a kind of preferred step method, and other variation also can be arranged when specifically making.Vertically arrange in the grid region and the drain region 24 that make, and laterally super-junction structure 26 is made up of N type post district of laterally alternately arranging 262 and P type post district 261.
(10) adopt LTO (low temperature silicon dioxide) mode growthing silica, cover whole active area.
(11) on said silicon dioxide, etch window, depositing metal then, grid 32, source electrode 31, drain electrode 33 are drawn in photoetching.Source electrode 31 is located on body contact zone 28 and source region 23 intersections.
(12) last deposit silicon nitride generates passivation layer.
The device that obtains at last is as shown in Figure 4.
The other technologies that relate among the present invention belong to the category that those skilled in the art are familiar with, and repeat no more at this.The foregoing description is the unrestricted technical scheme of the present invention in order to explanation only.Any technical scheme that does not break away from spirit and scope of the invention all should be encompassed in the middle of the patent claim of the present invention.
Claims (10)
1. the manufacture method with SOI super junction LDMOS device of resilient coating is characterized in that, may further comprise the steps:
(A) adopt the SOI substrate, its top layer silicon is carried out N type ion inject, make below, whole drift region become N type zone;
(B) shallow doped N-type ion is carried out in said drift region and inject, form shallow doped N-type resilient coating on the top layer of drift region;
(C) the N type zone that through domain step (A) is formed is carried out P type ion and is injected; In said N type zone, form equally spaced a plurality of transverse P-type posts district; Said a plurality of transverse P-type posts district is a plurality of horizontal N type posts districts with said N type area dividing, and the P type post district and the N type post district of alternately arranging each other form horizontal super-junction structure;
(D) utilize shallow trench isolation to leave the fabrication techniques groove isolation construction, the part silicon materials that will comprise the drift region isolate out;
(E) utilize repeatedly the ion injection mode that the part except that the drift region in the said part silicon materials is mixed, form the P trap body area;
(F) end near the drift region is produced the grid region on the P trap body area;
(G) in a side in said grid region, be infused in organizator contact zone and source region on the P trap body area through ion;
(H), be infused in through ion that the end away from the grid region forms the drain region on the horizontal super-junction structure, thereby obtain the core texture of LDMOS device at the opposite side in said grid region.
2. according to the said manufacture method with SOI super junction LDMOS device of resilient coating of claim 1, it is characterized in that: step (A) adopts the phosphonium ion injection to inject as N type ion.
3. according to the said manufacture method of claim 1 with SOI super junction LDMOS device of resilient coating; It is characterized in that: step (B) is carried out injection energy that shallow doped N-type ion injects and implantation dosage and is as the criterion with the actual needs that shallow doped N-type resilient coating is used to compensate the unnecessary electric charge that substrate-assisted depletion effect brings, and confirms through device is carried out emulation.
4. according to claim 1 or 3 said manufacture methods with SOI super junction LDMOS device of resilient coating, it is characterized in that: step (B) adopts shallow Doping Phosphorus ion to inject as shallow doped N-type ion injection, injects energy＜50kev, and implantation dosage is 1 * 10
15Cm
-3～7 * 10
15Cm
-3
5. according to the said manufacture method with SOI super junction LDMOS device of resilient coating of claim 1, it is characterized in that: the doping content that step (C) is carried out the injection of P type ion is 2 times that step (A) is carried out N type ion implantation doping concentration.
6. according to the said manufacture method with SOI super junction LDMOS device of resilient coating of claim 1, it is characterized in that: step (C) equates the P type post district of formation and N type post sector width through regulating territory pattern.
7. according to the said manufacture method with SOI super junction LDMOS device of resilient coating of claim 1, it is characterized in that: step (C) adopts the injection of boron ion to inject as P type ion.
8. according to the said manufacture method of claim 1 with SOI super junction LDMOS device of resilient coating; It is characterized in that: when step (F) is made the grid region; Prepare one deck gate dielectric material earlier; On said gate dielectric material, prepare grid material again, produce the grid region through photoetching end near said drift region on said P trap body area then, make said grid region comprise gate dielectric material and grid material.
9. the said according to Claim 8 manufacture method with SOI super junction LDMOS device of resilient coating is characterized in that: utilize thermal oxidation method to form said gate dielectric material.
10. the said according to Claim 8 manufacture method with SOI super junction LDMOS device of resilient coating, it is characterized in that: said grid material is a polycrystalline silicon material.
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| CN105097914B (en) * | 2014-05-04 | 2018-02-06 | 无锡华润上华科技有限公司 | Transverse diffusion metal oxide semiconductor device and its manufacture method |
| CN111969038A (en) * | 2020-08-06 | 2020-11-20 | 互升科技(深圳)有限公司 | Preparation method of field-effect tube and field-effect tube |
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| US7023050B2 (en) * | 2003-07-11 | 2006-04-04 | Salama C Andre T | Super junction / resurf LDMOST (SJR-LDMOST) |
| CN101916728A (en) * | 2010-07-20 | 2010-12-15 | 中国科学院上海微系统与信息技术研究所 | Manufacture technology of superstructure LDMOS structure on SOI capable of completely eliminating substrate-assisted depletion effect |
| CN101916730A (en) * | 2010-07-22 | 2010-12-15 | 中国科学院上海微系统与信息技术研究所 | Method for manufacturing silicon on insulator (SOI) super-junction laterally diffused metal oxide semiconductor (LDMOS) with linear buffer layer |
| CN101916729A (en) * | 2010-07-22 | 2010-12-15 | 中国科学院上海微系统与信息技术研究所 | Method for producing SOI (Silicon on Insulator) LDMOS (Laterally Diffused Metal Oxide Semiconductor) device provided with multi-layer super-junction structure |
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| US7436025B2 (en) * | 2006-09-29 | 2008-10-14 | Freescale Semiconductor, Inc. | Termination structures for super junction devices |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7023050B2 (en) * | 2003-07-11 | 2006-04-04 | Salama C Andre T | Super junction / resurf LDMOST (SJR-LDMOST) |
| CN101916728A (en) * | 2010-07-20 | 2010-12-15 | 中国科学院上海微系统与信息技术研究所 | Manufacture technology of superstructure LDMOS structure on SOI capable of completely eliminating substrate-assisted depletion effect |
| CN101916730A (en) * | 2010-07-22 | 2010-12-15 | 中国科学院上海微系统与信息技术研究所 | Method for manufacturing silicon on insulator (SOI) super-junction laterally diffused metal oxide semiconductor (LDMOS) with linear buffer layer |
| CN101916729A (en) * | 2010-07-22 | 2010-12-15 | 中国科学院上海微系统与信息技术研究所 | Method for producing SOI (Silicon on Insulator) LDMOS (Laterally Diffused Metal Oxide Semiconductor) device provided with multi-layer super-junction structure |
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