CN107994068A - A kind of junction of semiconductor device termination extension structure and preparation method - Google Patents
A kind of junction of semiconductor device termination extension structure and preparation method Download PDFInfo
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- CN107994068A CN107994068A CN201711385694.5A CN201711385694A CN107994068A CN 107994068 A CN107994068 A CN 107994068A CN 201711385694 A CN201711385694 A CN 201711385694A CN 107994068 A CN107994068 A CN 107994068A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 55
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- 238000000034 method Methods 0.000 claims description 19
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 150000002500 ions Chemical class 0.000 claims description 12
- 238000005468 ion implantation Methods 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 7
- 238000002513 implantation Methods 0.000 claims description 7
- 230000002093 peripheral effect Effects 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 4
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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Abstract
The present invention provides a kind of junction of semiconductor device termination extension structure and preparation method, including：Substrate；In forming epitaxial layer on substrate；Main knot is formed in epitaxial layer, main knot extends to inside from epi-layer surface；And shared area is formed from the center of main knot to edge direction in the trapezoid-shaped openings for distribution of continuously successively decreasing in the edge of main knot, ion is injected in each trapezoid-shaped openings, and carry out the high temperature anneal, to form the knot terminal expansion structure that doping concentration is continuously successively decreased along main knot center to edge direction, knot terminal expansion structure extends to inside from epi-layer surface, and positioned at the side wall of main knot.The invention enables the ratio that termination extension region area is accounted for from main knot center to the doped region of edge direction to be distributed in continuous linear decrease, so as to ensure to realize the variety lateral doping that concentration continuity reduces, and then reduce main knot termination environment maximum field strength, optimize the breakdown reverse voltage of semiconductor devices, improve the performance of semiconductor devices.
Description
Technical Field
The invention relates to the technical field of semiconductor chip manufacturing processes, in particular to a junction terminal extension structure of a semiconductor device and a preparation method thereof.
Background
Junction Termination Extension (JTE) technology was first proposed by a.k.sample et al, which is generally applied to semiconductor high-voltage power devices, and is used to control the surface electric field of semiconductor high-voltage devices. The junction termination extension technique is to make a ring of lightly doped P-type region around the main junction. When the main junction is reverse biased, the junction termination extension region will be depleted at the same time. In this case, it is equivalent to introduce negative charges into the depletion region of the drift region, and these negative charges expand the depletion region and can absorb a part of the electric field, so as to reduce the electric field spike at the edge of the main junction, thereby improving the breakdown resistance of the device.
The earliest JTE technology was a Lateral Variation Doping (VLD) technology that divided the termination region into multiple regions, where the JTE region near the main junction maintained a higher concentration to weaken the main junction electric field and the outermost region maintained a lower concentration to reduce the electric field strength of the region itself.
Fig. 1 is a top view of a semiconductor device employing junction termination expansion, comprising: the main junction 11 of the high-voltage power device comprises a large number of cellular structures inside; a junction termination extension structure 12, i.e., a region that employs a junction termination extension technique; and a cut-off ring structure 13 of the high-voltage power device. FIG. 2 is a cross-sectional view of the main junction 11 with the junction terminal extension 12 along AA' direction and an electric field diagram thereof, and it can be seen from FIG. 2 that the maximum value of the electric field intensity E (x) at the edge of the main junction 11 is effectively reduced and the voltage withstanding value of the main junction terminal is improved when the main junction 11 and the N-epitaxy 14 are applied with reverse voltages; at the boundary of the junction termination extension structure 12, the electric field intensity E (x) has a peak E0, and decreases to zero at the depletion layer boundary 131 of the stop ring structure 13. Fig. 3 shows an AA' cross-sectional view of the main junction 11 plus the three-region junction termination extension 12 and an electric field diagram thereof, wherein Q (x) represents the number of doped ions, the number of doped ions in the first junction termination extension 121 region is Q1+ Q2+ Q3, the number of doped ions in the second junction termination extension 122 region is Q2+ Q3, and the number of doped ions in the third junction termination extension 123 region is Q3; it can be seen from the figure that the maximum value of the electric field intensity E (x) at the edge of the main junction 11 is further reduced compared with the main junction plus single junction terminal extension structure of fig. 2, and the withstand voltage value of the main junction terminal is further improved; however, it is also seen that at the abrupt boundary of the first junction terminal extension structure 121, the second junction terminal extension structure 122, and the third junction terminal extension structure 123, the electric field intensity E (x) still has a peak value, E1, E2, E3 in the figure, but the peak value is smaller than E0 in fig. 2, when the main junction 11 and the N-epi 14 are applied with reverse voltages.
From the consideration of process complexity and cost, the prior art realizes junction terminal expansion by using one-time doping instead of multiple times of doping, and realizes windowing and shielding of a doping area according to different proportions mainly through a mask plate. First, as shown in fig. 4, a plurality of junction terminal extension doped regions 12 'are formed on the peripheral junction terminal extension region of the main junction 11, the junction terminal extension doped regions being distributed at intervals and parallel to the edge of the main junction 11, the intervals of the junction terminal extension doped regions 12' are equal, and the widths thereof are sequentially reduced from the center of the main junction to the edge. In the second method, as shown in fig. 5, a plurality of junction terminal extension doped regions 12' are formed on the peripheral junction terminal extension region of the main junction 11, the junction terminal extension doped regions 12' are distributed at intervals and are perpendicular to the edge of the main junction 11, the intervals of the junction terminal extension doped regions 12' are equal, the lengths of the junction terminal extension doped regions are different, and the areas of the doped regions are sequentially reduced along the direction from the center of the main junction to the edge. As shown in fig. 6, which is a cross-sectional view of a semiconductor device AA 'prepared by the prior art, the semiconductor device AA' includes a substrate 15, an N-epi 14 disposed on the substrate 15, a main junction 11 and a junction termination extension structure 12 formed in the N-epi 14, since the ratio of the doped region occupying the area of the termination extension region along the center of the main junction toward the edge direction is not continuously linearly decreased but is decreased in a stepwise manner, after ion redistribution, the implantation concentration ratio is also decreased in a stepwise manner as shown in fig. 7, which is equivalent to the multi-region doped junction termination extension structure of P1 to Pn.
As mentioned above, the electric field intensity E (x) of the junction termination extension region still has a peak value, so how to further optimize the reverse breakdown voltage of the junction termination extension structure 12 and improve the device performance has become one of the problems to be solved by those skilled in the art.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention provides a junction termination extension structure of a semiconductor device and a method for fabricating the same, which is used to solve the problem of high peak value of electric field intensity in the main junction termination region in the prior art.
To achieve the above and other related objects, the present invention provides a junction termination extension structure of a semiconductor device, including at least:
a substrate;
an epitaxial layer on the substrate;
a main junction extending from the epitaxial layer surface to the interior of the epitaxial layer; and
the doping concentration of the junction terminal extension structure is continuously reduced from the center of the main junction to the edge direction, and the junction terminal extension structure extends from the surface of the epitaxial layer to the inside of the epitaxial layer and is positioned on the side wall of the main junction;
wherein the substrate and the epitaxial layer have a first conductivity type, and the main junction and the junction termination extension structure have a second conductivity type.
Preferably, the main junction depth is greater than the depth of the junction termination extension.
Preferably, the first conductive type is P-type doping, and the second conductive type is N-type doping.
Preferably, the first conductive type is N-type doped, and the second conductive type is P-type doped.
Preferably, the doping concentration of the substrate is greater than that of the epitaxial layer, and the doping concentration of the main junction is greater than that of the junction terminal extension structure.
Preferably, the junction termination extension structure surrounds a peripheral edge of the main junction.
Preferably, the area occupied by the doped patterns of the junction terminal extension structure is continuously and progressively decreased from the center of the main junction to the edge direction.
Preferably, the doping pattern is a plurality of trapezoidal openings uniformly distributed on the peripheral edge of the main node, two parallel edges of each trapezoidal opening are parallel to the edge of the main node, and the length of the parallel edge close to the main node is greater than the length of the parallel edge far away from the main node.
Preferably, the doping concentration of the junction terminal extension structure is continuously and linearly decreased along the direction from the center of the main junction to the edge.
More preferably, the doping concentration of the junction termination extension structure satisfies the following relationship:
d ' is the doping concentration at a position h ' away from the edge of the main node, a is the length of the parallel edge of the trapezoidal opening close to the main node, b is the length of the parallel edge of the trapezoidal opening far away from the main node, c is the distance between two adjacent trapezoidal openings at the edge of the main node, h is the height of the trapezoidal opening, h ' is the distance from the edge of the main node, and D is the implantation doping concentration.
In order to achieve the above objects and other related objects, the present invention also provides a method for fabricating a junction termination extension structure of a semiconductor device, the method at least comprising:
step S1: providing a substrate, forming an epitaxial layer on the substrate, and forming a main junction in the epitaxial layer;
step S2: forming a doped pattern at the edge of the main junction, wherein the area occupied by the doped pattern is continuously and progressively decreased from the center of the main junction to the edge direction;
and step S3: and injecting ions into each trapezoid opening, and carrying out high-temperature annealing treatment to form an annular junction terminal extension structure surrounding the periphery of the main junction, wherein the doping concentration of the junction terminal extension structure is continuously reduced progressively along the center of the main junction towards the edge.
Preferably, in step S1, an N-type substrate is provided, an N-type epitaxial layer is epitaxially grown on the N-type substrate, and the P-type main junction is formed in the N-type epitaxial layer by ion implantation.
Preferably, in step S1, a P-type substrate is provided, a P-type epitaxial layer is epitaxially grown on the P-type substrate, and the N-type main junction is formed in the P-type epitaxial layer by ion implantation.
Preferably, in step S2, a mask is formed on the surface of the epitaxial layer and the main junction, and the doping pattern is formed by photolithography; the doping pattern is a plurality of trapezoidal openings uniformly distributed on the peripheral edge of the main junction, two parallel edges of each trapezoidal opening are parallel to the edge of the main junction, and the length of the parallel edge close to the main junction is larger than that of the parallel edge far away from the main junction.
Preferably, the doping concentration of the junction termination extension structure is continuously and linearly decreased along the direction from the center of the main junction to the edge, and the following relationship is satisfied:
d ' is the doping concentration at a position h ' away from the edge of the main node, a is the length of the parallel edge of the trapezoidal opening close to the main node, b is the length of the parallel edge of the trapezoidal opening far away from the main node, c is the distance between two adjacent trapezoidal openings at the edge of the main node, h is the height of the trapezoidal opening, h ' is the distance from the edge of the main node, and D is the implantation doping concentration.
As described above, the junction terminal extension structure of the semiconductor device and the manufacturing method of the junction terminal extension structure of the semiconductor device of the invention have the following beneficial effects:
the semiconductor device junction terminal extension structure and the preparation method of the invention enable the proportion of the doped region from the center of the main junction to the edge direction to the area of the terminal extension region to be continuously and linearly distributed in a descending manner, thereby ensuring the realization of transverse variable doping with reduced concentration continuity, further reducing the peak value of the electric field intensity of the main junction terminal region, optimizing the reverse breakdown voltage of the semiconductor device and improving the performance of the semiconductor device.
Drawings
Fig. 1 is a schematic top view of a prior art semiconductor device employing junction termination extension.
Figure 2 shows a cross-sectional view AA' of a main junction plus single junction termination extension structure of the prior art and its electric field diagram.
Figure 3 shows a cross-sectional view of the AA' direction of the main junction plus three-region junction termination extension structure and its electric field diagram in the prior art.
Fig. 4 shows a method of forming a junction termination extension structure for doping according to the prior art.
Figure 5 shows another prior art method of doping to form junction termination extension structures.
Fig. 6 shows a cross-sectional view of a semiconductor device fabricated in the prior art in the direction of AA'.
Fig. 7 is a schematic diagram showing the implantation concentration ratio of the junction termination extension structure in the prior art.
Fig. 8 is a schematic cross-sectional view of a substrate, an epitaxial layer and a main junction formed by the method for manufacturing a junction terminal extension structure of a semiconductor device according to the present invention.
Fig. 9 is a schematic cross-sectional view illustrating a second mask formed for a method of fabricating a junction termination extension structure of a semiconductor device according to the present invention.
Fig. 10 is a schematic top view illustrating the formation of a second mask for a method of fabricating a junction termination extension structure of a semiconductor device according to the present invention.
Fig. 11 is a partially enlarged top view illustrating a method for fabricating a junction termination extension structure of a semiconductor device according to the present invention, in which a trapezoidal opening is formed at a straight edge of a main junction.
Figure 12 is a partially enlarged top view of a method of forming a trapezoidal opening at the edge of a main junction fillet for fabricating a junction termination extension structure of a semiconductor device in accordance with the present invention.
Fig. 13 is a top view of a trapezoidal doped region formed for the method of fabricating a junction termination extension structure of a semiconductor device of the present invention.
Fig. 14 is a partially enlarged top view of a junction termination extension structure formed for the method of fabricating a junction termination extension structure of a semiconductor device of the present invention.
Fig. 15 is a partially enlarged sectional view showing the formation of a junction termination extension structure for the method of fabricating a junction termination extension structure of a semiconductor device according to the present invention.
Fig. 16 is a schematic view showing the implantation concentration ratio of the junction termination extension structure of the semiconductor device of the present invention.
Fig. 17 is a simulation comparison diagram showing reverse breakdown voltages V1, V2, and V3 of the main junction plus single junction termination extension structure, the main junction plus three-region junction termination extension structure, and the junction termination extension structure of the semiconductor device of the present invention under the same doping concentration D.
Description of the element reference
11. Main junction
12' junction termination extension doped region
12. Junction terminal extension structure
121. First junction terminal extension structure
122. Second junction termination extension structure
123. Third junction termination extension structure
13. Cutoff ring structure
131. Boundary of depletion layer
14 N-epitaxy
15. Substrate
21. Substrate
22. Epitaxial layer
23. Main junction
24. Second mask
241. Trapezoidal opening
251. Trapezoidal doped region
25. Junction termination extension structure
26. Depletion layer
S1 to S3
Detailed Description
The following embodiments of the present invention are provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 8-17. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
As shown in fig. 8, the present invention provides a method for preparing a junction termination extension structure of a semiconductor device, comprising:
step S1: a substrate 21 is provided, an epitaxial layer 22 is formed on the substrate, and a main junction 23 is formed in the epitaxial layer 22.
Specifically, as shown in fig. 8, as an implementation manner of the present invention, an N-type substrate is provided, and an N-type epitaxial layer is epitaxially grown on the N-type substrate, where a doping concentration of the N-type substrate is greater than a doping concentration of the N-type epitaxial layer. Forming a first mask on the surface of the N-type epitaxial layer, patterning the first mask through photoetching to expose the N-type epitaxial layer at a set main junction position, performing P-type doping on the N-type epitaxial layer by adopting ion implantation to form a main junction 23, and removing the first mask.
Specifically, as shown in fig. 8, as an implementation manner of the present invention, a P-type substrate is provided, and a P-type epitaxial layer is epitaxially grown on the P-type substrate, where a doping concentration of the P-type substrate is greater than a doping concentration of the P-type epitaxial layer. Forming a first mask on the surface of the P-type epitaxial layer, patterning the first mask through photoetching to expose the P-type epitaxial layer at a set main junction position, carrying out N-type doping on the P-type epitaxial layer by adopting ion implantation to form a main junction 23, and removing the first mask.
Step S2: and forming doped patterns at the edges of the main junction 23, wherein the areas occupied by the doped patterns are continuously and progressively distributed from the center of the main junction 23 to the edge direction.
Specifically, as shown in fig. 9, a second mask 24 is formed on the surface of the epitaxial layer 22 and the main junction 23, and the second mask 24 is patterned by photolithography to form the doping pattern. As shown in fig. 10 to 12, the doping pattern is a plurality of trapezoidal openings 241 uniformly distributed on the periphery of the main node 23, the shape of the trapezoidal openings 241 includes but is not limited to a trapezoid, in this embodiment, the trapezoidal openings 241 are isosceles trapezoids, and in practical applications, any occupied area is continuously and progressively decreased from the center of the main node 23 to the edge direction, and the structure is suitable for the present invention, and is not limited to this embodiment. As shown in fig. 11, two parallel sides of the trapezoidal opening 241 are parallel to corresponding edges of the main node 23, and the length of the parallel side close to the main node 23 is greater than the length of the parallel side far from the main node 23; the trapezoidal openings 241 are equally spaced. As shown in fig. 12, in the present embodiment, the main junction 23 is a regular quadrangle, four corners of the quadrangle are rounded corners, the trapezoidal openings 241 at the rounded corners are uniformly distributed along the edges of the rounded corners, and two parallel sides of each trapezoidal opening 241 are parallel to the tangent of the corresponding rounded corner.
And step S3: and injecting ions into each trapezoid opening 241, and performing high-temperature annealing treatment to form an annular junction terminal extension structure 25 surrounding the periphery of the main junction 23, wherein the doping concentration of the junction terminal extension structure 25 is continuously decreased progressively along the center of the main junction 23 towards the edge direction.
Specifically, as shown in fig. 13, as an embodiment of the present invention, P-type ion implantation is performed on the N-type epitaxial layer with a set dose D to form a plurality of trapezoidal doping regions 251, the doping concentration of the trapezoidal doping regions 251 is less than the doping concentration of the main junction 23, and the second mask is removed.
Specifically, as shown in fig. 13, as another embodiment of the present invention, N-type ion implantation is performed on the P-type epitaxial layer by using a set dose D to form a plurality of trapezoidal doping regions 251, the doping concentration of the trapezoidal doping regions 251 is less than the doping concentration of the main junction 23, and the second mask is removed.
Specifically, as shown in fig. 14, high-temperature annealing treatment is performed to redistribute impurity ions, so that ions in the trapezoidal doping region 251 are laterally diffused, and the diffused regions are mutually coherent and equivalent to different doping concentrations, thereby achieving a laterally varying doping effect, and further forming a junction terminal extension structure 25 surrounding the periphery of the main junction 23. As shown in fig. 14 to 15, the doping concentration of the junction termination extension structure 25 is continuously and linearly decreased from the center of the main junction 23 to the edge, and the doping depth is smaller than the depth of the main junction 23. As shown in fig. 16, in the present embodiment, the doping concentration of the junction termination extension structure 25 is continuously and linearly decreased along the center of the main junction 23 toward the edge.
On the premise of ensuring the geometrical design rule of the doped graph and the consistency of the doped region after high-temperature annealing and transverse diffusion, the doping concentration distribution curves with different concentration ratios can be realized by adjusting the length of the bottom side and the length of the top side of the trapezoid opening, the distance between the bottom sides of adjacent trapezoids and the height of the trapezoid. Setting a to be the length of the parallel edge of the trapezoidal opening 241 close to the main node 23, b to be the length of the parallel edge of the trapezoidal opening 241 far from the main node 23, c to be the distance between two adjacent trapezoidal openings 241 at the edge of the main node 23, and h to be the height of the trapezoidal opening 241, wherein a, b, c, and h all need to meet the minimum photoetching precision under the manufacturing process, and the width of a + c-b needs to ensure diffusion junction communication after high-temperature annealing transverse diffusion; the equivalent doping concentration D' of the junction termination extension structure 25 satisfies the following relationship:
as shown in fig. 14 to 15, the present invention provides a semiconductor device junction termination extension structure including:
a substrate 21, an epitaxial layer 22, a main junction 23, and a junction termination extension 24.
As shown in fig. 15, the substrate 21 is a P-type substrate or an N-type substrate.
As shown in fig. 15, the epitaxial layer 22 is located on the substrate 21, the doping type of the epitaxial layer 22 is the same as that of the substrate, and the doping concentration of the epitaxial layer 22 is less than that of the substrate 21.
As shown in fig. 15, the main junction 23 extends from the surface of the epitaxial layer 22 to the inside of the epitaxial layer 22, and is formed by doping ions into the epitaxial layer 22. As shown in fig. 10, in the present embodiment, the main junction 23 is a quadrilateral with smooth edges and rounded corners, and in practical applications, the shape of the horizontal cross section of the main junction 23 is not limited.
As shown in fig. 14 to 15, the junction termination extension structure 25 extends from the surface of the epitaxial layer 22 to the inside of the epitaxial layer 22 and surrounds the side wall of the main junction 23.
Specifically, the doping type of the junction termination extension structure 25 is the same as the doping type of the main junction 23, and the depth of the junction termination extension structure 25 is smaller than the depth of the main junction 23. The doping concentration of the junction terminal extension structure 25 is less than the doping concentration of the main junction 23, and the doping concentration of the junction terminal extension structure 25 decreases continuously along the center of the main junction 23 toward the edge direction, in this embodiment, the doping concentration of the junction terminal extension structure 25 decreases continuously and linearly along the center of the main junction 23 toward the edge direction.
As shown in fig. 15, a depletion layer 26 is provided below the main junction 23 and the junction termination extension structure 25.
As shown in fig. 17, a simulation comparison diagram of reverse breakdown voltages V1, V2, and V3 of the main junction plus single junction terminal extension structure, the main junction plus three-region junction terminal extension structure, and the junction terminal extension structure of the semiconductor device of the present invention under the condition of the same doping concentration D shows that V1< V2< V3.
In summary, the present invention provides a junction terminal extension structure of a semiconductor device and a method for manufacturing the same, including: a substrate; an epitaxial layer on the substrate; a main junction extending from the epitaxial layer surface to the interior of the epitaxial layer; the doping concentration of the junction terminal extension structure is continuously reduced from the center of the main junction to the edge direction, and the junction terminal extension structure extends from the surface of the epitaxial layer to the inside of the epitaxial layer and is positioned on the side wall of the main junction; wherein the substrate and the epitaxial layer have a first conductivity type, and the main junction and the junction termination extension structure have a second conductivity type. Providing a substrate, forming an epitaxial layer on the substrate, and forming a main junction in the epitaxial layer; forming a doped graph at the edge of the main junction, wherein the area occupied by the doped graph is continuously and progressively decreased from the center of the main junction to the edge direction; and injecting ions into each trapezoid opening, and carrying out high-temperature annealing treatment to form an annular junction terminal extension structure surrounding the periphery of the main junction, wherein the doping concentration of the junction terminal extension structure is continuously reduced progressively along the center of the main junction towards the edge. The semiconductor device junction terminal extension structure and the preparation method of the invention enable the proportion of the doped region from the center of the main junction to the edge direction to the area of the terminal extension region to be continuously and linearly distributed in a descending manner, thereby ensuring the realization of transverse variable doping with reduced concentration continuity, further reducing the peak value of the electric field intensity of the main junction terminal region, optimizing the reverse breakdown voltage of the semiconductor device and improving the performance of the semiconductor device. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (15)
1. A semiconductor device junction termination extension structure, comprising at least:
a substrate;
an epitaxial layer on the substrate;
a main junction extending from the epitaxial layer surface to the interior of the epitaxial layer; and
the doping concentration of the junction terminal extension structure is continuously reduced from the center of the main junction to the edge direction, and the junction terminal extension structure extends from the surface of the epitaxial layer to the inside of the epitaxial layer and is positioned on the side wall of the main junction;
wherein the substrate and the epitaxial layer have a first conductivity type, and the main junction and the junction termination extension structure have a second conductivity type.
2. The semiconductor device junction termination extension structure of claim 1, wherein: the main junction depth is greater than the junction termination extension depth.
3. The semiconductor device junction termination extension structure of claim 1, wherein: the first conductive type is P-type doping, and the second conductive type is N-type doping.
4. The semiconductor device junction termination extension structure of claim 1, wherein: the first conductive type is N-type doping, and the second conductive type is P-type doping.
5. The semiconductor device junction termination extension structure of claim 3 or 4, wherein: the doping concentration of the substrate is greater than that of the epitaxial layer, and the doping concentration of the main junction is greater than that of the junction terminal extension structure.
6. The semiconductor device junction termination extension structure of claim 1, wherein: the junction termination extension structure surrounds the peripheral edge of the main junction.
7. The semiconductor device junction termination extension structure of claim 1, wherein: the area occupied by the doped graph of the junction terminal extension structure is continuously and progressively decreased from the center of the main junction to the edge direction.
8. The semiconductor device junction termination extension structure of claim 7, wherein: the doping pattern is a plurality of trapezoidal openings uniformly distributed on the periphery of the main junction, two parallel edges of each trapezoidal opening are parallel to the edge of the main junction, and the length of the parallel edge close to the main junction is larger than that of the parallel edge far away from the main junction.
9. The semiconductor device junction termination extension structure of claim 1, wherein: and the doping concentration of the junction terminal extension structure is continuously and linearly decreased gradually from the center of the main junction to the edge direction.
10. The semiconductor device junction termination extension structure of claim 9, wherein: the doping concentration of the junction terminal extension structure satisfies the following relation:
d ' is the doping concentration at a position h ' away from the edge of the main node, a is the length of the parallel edge of the trapezoidal opening close to the main node, b is the length of the parallel edge of the trapezoidal opening far away from the main node, c is the distance between two adjacent trapezoidal openings at the edge of the main node, h is the height of the trapezoidal opening, h ' is the distance from the edge of the main node, and D is the implantation doping concentration.
11. A method for preparing a junction terminal extension structure of a semiconductor device is characterized in that the junction terminal extension structure of the semiconductor device at least comprises the following steps:
step S1: providing a substrate, forming an epitaxial layer on the substrate, and forming a main junction in the epitaxial layer;
step S2: forming a doped pattern at the edge of the main junction, wherein the area occupied by the doped pattern is continuously and progressively decreased from the center of the main junction to the edge direction;
and step S3: and injecting ions into each trapezoid opening, and carrying out high-temperature annealing treatment to form an annular junction terminal extension structure surrounding the periphery of the main junction, wherein the doping concentration of the junction terminal extension structure is continuously reduced progressively along the center of the main junction towards the edge.
12. The method for manufacturing a junction termination extension structure of a semiconductor device according to claim 11, wherein: in step S1, an N-type substrate is provided, an N-type epitaxial layer is epitaxially grown on the N-type substrate, and the P-type main junction is formed in the N-type epitaxial layer by ion implantation.
13. The method for manufacturing a junction termination extension structure of a semiconductor device according to claim 11, wherein: in step S1, a P-type substrate is provided, a P-type epitaxial layer is epitaxially grown on the P-type substrate, and the N-type main junction is formed in the P-type epitaxial layer by ion implantation.
14. The method for manufacturing a junction termination extension structure of a semiconductor device according to claim 11, wherein: in the step S2, forming a mask on the epitaxial layer and the surface of the main junction, and forming the doped pattern through photoetching; the doping patterns are a plurality of trapezoid openings uniformly distributed on the periphery of the main junction, two parallel edges of each trapezoid opening are parallel to the edge of the main junction, and the length of the parallel edge close to the main junction is larger than that of the parallel edge far away from the main junction.
15. The method for manufacturing a junction termination extension structure of a semiconductor device according to claim 11, wherein: the doping concentration of the junction terminal extension structure is continuously and linearly decreased along the direction from the center of the main junction to the edge, and the following relation is satisfied:
d ' is the doping concentration at a position h ' away from the edge of the main node, a is the length of the parallel edge of the trapezoidal opening close to the main node, b is the length of the parallel edge of the trapezoidal opening far away from the main node, c is the distance between two adjacent trapezoidal openings at the edge of the main node, h is the height of the trapezoidal opening, h ' is the distance from the edge of the main node, and D is the implantation doping concentration.
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