CN115497934B - Territory structure for protecting super junction device terminal - Google Patents
Territory structure for protecting super junction device terminal Download PDFInfo
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- CN115497934B CN115497934B CN202211229220.2A CN202211229220A CN115497934B CN 115497934 B CN115497934 B CN 115497934B CN 202211229220 A CN202211229220 A CN 202211229220A CN 115497934 B CN115497934 B CN 115497934B
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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Abstract
The invention provides a layout structure for terminal protection of a superjunction device, which comprises a transition region and a terminal region; the terminal area is arranged at the periphery of the transition area; the transition zone comprises: a first conductive type column and a second conductive type column alternately arranged, and a second conductive type base region formed over the first conductive type column and the second conductive type column; the layout graph of the second conductive type base region positioned at the corner part of the transition region is in a ladder shape, and the mesa starting point of each step in the ladder-shaped graph is positioned on the second conductive type column. The layout structure for the terminal protection of the super-junction device can solve the problem that when the depletion layer of the traditional super-junction device expands to the corner of the transition region and the corner of the terminal region, charge depletion on two sides of an N-type column is unbalanced, the depletion layer is defective, and the breakdown voltage of the device is low.
Description
Technical Field
The invention relates to the field of power semiconductor devices, in particular to a layout structure for protecting a super junction device terminal.
Background
The on-resistance of the conventional power semiconductor device increases sharply with the increase of withstand voltage, resulting in a drastic increase of power consumption. The occurrence of charge balance devices represented by Super-Junction devices breaks the limitation, improves the restriction relation between on-resistance and withstand voltage, and can realize low on-state power consumption and high blocking voltage at the same time, so that the charge balance device can be rapidly applied to various high-energy-efficiency occasions, and has very wide market prospect.
In the super junction device, a P-type column and an N-type column structure which are alternately arranged are adopted to replace a single conductive type material in the traditional power device as a voltage maintaining layer, and a transverse electric field is introduced into a drift region; and the P-type column and the N-type column meet the charge balance condition, under the reverse bias, the P-type column and the N-type column are completely depleted, and only the external voltage is larger than the internal transverse electric field, the region can be broken down, so that the voltage withstand of the region (the active region is divided into a charge flow region and a transition region around the charge flow region) is extremely high, and the purposes of improving the breakdown voltage and reducing the on-resistance can be achieved.
The terminal structure of the superjunction device most widely used at present adopts the same structure as the active region, as shown in fig. 1 and 2, and is a layout structure of the superjunction device most widely used (N-type channel device), it can be seen that the terminal region also has a plurality of alternating P-type columns and N-type columns, but since the P-type base region pattern at the corner of the terminal region and the transition region is of a right angle type (as shown in the dashed line frame in fig. 1) or of an arc type (as shown in the dashed line frame in fig. 2), the depletion layer at this position is prone to defects:
because of the voltage effect of reverse breakdown, depletion is approximately expanded in a spherical shape in the whole device, and for the right-angle type boundary line shown in fig. 1, when the depletion layer is expanded to the sharp corner of the right-angle type boundary line, the depletion state of the depletion layer is influenced by charge concentration existing at the sharp corner, so that the breakdown voltage of the superjunction device is reduced; for the arc boundary line shown in fig. 2, when the depletion layer expands to the boundary line, the P-type pillar at the boundary line cannot fully deplete the N-type pillar, which affects the formation speed and the form of the depletion layer and reduces the breakdown voltage of the superjunction device.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention is directed to providing a layout structure for protecting a super junction device terminal, which is used for solving the problem that when a depletion layer of the existing super junction device is expanded to a transition region corner and a terminal region corner, charge depletion on two sides of an N-type column is unbalanced, and the depletion layer is defective, so that breakdown voltage of the device is low.
In order to achieve the above purpose, the invention provides a layout structure for protecting a super junction device terminal, wherein the layout structure comprises a transition region and a terminal region;
the terminal area is arranged at the periphery of the transition area;
the transition zone comprises: a first conductive type column and a second conductive type column alternately arranged, and a second conductive type base region formed over the first conductive type column and the second conductive type column;
the layout graph of the second conductive type base region positioned at the corner part of the transition region is in a ladder shape, and the mesa starting point of each step in the ladder-shaped graph is positioned on the second conductive type column.
Optionally, the mesa starting points of the steps of each stage together form an arc, and the opening of the arc faces to the inner side of the transition region.
Optionally, the mesa start point and the mesa end point of the step of each level are located on a longitudinal central axis of the second conductivity type pillar.
Optionally, the mesa start point of the step of the kth level is located on the kth column of the second conductivity type, and then the mesa end point of the step of the kth level is located on the k+1th column of the second conductivity type, where K is greater than or equal to 1.
Optionally, the layout structure further includes a charge flow region, wherein the transition region is formed between the charge flow region and the terminal region; a second conductivity type base region is formed on the second conductivity type pillar in the charge flow region, and the second conductivity type base region is formed on both the first conductivity type pillar and the second conductivity type pillar in the transition region.
Optionally, the layout structure further comprises a cutoff ring, and the cutoff ring is located at the periphery of the terminal area.
Optionally, the length of the first conductivity type pillars is the same as the length of the second conductivity type pillars.
Optionally, the first conductivity type is N-type, and the second conductivity type is P-type.
As described above, in the layout structure for protecting the super junction device terminal, the layout pattern of the second conductive type base region at the corner part of the transition region is in a ladder shape, and the multi-stage steps at the corner part jointly bear charge concentration, compared with the layout pattern of a right angle type, the layout structure has the advantages that the charge concentration is borne by only one right angle, and the influence generated by the charge concentration can be obviously reduced; and the mesa starting point and the mesa end point of each step are both positioned at the center of the second conductive type column, when the depletion layer expands the corner part of the transition region and the corner part of the terminal region, the charge depletion on two sides of the second conductive type column is balanced, the expansion depletion state of the depletion layer is not influenced, and the breakdown voltage of the superjunction device is not reduced.
Drawings
Fig. 1 shows a layout structure of a right-angle super-junction device terminal protection of a layout pattern of a second conductive type base region of a corner part of a transition region in the background art.
Fig. 2 shows a layout structure of terminal protection in which the layout pattern of the second conductivity type base region of the corner portion of the transition region is an arc type.
Fig. 3 shows a layout structure for protecting a super junction device terminal according to the invention.
Figure 4 shows a quarter-turn of the layout structure for termination protection of the superjunction device according to the invention.
Fig. 5 is a schematic perspective view of a superjunction device according to the present invention.
Description of the component reference numerals
10. Layout structure for protecting super junction device terminal
Two central axes of layout structure for terminal protection of A-A ', B-B' super junction device
11. Quarter equal parts of layout structure for terminal protection of superjunction device
111. Charge flow region
112. Transition zone
120. Termination region
130 N type column (first conductivity type column)
140 P type column (second conductive type column)
131. K-th N-type column
141. K-stage P-type column
142. K+1st P-type column
150 P base region (second conductivity type base region)
160. Cut-off ring
Midline of M-M' K-th N-type column
Midline of L-L' K-th P-type column
Neutral line of R-R' K+1st P-type column
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 3 to fig. 5. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
The present embodiment provides a layout structure 10 for protecting a super junction device terminal, as shown in fig. 3, the layout structure 10 includes a transition region 112 and a terminal region 120.
In this embodiment, for convenience of explanation, the layout structure 10 is divided into 4 equal parts along two central axes (axis A-A 'and axis B-B') of the layout structure 10 for superjunction device termination protection as shown in fig. 3, and the following figures are all descriptions of the layout structure 10 for superjunction device termination protection based on the quarter equal part 11 located in the upper left corner as an example as shown in fig. 4.
The terminal area 120 is disposed at the outer periphery of the transition area 112, and the transition area 112 includes: the first conductive type pillars 130 and the second conductive type pillars 140 are alternately arranged, and the second conductive type base region 150 is formed over the first conductive type pillars 130 and the second conductive type pillars 140.
In this embodiment, the first conductive type pillar 130 may be an N-type pillar or a P-type pillar, the second conductive type pillar 140 may be an N-type pillar or a P-type pillar, and the conductive type of the first conductive type pillar 130 is opposite to the conductive type of the second conductive type pillar 140; taking a superjunction device with an N-type channel region as an example (the first conductive type column is an N-type column, and the second conductive type column is a P-type column), as shown in fig. 4, in the transition region 112 of the layout structure 10 for terminal protection of the superjunction device, a plurality of P-type columns 140 and a plurality of N-type columns 130 are arranged in parallel and adjacently and alternately, and the arrangement direction of the P-type columns and the N-type columns, and the lengths of the P-type columns and the N-type columns formed in the terminal region 120 are the same as those in the transition region 112. As a preferred embodiment, the length dimension between each P-type pillar 140 and N-type pillar 130 may be the same; it should be noted that in some variant embodiments, the superjunction unit with other topologies is also applicable to the superjunction device of the present invention.
Specifically, the layout structure 10 for terminal protection of the superjunction device further includes a charge flow region 111, where the transition region 112 is formed between the charge flow region 111 and the terminal region 120; a second conductivity type base region 150 is formed on the second conductivity type pillar 140 in the charge flow region 111, and the second conductivity type base region 150 is formed on both the first conductivity type pillar 130 and the second conductivity type pillar 140 in the transition region 120.
In this embodiment, the second conductivity type base region 150 has the same conductivity type as the second conductivity type column 140, and is P-type conductivity, and thus is P-base region (P-body); as shown in fig. 4 and 5, the region covered by diagonal hatching in the drawing is a P base region, and the P base region is formed at the upper end of a P-type column or an N-type column by ion implantation or the like; as shown in fig. 4, the P base region is formed only at the upper end of the P-type pillar (the P base region has the same width as the P-type pillar), and it should be noted that, in some embodiments, the P base region on the charge flow region 111 may be slightly wider than the P-type pillar, and some regions are formed at the upper end of the N-type pillar, but not completely cover one N-type pillar, so that a sufficient channel region width is reserved for the superjunction device in advance; a P base region is formed on the transition region 112, at the upper end of the N-type column or the upper end of the P-type column, and completely covers the P-type column and the B-type column; no P base region is formed in the terminal region 120, either at the upper end of the N-type pillar or at the upper end of the P-type pillar.
The layout pattern of the second conductivity type base region 140 located at the corner of the transition region 112 is in a step shape, and the mesa start point of each step in the step shape is located on the second conductivity type column 140.
In this embodiment, as shown in fig. 4, the layout pattern of the P base region located at the corner portion of the transition region 112 is in a stepped shape, and the external line of the layout pattern of the P base region is actually the boundary between the transition region 112 and the terminal region 120, where the P base region needs to be formed in the transition region 112, and the P base region does not need to be formed in the terminal region. When the layout graph of the P base region is in a ladder shape, the charges collected at the corners of the P base region are jointly borne by N steps, and compared with the charges collected at the corners of the P base region in fig. 1, the charges collected at the corners of the P base region are all borne by a right angle, so that the influence of charge concentration can be remarkably reduced, and the influence of the charge concentration at the corners on depletion forms is reduced.
Specifically, the mesa start point and the mesa end point of the step of each level are located on the longitudinal central axis of the second conductive type column 150.
In this embodiment, as shown in fig. 5, when the depletion layer expands to the corner of the transition region 112 and the terminal region 120, the N-type column and the P-type column below each step can be completely depleted, so that the problem of the depletion state of the depletion layer due to unbalanced charge on both sides of the N-type column in the dashed line frame in fig. 2 is avoided. Taking the kth step in the transition region 112 as an example, one N-type pillar 131 spanned by the kth step is defined as a kth-type N-type pillar, the center line of the kth-type N-type pillar 131 is M, the center line of the kth-type P-type pillar 141 immediately on the left side of the kth-type N-type pillar 131 is L, and the center line of the k+1th-type P-type pillar 142 immediately on the right side of the kth-type N-type pillar 131 is R; when the depletion layer expands, the region from the center line L to the center line R can be completely depleted by taking M as the center line, and the expansion form of the depletion layer when the depletion layer expands to the corner of the transition region and the corner of the terminal region is not influenced.
Specifically, the mesa starting points of the steps of each stage together form an arc, and the opening of the arc faces toward the inner side of the transition region 112.
In this embodiment, as shown in fig. 3, when the depletion layer expands in the superjunction device, the depletion layer expands approximately spherically, and when the number of steps is enough, if the mesa starting points of the steps are all distributed sequentially on a smooth circular arc (as shown by the dashed curve in fig. 3), then, as shown in fig. 4, the stepped graph formed by a plurality of micro steps can be regarded as a circular arc smooth curve, and when the depletion layer expands to the corner of the transition region 112 and the terminal region 120, the shape of the depletion layer expands approximately as a curved surface, so that the depletion layer continues to expand spherically, the shape of the depletion layer is not affected during expansion, and the breakdown voltage of the superjunction device can be effectively reduced. As a preferable example, when the mesa starting point of the step of the Kth stage is located on the Kth P-type column and the mesa end point of the step of the Kth stage is located on the K+1st P-type column (K is greater than or equal to 1), the point positions forming the arc line can be the most, the curve is the smoother, the expansion form of the depletion layer is more similar to that of the depletion layer, and the expansion form of the depletion layer is further slightly influenced.
Specifically, the layout structure further includes a stop ring 160, where the stop ring 160 is located at the periphery of the termination region 120.
In this embodiment, in the terminal region 120, the outer sides of the alternating arrangement of the N-type pillars 130 and the P-type pillars 140 are further provided with stop rings 160, and the conductivity type of the stop rings 160 is N-type, which is n+ doped with a doping concentration greater than 1e16cm-3 relative to the N-type substrate.
Specifically, the length of the first conductive type pillars 130 is the same as the length of the second conductive type pillars 140.
In this embodiment, whether the K-stage N-type pillar 131 and the K-stage P-type pillar 141 and the k+1st stage P-type pillar 142 can be completely depleted in the region from the center line L to the center line R depends on the width and the concentration of the N-type pillar 130 and the P-type pillar 140, and when the product of the width and the concentration of the N-type pillar 130 is equal to the product of the width and the concentration of the P-type pillar 140, the region from the center line L to the center line R is completely depleted and exhibits the intrinsic characteristic, which is beneficial to improving the breakdown voltage of the superjunction device.
The embodiment also provides a photomask and a superjunction device, wherein the photomask is obtained based on the layout structure of the terminal protection of the superjunction device, and the photomask is used for forming the second conductive type base region.
In this embodiment, due to the improvement of the layout structure of the superjunction device terminal protection, in order to form a corresponding device structure, the photomask applied in the process needs to be changed correspondingly, and the layout structure of the superjunction device terminal protection in this embodiment actually relates to a two-layer layout, wherein the first layer layout is a layout layer defining the distribution, shape and size of the N-type columns and the P-type columns, and the second layer layout is a layout layer defining the distribution, shape and size of the P-base region, and the photomask applied in the process needs to be changed correspondingly according to the second layer layout, so as to prepare the P-base region conforming to the layout of the superjunction device in this embodiment.
The embodiment also provides a superjunction device, which is prepared by adopting the photomask.
In this embodiment, during the preparation, a substrate is provided first, and the above photomask is used to prepare the superjunction device, and the layout structure of terminal protection of the superjunction device is described in detail above, so that the description is omitted here.
In summary, in the layout structure for protecting the super-junction device terminal, the layout pattern of the second conductive type base region at the corner part of the transition region is in a ladder shape, and the multi-stage steps at the corner part jointly bear charge concentration, so that compared with the layout pattern of a right angle type, the layout structure has the advantages that the effect of charge concentration can be obviously reduced because only one right angle bears charge concentration; and the mesa starting point and the mesa end point of each step are both positioned at the center of the second conductive type column, when the depletion layer expands to the corner part of the transition region and the corner part of the terminal region, the charge depletion on the two sides of the second conductive type column is balanced, the depletion expansion form of the depletion layer is not influenced, and the breakdown voltage of the superjunction device is not reduced. Therefore, the invention has great industrial application value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (8)
1. The layout structure for protecting the super junction device terminal is characterized by comprising a transition area and a terminal area;
the terminal area is arranged at the periphery of the transition area;
the transition zone comprises: a first conductive type column and a second conductive type column alternately arranged, and a second conductive type base region formed over the first conductive type column and the second conductive type column;
the layout graph of the second conductive type base region positioned at the corner part of the transition region is in a ladder shape, and the mesa starting point of each step in the ladder-shaped graph is positioned on the second conductive type column.
2. The layout structure of the super junction device termination protection according to claim 1, wherein the mesa start points of the steps of each stage together form an arc, and the opening of the arc faces to the inner side of the transition region.
3. The layout structure of claim 1, wherein the mesa start point and the mesa end point of each level of the step are located on a longitudinal central axis of the second conductivity type pillar.
4. The layout structure for protecting a super junction device terminal according to claim 1, wherein a mesa start point of the step of the kth level is located on the kth second conductive type column, and a mesa end point of the step of the kth level is located on the (k+1) th second conductive type column, and K is greater than or equal to 1.
5. The layout structure of claim 1, further comprising a charge flow region, wherein the transition region is formed between the charge flow region and the termination region; a second conductivity type base region is formed on the second conductivity type pillar in the charge flow region, and the second conductivity type base region is formed on both the first conductivity type pillar and the second conductivity type pillar in the transition region.
6. The layout structure for termination protection of a superjunction device according to claim 1, further comprising a cutoff ring located at the periphery of the termination region.
7. The layout structure for termination protection of a superjunction device according to claim 1, wherein the length of the first conductivity type pillar is the same as the length of the second conductivity type pillar.
8. The layout structure of claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type.
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| CN104183627A (en) * | 2014-08-29 | 2014-12-03 | 电子科技大学 | Super junction power device terminal structure |
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| CN106328688A (en) * | 2015-07-02 | 2017-01-11 | 北大方正集团有限公司 | Structure and manufacturing method of terminal voltage-division region for super-junction device |
| CN113782584A (en) * | 2021-08-05 | 2021-12-10 | 上海华虹宏力半导体制造有限公司 | Super junction device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4289123B2 (en) * | 2003-10-29 | 2009-07-01 | 富士電機デバイステクノロジー株式会社 | Semiconductor device |
| JP5052025B2 (en) * | 2006-03-29 | 2012-10-17 | 株式会社東芝 | Power semiconductor device |
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1663049A (en) * | 2002-06-26 | 2005-08-31 | 剑桥半导体有限公司 | Lateral semiconductor device |
| JP2007335844A (en) * | 2006-05-16 | 2007-12-27 | Toshiba Corp | Semiconductor device |
| CN104183627A (en) * | 2014-08-29 | 2014-12-03 | 电子科技大学 | Super junction power device terminal structure |
| CN106057888A (en) * | 2015-04-02 | 2016-10-26 | 富士电机株式会社 | Semiconductor device and semiconductor device manufacturing method |
| CN106328688A (en) * | 2015-07-02 | 2017-01-11 | 北大方正集团有限公司 | Structure and manufacturing method of terminal voltage-division region for super-junction device |
| CN113782584A (en) * | 2021-08-05 | 2021-12-10 | 上海华虹宏力半导体制造有限公司 | Super junction device |
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Denomination of invention: A Layout Structure for Terminal Protection of Hyperjunction Devices Effective date of registration: 20231228 Granted publication date: 20230526 Pledgee: Wuding Road Sub branch of Bank of Shanghai Co.,Ltd. Pledgor: Shanghai Gongcheng Semiconductor Technology Co.,Ltd. Registration number: Y2023980075345 |