CN104112770A - Flat-edge structure of semiconductor device terminal, manufacturing process and optical mask plate - Google Patents
Flat-edge structure of semiconductor device terminal, manufacturing process and optical mask plate Download PDFInfo
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- CN104112770A CN104112770A CN201410326054.7A CN201410326054A CN104112770A CN 104112770 A CN104112770 A CN 104112770A CN 201410326054 A CN201410326054 A CN 201410326054A CN 104112770 A CN104112770 A CN 104112770A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 230000003287 optical effect Effects 0.000 title abstract 5
- 239000012535 impurity Substances 0.000 claims abstract description 19
- 238000002347 injection Methods 0.000 claims abstract description 11
- 239000007924 injection Substances 0.000 claims abstract description 11
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims description 21
- 238000002513 implantation Methods 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 2
- 230000002093 peripheral effect Effects 0.000 abstract 3
- 230000005540 biological transmission Effects 0.000 abstract 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 8
- 239000010410 layer Substances 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 6
- 230000005684 electric field Effects 0.000 description 4
- 238000000407 epitaxy Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/26—Phase shift masks [PSM]; PSM blanks; Preparation thereof
- G03F1/34—Phase-edge PSM, e.g. chromeless PSM; Preparation thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
Abstract
The invention discloses a flat-edge structure of a semiconductor device terminal. The flat edge is provided with a center region and a plurality of peripheral regions which are located outside the two ends of the center region and have doping concentrations which are reduced sequentially from inside to outside, a midpoint of the flat edge of the terminal being the center. The invention also discloses a manufacturing process of the flat-edge structure. The process includes the following steps: rotating coating of a photoresist is carried out and the following optical mask plate is used for exposure and development; areas of transmission regions of the peripheral regions outside the two ends of the center region of the optical mask plate are reduced gradually from inside to outside; doping is formed through N-type or P-type impurity injection; high-temperature oxidization junction pushing is carried out; stop rings are formed through the N-type or P-type injection; and field plates are formed. The invention also discloses the optical mask plate used for manufacturing of the semiconductor device terminal and the areas of the transmission regions of the peripheral regions outside the two ends of the center region are reduced gradually from inside to outside. Through gradual reduction of the doping concentration of the flat edge of the semiconductor device terminal from the middle to the two sides, the flat-edge structure of the semiconductor device, the manufacturing process and the optical mask plate are capable of shorter terminal length or lower switch-on resistance.
Description
Technical field
The present invention relates to a kind of semiconductor device terminal and manufacturing process thereof, relate in particular to a kind of flat limit structure, manufacturing process and photomask blank of semiconductor device terminal.
Background technology
In semiconductor technology industry, its power electronic device, particularly high tension apparatus, in order to improve surface breakdown voltage, need to artificially arrange doped regions, so that the electric field at plane p-n junction near surface place is evenly distributed and weakens.
Above-mentioned doped regions is artificially set at present and adopts RESURF technology more, reduce surface field technology, its principle is: for an epitaxial planar p-n junction, in the time that epitaxy layer thickness is larger, under reverse voltage, epitaxial loayer can not exhaust completely, less in the depletion width of p-n junction surface, the electric field at this place is stronger, thereby surface breakdown voltage is lower; When epitaxy layer thickness hour, epitaxial loayer can exhaust completely, larger in the depletion width of p-n junction surface, thereby the electric field at this place weakens, increase in breakdown voltage; Further, in the time that epitaxy layer thickness is very little, not only epitaxial loayer can exhaust completely, and epitaxial loayer is also depleted greatly, the depletion width that is equivalent to p-n junction surface increases greatly, and electric field weakens greatly, thereby surface breakdown voltage can improve greatly.
Exhaust brought so a kind of effect completely based on epitaxial loayer, therefore just proposed the structure of the RESURF diode that can obviously reduce surface breakdown impact; In this structure, epitaxial loayer is very thin, and doping content is suitable, to ensure that whole epitaxial loayer can exhaust completely under reverse voltage; The core of diode is horizontal n+-p+ knot, and the puncture voltage of this diode approaches puncture voltage in body very much.The method of this reduction surface field, raising puncture voltage is exactly RESURF technology.
Above-mentioned RESURF technology is reaching same withstand voltage in the situation that, because the doping content of its doped regions is constant, so can not accomplish shorter terminal length lower conducting resistance in other words.
Summary of the invention
Object of the present invention is just to provide in order to address the above problem a kind of flat limit structure, manufacturing process and photomask blank of the semiconductor device terminal changing based on doping content.
The present invention is achieved through the following technical solutions above-mentioned purpose:
A kind of flat limit structure of semiconductor device terminal, centered by the mid point on the flat limit of described terminal, the flat limit of described terminal is provided with central area and multiple neighboring area, the quantity that is positioned at described neighboring area in addition, two ends, described central area is identical, the doping content of described neighboring area reduces from inside to outside successively, and the doping content of two the described neighboring areas equidistant with described central area is identical.
Particularly, totally eight of described neighboring areas, tetrad lays respectively at beyond two ends, described central area.
A manufacturing process for the flat limit structure of semiconductor device terminal, comprises the following steps:
(1) prepare N-type substrate or P type substrate: resistivity is 10～200 ohmcms;
(2) oxide layer before N-type substrate or the injection of P type Grown;
(3) spin coating photoresist, and use photomask board to explosure, development, the structure of described photomask blank is: centered by the mid point of described photomask blank, described photomask blank is provided with central area and is positioned at neighboring area in addition, two ends, described central area, and the transparent area area of described neighboring area reduces from inside to outside gradually;
(4) injected and formed the doping of P type or the doping of N-type Impurity injection formation N-type by p type impurity, implantation dosage is 1e12atom/cm2～1e15atom/cm2;
(5) by high-temperature oxydation knot, furnace tube temperature is 850 DEG C～1200 DEG C, and the duration is 30 minutes～300 minutes, growth oxide layer, and activate p type impurity or N-type impurity, form terminal end surface withstand voltage zone;
(6) for NMOS, form N-type substrate source-drain area by N-type Impurity injection, implantation dosage is 1e12atom/cm2～5e15atom/cm2; For PMOS, inject and form P type substrate source-drain area by p type impurity, implantation dosage is 1e12atom/cm2～5e15atom/cm2; N-type substrate or P type substrate are also used as the field cut-off ring at edge, withstand voltage zone;
(7) deposit TEOS is as inter-level dielectric;
(8) sputter or hydatogenesis aluminium, makes Metal Contact electrode, is also used as the inclined to one side field plate of metal zero and cut-off ring field plate, forms complete terminal pressure-resistance structure.
As required, the described photomask blank in described step (3) is one or more in interdigitated, checkerboard type, zigzag, staged, round point shape, polygon and annular.
A kind of photomask blank of manufacturing for semiconductor device terminal, centered by the mid point of described photomask blank, described photomask blank is provided with central area and is positioned at neighboring area in addition, two ends, described central area, and the transparent area area of described neighboring area reduces from inside to outside gradually.
Particularly, described photomask blank is one or more in interdigitated, checkerboard type, zigzag, staged, round point shape, polygon and annular.
Beneficial effect of the present invention is:
The present invention is by being reduced the flat limit of semiconductor device terminal gradually to both sides doping content by centre, the boundary of its surface breakdown voltage eases up, can realize and seamlessly transitting, in the situation that reaching same withstand voltage, can accomplish shorter terminal length or lower conducting resistance, in other words, in the case of same terminal length or conducting resistance, realize higher withstand voltage properties.
Brief description of the drawings
Fig. 1 is the plan structure schematic diagram of the flat limit structure of semiconductor device terminal of the present invention;
Fig. 2 is one of plan structure schematic diagram of photomask blank of the present invention;
Fig. 3 be photomask blank of the present invention plan structure schematic diagram two;
Fig. 4 be photomask blank of the present invention plan structure schematic diagram three;
Fig. 5 be photomask blank of the present invention plan structure schematic diagram four;
Fig. 6 be photomask blank of the present invention plan structure schematic diagram five;
Fig. 7 be photomask blank of the present invention plan structure schematic diagram six;
Fig. 8 be photomask blank of the present invention plan structure schematic diagram seven.
Embodiment
Below in conjunction with accompanying drawing, the invention will be further described:
As shown in Figure 1, the flat limit structure of semiconductor device terminal of the present invention, centered by the mid point on the flat limit 1 of terminal, the flat limit 1 of terminal is provided with central area P0 and multiple neighboring area, multiple neighboring areas are respectively the P1 of first group, P2, P3, the P1 ' of P4 and second group, P2 ', P3 ', P4 ', wherein, P1 and P1 ' are equidistant with P0 respectively, P2 and P2 ' are equidistant with P0 respectively, P3 and P3 ' are equidistant with P0 respectively, P4 and P4 ' are equidistant with P0 respectively, the doping content of neighboring area reduces from inside to outside successively, the doping content of two neighboring areas equidistant with central area P0 is identical, that is: P1=P1 ' <P0, P2=P2 ' <P1, P3=P3 ' <P2, P4=P4 ' <P3.In Fig. 1, also show field cut-off ring 11, the interlayer dielectric layer 12 (being inter-level dielectric) at withstand voltage zone field oxide 10, edge, withstand voltage zone, and metal contact hole and Metal field plate structure 13.
As shown in Fig. 2-Fig. 7, the photomask blank 2 of manufacturing for semiconductor device terminal of the present invention, centered by the mid point of photomask blank 2, photomask blank 2 is provided with central area and is positioned at neighboring area in addition, two ends, central area, and the transparent area area of neighboring area reduces from inside to outside gradually.
Particularly, the transparent area shape of the neighboring area of photomask blank 2 has multiple, introduces respectively below:
As shown in Figure 2, whole transparent area 3 is interdigitated, the transparent area 3 of central area is full impregnated light, the transparent area 3 of neighboring area is isolated into the transparent area 3 of the bar shaped that multiple density from inside to outside reduces gradually by interval, non-transparent area, thereby forms the interdigitated transparent area 3 that area reduces gradually from inside to outside.
As shown in Figure 3, whole transparent area 4 is checkerboard type, and the transparent area 4 of central area is full impregnated light, the transparent area of neighboring area 4 for criss-cross and from inside to outside density reduce gradually, thereby form the checkerboard type transparent area 4 that area reduces gradually from inside to outside.
As shown in Figure 4, whole transparent area 5 is zigzag, and the transparent area 5 of central area is full impregnated light, the transparent area of neighboring area 5 for bar shaped and from inside to outside width reduce gradually, thereby form the zigzag transparent area 5 that area reduces gradually from inside to outside.
As shown in Figure 5, whole transparent area 6 is staged, and the transparent area 6 of central area is full impregnated light, the bar shaped that the transparent area of neighboring area 6 is adjacent arrangement and form from inside to outside stairstepping, thus form the staged transparent area 6 that area reduces gradually from inside to outside.
As shown in Figure 6, whole transparent area 7 is made up of multiple round point shapes transparent area 7, round point shape transparent area 7 areas of central area are large and interconnect, basic is full impregnated light, the round point shape transparent area 7 of neighboring area alternately and from inside to outside density reduces gradually, thereby forms the round point shape transparent area 7 that area reduces gradually from inside to outside.
As shown in Figure 7, whole transparent area 8 is made up of multiple polygons transparent area 8, it in Fig. 7, is hexagon, polygon transparent area 8 areas of central area are large and interconnect, basic is full impregnated light, the polygon transparent area 8 of neighboring area alternately and from inside to outside density reduces gradually, thereby forms the polygon transparent area 8 that area reduces gradually from inside to outside.
As shown in Figure 8, whole transparent area 9 is made up of multiple annulars (flat limit is local is bar shaped) transparent area 9, the transparent area 9 of central area is full impregnated light, multiple annulars of neighboring area (flat limit is local is bar shaped) transparent area 9 alternately and from inside to outside spacing increases gradually, thereby forms the annular transparent area 9 that glazed area reduces gradually from inside to outside.
As required, transparent area can also be the combination in any of above-mentioned shape, as long as meet the requirement that area reduces gradually from inside to outside.
The manufacturing process of the flat limit structure of semiconductor device terminal of the present invention, comprises the following steps:
(1) prepare N-type substrate or P type substrate: resistivity is 10～200 ohmcms;
(2) oxide layer before N-type substrate or the injection of P type Grown;
(3) spin coating photoresist, and use photomask board to explosure, development, the structure of described photomask blank is: centered by the mid point of described photomask blank, described photomask blank is provided with central area and is positioned at neighboring area in addition, two ends, described central area, and the transparent area area of described neighboring area reduces from inside to outside gradually;
(4) injected and formed the doping of P type or the doping of N-type Impurity injection formation N-type by p type impurity, implantation dosage is 1e12atom/cm2～1e15atom/cm2;
(5) by high-temperature oxydation knot, furnace tube temperature is 850 DEG C～1200 DEG C, and the duration is 30 minutes～300 minutes, growth oxide layer, and activate p type impurity or N-type impurity, form terminal end surface withstand voltage zone;
(6) for NMOS, form N-type substrate source-drain area by N-type Impurity injection, implantation dosage is 1e12atom/cm2～5e15atom/cm2; For PMOS, inject and form P type substrate source-drain area by p type impurity, implantation dosage is 1e12atom/cm2～5e15atom/cm2; N-type substrate or P type substrate are also used as the field cut-off ring at edge, withstand voltage zone;
(7) deposit TEOS is as inter-level dielectric;
(8) sputter or hydatogenesis aluminium, makes Metal Contact electrode, is also used as the inclined to one side field plate of metal zero and cut-off ring field plate, forms complete terminal pressure-resistance structure.
In actual manufacture, on the basis of above-mentioned eight steps, also have following continuous step:
(9) as required make semiconductor device and build, insert essential processing step, as CMOS, VDMOS, IGBT, DIODE, JFET, BJT etc.
Illustrate: the part that above-mentioned steps (9) is conventional manufacturing process is not innovative technology of the present invention.
Above-described embodiment is preferred embodiment of the present invention; it is not the restriction to technical solution of the present invention; as long as the technical scheme that can realize on the basis of above-described embodiment without creative work, all should be considered as falling within the scope of the rights protection of patent of the present invention.
Claims (6)
1. the flat limit structure of a semiconductor device terminal, it is characterized in that: centered by the mid point on the flat limit of described terminal, the flat limit of described terminal is provided with central area and multiple neighboring area, the quantity that is positioned at described neighboring area in addition, two ends, described central area is identical, the doping content of described neighboring area reduces from inside to outside successively, and the doping content of two the described neighboring areas equidistant with described central area is identical.
2. the flat limit structure of semiconductor device terminal according to claim 1, is characterized in that: totally eight of described neighboring areas, tetrad lays respectively at beyond two ends, described central area.
3. a manufacturing process for the flat limit structure of semiconductor device terminal as claimed in claim 1 or 2, is characterized in that: comprise the following steps:
(1) prepare N-type substrate or P type substrate: resistivity is 10～200 ohmcms;
(2) oxide layer before N-type substrate or the injection of P type Grown;
(3) spin coating photoresist, and use photomask board to explosure, development, the structure of described photomask blank is: centered by the mid point of described photomask blank, described photomask blank is provided with central area and is positioned at neighboring area in addition, two ends, described central area, and the transparent area area of described neighboring area reduces from inside to outside gradually;
(4) injected and formed the doping of P type or the doping of N-type Impurity injection formation N-type by p type impurity, implantation dosage is 1e12atom/cm2～1e15atom/cm2;
(5) by high-temperature oxydation knot, furnace tube temperature is 850 DEG C～1200 DEG C, and the duration is 30 minutes～300 minutes, growth oxide layer, and activate p type impurity or N-type impurity, form terminal end surface withstand voltage zone;
(6) for NMOS, form N-type substrate source-drain area by N-type Impurity injection, implantation dosage is 1e12atom/cm2～5e15atom/cm2; For PMOS, inject and form P type substrate source-drain area by p type impurity, implantation dosage is 1e12atom/cm2～5e15atom/cm2; N-type substrate or P type substrate are also used as the field cut-off ring at edge, withstand voltage zone;
(7) deposit TEOS is as inter-level dielectric;
(8) sputter or hydatogenesis aluminium, makes Metal Contact electrode, is also used as the inclined to one side field plate of metal zero and cut-off ring field plate, forms complete terminal pressure-resistance structure.
4. the manufacturing process of the flat limit structure of semiconductor device terminal according to claim 3, is characterized in that: the described photomask blank in described step (3) is one or more in interdigitated, checkerboard type, zigzag, staged, round point shape, polygon and annular.
5. a photomask blank of manufacturing for semiconductor device terminal, it is characterized in that: centered by the mid point of described photomask blank, described photomask blank is provided with central area and is positioned at neighboring area in addition, two ends, described central area, and the transparent area area of described neighboring area reduces from inside to outside gradually.
6. the photomask blank of manufacturing for semiconductor device terminal according to claim 5, is characterized in that: described photomask blank is one or more in interdigitated, checkerboard type, zigzag, staged, round point shape, polygon and annular.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410326054.7A CN104112770A (en) | 2014-07-08 | 2014-07-08 | Flat-edge structure of semiconductor device terminal, manufacturing process and optical mask plate |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410326054.7A CN104112770A (en) | 2014-07-08 | 2014-07-08 | Flat-edge structure of semiconductor device terminal, manufacturing process and optical mask plate |
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| CN104112770A true CN104112770A (en) | 2014-10-22 |
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| CN201410326054.7A Pending CN104112770A (en) | 2014-07-08 | 2014-07-08 | Flat-edge structure of semiconductor device terminal, manufacturing process and optical mask plate |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105572973A (en) * | 2015-12-23 | 2016-05-11 | 南京中电熊猫液晶显示科技有限公司 | Mask board and photo-alignment method |
| CN107994068A (en) * | 2017-12-20 | 2018-05-04 | 上海南麟电子股份有限公司 | A kind of junction of semiconductor device termination extension structure and preparation method |
| CN109100914A (en) * | 2018-06-29 | 2018-12-28 | 武汉华星光电半导体显示技术有限公司 | Mask plate and flexible display panels |
-
2014
- 2014-07-08 CN CN201410326054.7A patent/CN104112770A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105572973A (en) * | 2015-12-23 | 2016-05-11 | 南京中电熊猫液晶显示科技有限公司 | Mask board and photo-alignment method |
| CN105572973B (en) * | 2015-12-23 | 2018-10-09 | 南京中电熊猫液晶显示科技有限公司 | A kind of mask plate and light alignment method |
| CN107994068A (en) * | 2017-12-20 | 2018-05-04 | 上海南麟电子股份有限公司 | A kind of junction of semiconductor device termination extension structure and preparation method |
| CN109100914A (en) * | 2018-06-29 | 2018-12-28 | 武汉华星光电半导体显示技术有限公司 | Mask plate and flexible display panels |
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Application publication date: 20141022 |