CN104319289A - NLDMOS device and manufacture method thereof - Google Patents
NLDMOS device and manufacture method thereof Download PDFInfo
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- CN104319289A CN104319289A CN201410521717.0A CN201410521717A CN104319289A CN 104319289 A CN104319289 A CN 104319289A CN 201410521717 A CN201410521717 A CN 201410521717A CN 104319289 A CN104319289 A CN 104319289A
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- 238000000034 method Methods 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 230000005516 deep trap Effects 0.000 claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 39
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 30
- 239000010703 silicon Substances 0.000 claims abstract description 30
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 41
- 229910052760 oxygen Inorganic materials 0.000 claims description 41
- 239000001301 oxygen Substances 0.000 claims description 41
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 19
- 229920005591 polysilicon Polymers 0.000 claims description 19
- 125000006850 spacer group Chemical group 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 3
- 238000000605 extraction Methods 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 210000003323 beak Anatomy 0.000 abstract description 3
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 108091006146 Channels Proteins 0.000 description 14
- 238000005516 engineering process Methods 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 5
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses an NLDMOS device. An N-type deep trap is formed at the left portion of a P-type silicon substrate; a P trap is formed in the N-type deep trap; an N trap is formed at the right portion of the P-type silicon substrate; and a P-type silicon substrate interval zone is arranged between the N-type deep trap and the N trap. The invention also discloses a manufacture method of the NLDMOS device. According to the NLDMOS device and the manufacture method thereof, the deep N trap wraps the P trap so as to enable the P trap to be isolated from the substrate; the dimension of the N-type deep trap is reduced to the P trap which is taken as the channel zone of an NLDMOS, it is ensured that the P trap is isolated from the substrate, and the N-type deep trap is not formed at the N trap which is taken as the drifting zone of the NLDMOS, such that the N-type doping concentration in the drifting zone is decreased, and accordingly, the off-BV of the device is increased; and the dimension of the N trap is increased to the portion between the N-type deep trap and a beak, and the N-type doping concentration below a gate oxide layer is increased, such that the on-BV is increased, and at the same time, it is ensured that the on-resistance is not too large.
Description
Technical field
The present invention relates to semiconductor technology, particularly a kind of NLDMOS device and manufacture method thereof.
Background technology
LDMOS (Laterally Diffused Metal Oxide Semiconductor) due to have high pressure resistant, high current drive capability, extremely low power dissipation and can with the advantage such as CMOS is integrated, be widely adopted in electric power management circuit at present.
Existing a kind of 40V isolated form NLDMOS (N-type Laterally Diffused Metal Oxide Semiconductor) device, as shown in Figure 1, P-type silicon substrate 101 is formed with N-type deep trap 102, N-type deep trap 102 left part is formed with P trap 105, and right part is formed with N trap 104; P trap 105 is with there being N-type deep trap 102 spacer region between N trap 104, and P trap 105 right part, N trap 104 left part and P trap 105 are formed with polysilicon gate 107 with above N-type deep trap 102 spacer region between N trap 104; Polysilicon gate 107 is isolated by gate oxide 106 with between the N-type deep trap 102 spacer region left part between N trap 104 with P trap 105 right part, P trap 105, and polysilicon gate 107 is isolated by field oxygen 103 with between the N-type deep trap 102 spacer region right part between N trap 104 with N trap 104 left part, P trap 105; P trap 105 is formed on a heavily doped P-type district 109 and heavily doped N-type district 112, N trap 104 right part and is formed with a heavily doped N-type district 108; Heavily doped P-type district 109 on P trap 105 is as P trap 105 exit, and the heavily doped N-type district 108 on the heavily doped N-type district 112 on P trap 105, N trap 104 right part is respectively as the source region of NLDMOS device, drain region exit.
NLDMOS device shown in Fig. 1, N-type deep trap 102 and N trap 104 are owing to sometimes needing to share with other devices, and doping content is immutable, and N-type deep trap 102 is denseer and darker, not easily exhaust, puncture voltage not easily improves, and can only improve device electric breakdown strength by change device size and structure.
Summary of the invention
The technical problem to be solved in the present invention improves the puncture voltage that can adopt the NLDMOS device of BCD manufacture technics.
For solving the problems of the technologies described above, NLDMOS device provided by the invention, its structure is: be formed with N-type deep trap at P-type silicon substrate left part;
Described N-type deep trap is formed with P trap;
N trap is formed at described P-type silicon substrate right part;
Described N-type deep trap has P-type silicon substrate spacer region with between described N trap;
Described P trap, middle part is formed with field, channel region oxygen;
P trap on the left of the oxygen of field, described channel region is formed with a heavily doped P-type district, the P trap on the right side of the oxygen of field, described channel region is formed with a heavily doped N-type district;
Field, drift region oxygen is formed in the middle part of described N trap; N trap on the right side of the oxygen of field, drift region is formed with a heavily doped N-type district;
Silicon chip between described heavily doped N-type district on P trap to field, described drift region oxygen is formed with gate oxide;
Polysilicon gate is formed in above described gate oxide and above the oxygen left part of field, described drift region;
Heavily doped P-type district on described P trap is as P trap exit;
Heavily doped N-type district on described P trap, the heavily doped N-type district on N trap are respectively as the source region of NLDMOS device, drain region exit;
The N-type doping content of described N trap, is greater than the N-type doping content of N-type deep trap, and is less than the N-type doping content in heavily doped N-type district;
The P type doping content of described P trap, is greater than the P type doping content of P-type silicon substrate, and is less than the P type doping content in heavily doped P-type district.
Preferably, described N-type deep trap is less than 1 μm with the P-type silicon substrate spacer region minimum widith between described N trap.
For solving the problems of the technologies described above, the manufacture method of NLDMOS device provided by the invention, comprises following processing step:
One, on P type substrate left part, N-type deep trap is formed by N-type ion implantation;
Two, utilize active area photoetching, open an oxygen region, etching Chang Yang district, raw long field oxide, N-type deep trap is formed field, channel region oxygen, P type substrate right part is formed field, drift region oxygen;
Three, trap injection zone is opened in photoetching, and below the oxygen of field, channel region and in the N-type deep trap of the left and right sides, implanting p-type foreign ion forms P trap, injects N-type impurity ion and form N trap below the oxygen of field, drift region and in the P type substrate of the left and right sides;
Described N trap has P-type silicon substrate spacer region with between described N-type deep trap;
Four, on silicon chip, gate oxide is grown by thermal oxidation process, depositing polysilicon; Then carry out polysilicon gate etching, form polysilicon gate;
The left part of polysilicon gate is positioned at above P trap right part, and right part is positioned at above N trap left part;
Five, carry out source and drain ion implantation, the P trap of the Chang Yang left and right sides, channel region is formed a heavily doped P-type district and a heavily doped N-type district respectively, the N trap on the right side of the oxygen of field, drift region is formed with a heavily doped N-type district;
Six, form contact hole by contact hole technique to connect, by contact hole and metal wire extraction electrode, complete the making of this NLDMOS device.
NLDMOS device of the present invention and manufacture method thereof, dark type N trap bag P trap realizes P trap and substrate isolation, reduce N-type deep trap size to the P trap place as the channel region of NLDMOS, and ensure P trap and substrate isolation, and N-type deep trap is not formed at the N trap place of the drift region as NLDMOS, drift region N-type doping content is reduced, thus the shutoff puncture voltage (off-BV) of device is increased; Increase N trap size between N-type deep trap and beak, under making gate oxide, N-type doping content increases, thus conducting puncture voltage (on-BV) is increased, and ensures that conducting resistance is unlikely to excessive simultaneously.
Accompanying drawing explanation
In order to be illustrated more clearly in technical scheme of the present invention, below the accompanying drawing that will use required for the present invention is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is existing a kind of 40V isolated form NLDMOS device sectional view;
Fig. 2 is NLDMOS device one embodiment sectional view of the present invention;
Fig. 3 is the device sectional view after NLDMOS manufacture method one embodiment n type buried layer of the present invention injects;
Fig. 4 is the device sectional view after NLDMOS manufacture method one embodiment field of the present invention oxygen is formed;
Fig. 5 is the device sectional view after NLDMOS manufacture method one embodiment N trap of the present invention and P trap are formed;
Fig. 6 is the device sectional view after NLDMOS manufacture method one embodiment polysilicon gate of the present invention is formed;
Fig. 7 is the device sectional view after NLDMOS manufacture method one embodiment trap of the present invention injects.
Embodiment
Below in conjunction with accompanying drawing, carry out clear, complete description to the technical scheme in the present invention, obviously, described embodiment is a part of embodiment of the present invention, instead of whole embodiments.Based on the embodiment in the present invention, other embodiments all that those of ordinary skill in the art obtain under the prerequisite not making creative work, all belong to the scope of protection of the invention.
Embodiment one
NLDMOS (N-type Laterally Diffused Metal Oxide Semiconductor) device, as shown in Figure 2, is formed with N-type deep trap 102 at P-type silicon substrate 101 left part;
Described N-type deep trap 102 is formed with P trap 105;
N trap 104 is formed at described P-type silicon substrate 101 right part;
Described N-type deep trap 102 has P-type silicon substrate 101 spacer region with between described N trap 104;
Described P trap 105, middle part is formed with field, channel region oxygen 114;
P trap 105 on the left of field, described channel region oxygen 114 is formed with a heavily doped P-type district 109, the P trap 105 on the right side of the oxygen of field, described channel region is formed with a heavily doped N-type district 112;
Field, drift region oxygen 103 is formed in the middle part of described N trap 104; N trap 104 on the right side of field, drift region oxygen 103 is formed with a heavily doped N-type district 108;
Silicon chip between described heavily doped N-type district 112 on P trap 105 to field, described drift region oxygen 103 is formed with gate oxide 106;
Polysilicon gate 107 is formed in above described gate oxide 106 and above oxygen 103 left part of field, described drift region;
Heavily doped P-type district 109 on described P trap 105 is as P trap 105 exit;
Heavily doped N-type district 112 on described P trap 105, the heavily doped N-type district 108 on N trap 104 are respectively as the source region of NLDMOS device, drain region exit;
The N-type doping content of described N trap 104, is greater than the N-type doping content of N-type deep trap 102, and is less than the N-type doping content in heavily doped N-type district 108,112;
The P type doping content of described P trap 105, is greater than the P type doping content of P-type silicon substrate 101, and is less than the P type doping content in heavily doped P-type district 109.
Preferably, described N-type deep trap 102 is less than 1 μm with the P-type silicon substrate 101 spacer region minimum widith between described N trap 104.
NLDMOS (N-type Laterally Diffused Metal Oxide Semiconductor) device of embodiment one, dark type N trap 102 wraps P trap and realizes P trap 105 and isolate with substrate 101, reduce N-type deep trap 102 size to P trap 105 place as the channel region of NLDMOS, and ensure that P trap 105 and substrate 101 are isolated, and N-type deep trap is not formed at N trap 104 place of the drift region as NLDMOS, drift region N-type doping content is reduced, thus the shutoff puncture voltage (off-BV) of device is increased; Increase N trap 104 size to (N-type deep trap 102 can be less than 1 μm with the interval between N trap 104) between N-type deep trap 102 and beak, gate oxide 106 times N-type doping contents are increased, thus conducting puncture voltage (on-BV) is increased, ensure that conducting resistance is unlikely to excessive simultaneously.
The NLDMOS device of embodiment one, by changing device architecture, reach make shutoff puncture voltage (off-BV), object that conducting puncture voltage (on-BV) all improves, and its fabrication process condition can share with the CMOS technology of BCD (bipolar CMOS DMOS) platform, without the need to additionally adding version, provide cost savings.
Embodiment two
The manufacture method of the NLDMOS device of embodiment one, mainly comprises following processing step:
One, on P type substrate 101 left part, N-type deep trap 102 is formed by N-type ion implantation, as shown in Figure 3;
Two, utilize active area photoetching, open an oxygen region, etching Chang Yang district, raw long field oxide, N-type deep trap 102 is formed field, channel region oxygen 114, P type substrate 101 right part forms field, drift region oxygen 103, as shown in Figure 4;
Three, trap injection zone is opened in photoetching, below the oxygen of field, channel region 114 and the left and right sides N-type deep trap 102 in implanting p-type foreign ion form P trap 105, inject N-type impurity ion below field, drift region oxygen 103 and in the P type substrate 101 of the left and right sides and form N trap 104; Described N trap 104 has P-type silicon substrate 101 spacer region with between described N-type deep trap 102, as shown in Figure 5;
Four, on silicon chip, by thermal oxidation process growth gate oxide 106, depositing polysilicon; Then carry out polysilicon gate etching, form polysilicon gate 107;
The left part of polysilicon gate 107 is positioned at above P trap 105 right part, and right part is positioned at above N trap 104 left part, as shown in Figure 6;
Five, conventional source and drain ion implantation is optionally carried out, the P trap 105 of the Chang Yang114 left and right sides, channel region is formed heavily doped P-type district 109 and a heavily doped N-type district 112 respectively, N trap 104 on the right side of field, drift region oxygen 103 is formed with a heavily doped N-type district 108, as shown in Figure 7;
Six, form contact hole by traditional contact hole technique to connect, by contact hole 110 and metal wire 111 extraction electrode;
Heavily doped P-type district 109 on P trap 105 is as P trap 105 exit;
Heavily doped N-type district 112 on P trap 105, the heavily doped N-type district 108 on N trap 104, respectively as the source region of NLDMOS device, drain region exit, finally complete the making of this NLDMOS device, as shown in Figure 2.
Preferably, described N trap 104 is less than 1 μm with the P-type silicon substrate 101 spacer region minimum widith between described N-type deep trap 102.
The manufacture method of the NLDMOS device of embodiment two, the P type channel region of the NLDMOS device manufactured is made up of the P trap in CMOS technology, N-type drift region is made up of the N trap in CMOS technology, device electric breakdown strength is high, and BCD (bipolar CMOS DMOS) technique can be adopted, without the need to additionally adding version, cost is low.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (4)
1. a NLDMOS device, is characterized in that, is formed with N-type deep trap at P-type silicon substrate left part;
Described N-type deep trap is formed with P trap;
N trap is formed at described P-type silicon substrate right part;
Described N-type deep trap has P-type silicon substrate spacer region with between described N trap;
Described P trap, middle part is formed with field, channel region oxygen;
P trap on the left of the oxygen of field, described channel region is formed with a heavily doped P-type district, the P trap on the right side of the oxygen of field, described channel region is formed with a heavily doped N-type district;
Field, drift region oxygen is formed in the middle part of described N trap; N trap on the right side of the oxygen of field, drift region is formed with a heavily doped N-type district;
Silicon chip between described heavily doped N-type district on P trap to field, described drift region oxygen is formed with gate oxide;
Polysilicon gate is formed in above described gate oxide and above the oxygen left part of field, described drift region;
Heavily doped P-type district on described P trap is as P trap exit;
Heavily doped N-type district on described P trap, the heavily doped N-type district on N trap are respectively as the source region of NLDMOS device, drain region exit;
The N-type doping content of described N trap, is greater than the N-type doping content of N-type deep trap, and is less than the N-type doping content in heavily doped N-type district;
The P type doping content of described P trap, is greater than the P type doping content of P-type silicon substrate, and is less than the P type doping content in heavily doped P-type district.
2. NLDMOS device according to claim 1, is characterized in that,
Described N-type deep trap is less than 1 μm with the P-type silicon substrate spacer region minimum widith between described N trap.
3. a manufacture method for NLDMOS device, is characterized in that, comprises following processing step:
One, on P type substrate left part, N-type deep trap is formed by N-type ion implantation;
Two, utilize active area photoetching, open an oxygen region, etching Chang Yang district, raw long field oxide, N-type deep trap is formed field, channel region oxygen, P type substrate right part is formed field, drift region oxygen;
Three, trap injection zone is opened in photoetching, and below the oxygen of field, channel region and in the N-type deep trap of the left and right sides, implanting p-type foreign ion forms P trap, injects N-type impurity ion and form N trap below the oxygen of field, drift region and in the P type substrate of the left and right sides;
Described N trap has P-type silicon substrate spacer region with between described N-type deep trap;
Four, on silicon chip, gate oxide is grown by thermal oxidation process, depositing polysilicon; Then carry out polysilicon gate etching, form polysilicon gate;
The left part of polysilicon gate is positioned at above P trap right part, and right part is positioned at above N trap left part;
Five, carry out source and drain ion implantation, the P trap of the Chang Yang left and right sides, channel region is formed a heavily doped P-type district and a heavily doped N-type district respectively, the N trap on the right side of the oxygen of field, drift region is formed with a heavily doped N-type district;
Six, form contact hole by contact hole technique to connect, by contact hole and metal wire extraction electrode, complete the making of this NLDMOS device.
4. the manufacture method of NLDMOS device according to claim 3, is characterized in that,
Described N trap is less than 1 μm with the P-type silicon substrate spacer region minimum widith between described N-type deep trap.
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| CN201410521717.0A CN104319289A (en) | 2014-09-30 | 2014-09-30 | NLDMOS device and manufacture method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410521717.0A CN104319289A (en) | 2014-09-30 | 2014-09-30 | NLDMOS device and manufacture method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104659100A (en) * | 2015-02-10 | 2015-05-27 | 上海华虹宏力半导体制造有限公司 | Isolated NLDMOS device and manufacturing method thereof |
| CN113611733A (en) * | 2021-07-07 | 2021-11-05 | 上海华虹宏力半导体制造有限公司 | Isolated NLDMOS device and manufacturing method thereof |
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| CN113611733B (en) * | 2021-07-07 | 2024-01-23 | 上海华虹宏力半导体制造有限公司 | Isolation NLDMOS device and manufacturing method thereof |
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Application publication date: 20150128 |