CN107785365A - It is integrated with the device and its manufacture method of junction field effect transistor - Google Patents
It is integrated with the device and its manufacture method of junction field effect transistor Download PDFInfo
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- 230000005669 field effect Effects 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 42
- 229910052751 metal Inorganic materials 0.000 claims abstract description 42
- 150000001875 compounds Chemical class 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 229920005591 polysilicon Polymers 0.000 claims description 14
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 13
- 229910052760 oxygen Inorganic materials 0.000 claims description 13
- 239000001301 oxygen Substances 0.000 claims description 13
- 230000008447 perception Effects 0.000 claims description 13
- 238000002347 injection Methods 0.000 claims description 12
- 239000007924 injection Substances 0.000 claims description 12
- 238000001259 photo etching Methods 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 230000000903 blocking effect Effects 0.000 claims description 8
- 239000007943 implant Substances 0.000 claims description 8
- 238000002513 implantation Methods 0.000 claims description 7
- 150000002739 metals Chemical class 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 5
- 238000000407 epitaxy Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 229910044991 metal oxide Inorganic materials 0.000 claims 1
- 150000004706 metal oxides Chemical class 0.000 claims 1
- 239000002131 composite material Substances 0.000 abstract description 6
- 230000015556 catabolic process Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
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- 239000002019 doping agent Substances 0.000 description 2
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- 241000047703 Nonion Species 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 210000000080 chela (arthropods) Anatomy 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003834 intracellular effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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Abstract
The present invention relates to a kind of device and its manufacture method for being integrated with junction field effect transistor, the JFET areas of the device include：JFET source electrodes, it is the first conduction type；The metal electrode of JFET source electrodes, it is formed on the JFET source electrodes and the JFET source contacts；Compound well region structure, for the second conduction type and in the first conductivity regions, the second trap including the first trap and in the first trap, the ion concentration of second trap is more than the ion concentration of the first trap, compound well region structure is in the both sides of JFET source electrodes respectively formed with one, and JFET source electrodes are extended laterally into the first trap and the second trap；JFET metal gates, in the compound well region structure of JFET source electrodes both sides.The compound well region that the present invention is formed using the first trap and the second trap forms composite channel, enhances raceway groove and exhausts ability, strengthens pinch-off voltage stability.Accurate adjustment pinch-off voltage size, different circuit application scenarios can be met by adjusting the distance of composite channel simultaneously.
Description
Technical field
The present invention relates to semiconductor fabrication, more particularly to a kind of device for being integrated with junction field effect transistor,
Further relate to a kind of manufacture method for the device for being integrated with junction field effect transistor.
Background technology
Integrated high voltage junction field effect transistor (the Junction Field-Effect on high-pressure process platform
Transistor, JFET) for nowadays smart-power IC field a kind of advanced exploitation with conceiving, it can be greatly promoted
The ON state performance of longitudinal power device, and significantly reduce chip area, meet the main flow of current smart power device manufacture
Trend.
The high pressure of traditional structure, which integrates JFET, has better simply technique to realize, but the unstable and tune of its pinch-off voltage
The control property characteristic such as poor limits its large-scale application in intelligent power integration field.
The content of the invention
Based on this, it is necessary to for the problem of traditional JFET pinch-off voltages are unstable and control is poor, there is provided a kind of
It is integrated with the device of junction field effect transistor.
A kind of device for being integrated with junction field effect transistor, the device include JFET areas and power device area, are located at
The drain electrode of first conduction type at the device back side, and led located at the drain electrode towards first on the positive face of the device
The drain electrode and the first conductivity regions are shared by electric class area, the JFET areas and power device area；The JFET areas also include：
JFET source electrodes, it is the first conduction type；The metal electrode of JFET source electrodes, it is formed on the JFET source electrodes and the JFET source electrodes
Contact；Compound well region structure, is the second conduction type and in first conductivity regions, including the first trap and positioned at institute
The second trap in the first trap is stated, the ion concentration of second trap is more than the ion concentration of first trap, the compound well region
Structure is in the both sides of the JFET source electrodes respectively formed with one, and the JFET source electrodes extend laterally into first trap and
In two traps；First conduction type and the second conduction type are opposite conduction type；JFET metal gates, located at described
In the compound well region structure of JFET source electrodes both sides.
In one of the embodiments, the JFET areas and power device area intersection are made formed with first trap
For the isolation in JFET areas and power device area.
In one of the embodiments, the device is vertical DMOS field-effect transistor
VDMOS。
In one of the embodiments, the power device area also includes grid, the second trap, the in second trap
The clamper area of the VDMOS source electrodes of one conduction type and the second conduction type located at the second trap bottom.
In one of the embodiments, VDMOS is also included formed with groove, the power device area in each second trap
Source metal contacts, in each second trap and ohmic contact regions of the bottom contact position of the groove formed with the second conduction type,
VDMOS source metals contact is filled in the groove in the power device area, through the VDMOS source electrodes and extends to institute
Ohmic contact regions are stated, the JFET metal gates are filled in the groove in the JFET areas and extend to the ohmic contact regions,
The ion concentration of the ohmic contact regions is more than the ion concentration of second trap.
In one of the embodiments, in second trap in the power device area, the VDMOS source electrodes and described ohm
The non-clamper perception switch region of the second conduction type is also formed between contact zone, the ion of the non-clamper perception switch region is dense
Ion concentration of the degree more than second trap.
In one of the embodiments, first conduction type is N-type, and second conduction type is p-type, described
One conductivity regions are N-type epitaxy layer.
It there is a need to and a kind of manufacture method for the device for being integrated with junction field effect transistor is provided.
A kind of manufacture method for the device for being integrated with junction field effect transistor, the device include JFET areas and power device
Part area, methods described include：The substrate of the first conduction type is provided, formed with the first conductivity regions on the substrate；It is described
First conduction type and the second conduction type are opposite conduction type；The second conduction type is injected into the first conductivity regions
Ion and push away trap, form the first trap in first conductivity regions；Successively growth field oxygen layer and grid oxide layer, described the
One conductivity regions surface form polysilicon layer, inject the ion of the second conduction type to first conductivity regions and push away trap
Multiple second traps are formed, second trap positioned at the JFET areas is respectively formed in different first traps；To described
The ion of the first conduction type is injected in second trap in power device area, forms power device source electrode；To the two of the JFET areas
The ion of the first conduction type is injected between adjacent second trap, forms JFET source electrodes；Photoetching simultaneously etches contact hole, deposits metal
Layer, is inserted in the contact hole, respectively the gold of the metal electrode of formation JFET source electrodes, JFET metal gates and power device source electrode
Category contact.
In one of the embodiments, described the step of forming the first trap in first conductivity regions, it is included in
The JFET areas and power device area intersection forms isolation of first trap as JFET areas and power device area.
In one of the embodiments, it is described to inject the ion of the second conduction type to first conductivity regions and push away
Trap was formed in the step of multiple second traps, was to be injected using the field oxygen layer and polysilicon layer as mask.
In one of the embodiments, the step of formation power device source electrode and the step of the formation JFET source electrodes
Between, in addition to step：The surface of formation implant blocking layer, the field oxygen layer and polysilicon layer is also superimposed with the injection and stopped
Layer；The ion of the second conduction type is injected into second trap in the power device area, with described in second trap
The non-clamper perception switch region formed below of power device source electrode, Implantation Energy are more than described to the second of the power device area
The Implantation Energy for the step of ion of the first conduction type is injected in trap, it is superimposed with the field oxygen layer and polycrystalline of the implant blocking layer
Silicon layer is by the ion barrier of the second conduction type of injection.
In one of the embodiments, the photoetching and the step of etch contact hole before, be additionally included in each described second
In trap the step of etching groove, and to second trap inject the second conduction type ion, in every one second trap with institute
The step of stating the ohmic contact regions of the second conduction type of bottom contact position formation of groove, inserts in second trap in the JFET areas
Groove metal level, form the JFET metal gates, the metal for the groove inserted in second trap in the power device area
Layer, form the metal contact of the power device source electrode.
In one of the embodiments, first conduction type is N-type, and second conduction type is p-type, described
One conductivity regions are N-type epitaxy layer, and the power device is vertical DMOS field-effect transistor
VDMOS。
The above-mentioned device and its manufacture method for being integrated with junction field effect transistor, formed using the first trap and the second trap
Compound well region forms composite channel, enhances raceway groove and exhausts ability, strengthens pinch-off voltage stability.Regulation can be passed through simultaneously
The distance of composite channel, accurate adjustment pinch-off voltage size, meet different circuit application scenarios.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, embodiment will be described below
In the required accompanying drawing used be briefly described, it should be apparent that, drawings in the following description be only the present invention some
Embodiment, for those of ordinary skill in the art, on the premise of not paying creative work, can also be attached according to these
Figure obtains the accompanying drawing of other embodiment.
Fig. 1 is the cross-sectional view that a kind of traditional high pressure integrates JFET；
Fig. 2 is the cross-sectional view for the device that junction field effect transistor is integrated with an embodiment；
Fig. 3 is the schematic diagram for the composite channel that JFET areas influence pinch-off voltage；
Fig. 4 be different adjacent second traps spacing x under device Voff situation of change analog result；
Fig. 5 is the flow chart of the manufacture method for the device that junction field effect transistor is integrated with an embodiment；
Fig. 6 a~6e are that the device manufactured using the manufacture method for the device for being integrated with junction field effect transistor is being manufactured
During cross-sectional view.
Embodiment
For the ease of understanding the present invention, the present invention is described more fully below with reference to relevant drawings.In accompanying drawing
Give the preferred embodiment of the present invention.But the present invention can realize in many different forms, however it is not limited to this paper institutes
The embodiment of description.On the contrary, the purpose for providing these embodiments is made to the disclosure more thorough and comprehensive.
Unless otherwise defined, all of technologies and scientific terms used here by the article is with belonging to technical field of the invention
The implication that technical staff is generally understood that is identical.Term used in the description of the invention herein is intended merely to description tool
The purpose of the embodiment of body, it is not intended that in the limitation present invention.Term as used herein " and/or " include one or more phases
The arbitrary and all combination of the Listed Items of pass.
It should be noted that when element is referred to as " being fixed on " another element, it can be directly on another element
Or there may also be element placed in the middle.When an element is considered as " connection " another element, it can be directly connected to
To another element or it may be simultaneously present centering elements.Term as used herein " vertical ", " horizontal ", " on ",
" under ", "left", "right" and similar statement for illustrative purposes only.
Semiconductor applications vocabulary used herein is the technical words that those skilled in the art commonly use, such as p-type
And N-type impurity, to distinguish doping concentration, P+ type is easily represented to the p-type of heavy dopant concentration, the P of doping concentration during p-type represents
Type, P-type represent the p-type that concentration is lightly doped, and N+ types represent the N-type of heavy dopant concentration, the N-type of doping concentration, N- during N-type represents
Type represents the N-type that concentration is lightly doped.
A kind of traditional integrated high voltage junction field effect transistor (Junction Field-Effect Transistor,
JFET vertical DMOS field-effect transistor (Vertical Double-diffused)
MOSFET, VDMOS) structure it is as shown in Figure 1.Including grid 101, source electrode 102, high pressure p-well 103, body contact 104, N-type extension
105 and N+ of layer contacts 106.
When VDMOS is in open stage, electric current flows through JFET from bottom drain terminal, is flowed out from source2.Work as source2
Voltage Vg2 that is upper plus becoming larger, while also add same voltage Vg1 on grid gate, work as Vg2>During pinch-off voltage Voff, JFET
Depletion layer blocked electric current, i.e., there occurs pinch off.Now Vg1>Vth, VDMOS are opened, and complete an opening process.JFET
Absorb mutation currents of the DMOS in Miller platform herein, allow start it is more gentle, electric current can convert into approximately linear, institute
There is very remarkable effect to device stability lifting in start-up course with JFET.Power device is integrated on its technique platform and posted
Raw JFET is then more advantageous.
In the JFET device application of reality, its pinch-off voltage needs stronger stability and Modulatory character, particularly
In high pressure field.Above-mentioned traditional structure typically by the use of autoregistration p-type inject substrate as p-type pinch off substrate, due to VDMOS member
Its longitudinal junction depth of the P type substrate of born of the same parents (cell) is very shallow, typically only 3~5 microns, therefore JFET longitudinal channel is very short.Simultaneously
Because the channel concentration that High temperature diffusion is formed is also uneven, so pinch-off voltage is very unstable.It can be learnt by emulation and work as drain terminal
When voltage changes from 50V to 100V, pinch-off voltage Voff can become greatly to 20V from 11V；Integrated simultaneously with conventional high-tension technique
JFET, because high pressure p-well concentration can also compare fixation so that its pinch-off voltage Modulatory character is poor.But in actual circuit application
In, the pinch-off voltage gear that different circuits needs can be different, therefore can not meet actual demand.
Fig. 2 is the cross-sectional view for the device that junction field effect transistor is integrated with an embodiment, in this implementation
In example, definition N-type is the first conduction type, and p-type is the second conduction type, power device VDMOS.It is as shown in Figure 2, by device
Part is divided into JFET areas and VDMOS areas by structure, and JFET areas and VDMOS areas, which share, is located at the device back side (i.e. face directed downwardly in Fig. 2)
N-type drain electrode 201, and the N-type region 214 located at drain electrode 201 positive (i.e. faces in Fig. 2 upward).In the present embodiment, drain
201 be that N+ drains, and N-type region 214 is N- epitaxial layers (can also directly use N-type substrate in other embodiments).
In the present embodiment, JFET areas include JFET source electrodes 208, the metal electrode 212 of JFET source electrodes, JFET metal gates
213 and the compound well region structure that is made up of the first trap 202 and the second trap 205.
In the present embodiment, compound well region nodes are configured in N- epitaxial layers, wherein the first trap 202 is P-well, the second trap
205 be the high pressure p-well in the first trap 202.The ion concentration of second trap 205 is more than the ion concentration of the first trap 202.One
Individual first intracellular, the both sides of N+ JFET source electrodes 208 are respectively formed with a compound well region structure, and JFET source electrodes 208 extend laterally
Into in the first trap 202 and the second trap 205.Second trap 205 contacts as the N-type of device, forms conducting channel.JFET source electrodes
Metal electrode 212 is formed on JFET source electrodes 208, the source contact as JFET source electrodes 208.JFET metal gates 213 are located at
In compound well region structure, the gate contact as JFET.
The above-mentioned device for being integrated with junction field effect transistor, answering for formation is combined using the first trap 202 and the second trap 205
Close raceway groove, enhance raceway groove and exhaust ability, strengthen pinch-off voltage stability, at the same can by adjust composite channel away from
From accurate adjustment pinch-off voltage size, meeting different circuit application scenarios.Referring to Fig. 3, JFET when can be by adjusting photoetching
The spacing of the compound well region of the both sides of source electrode 208 adjusts whole JFET pinch-off voltage.Two traps are symmetrically adjusted by distance,
The concentration of channel region can be effectively adjusted, it is combined with channel region injection, and pinch-off voltage is accomplished accurately to adjust, has reached collection
The purpose controllable into JFET pinch-off voltages.Specifically, the method for adjusting pinch-off voltage is exactly to adjust JFET source electrodes in Fig. 3
The spacing x sizes of adjacent second trap 205 of 208 both sides, and the spacing L of adjacent first trap 202 size is fixed with P- junction depths,
X values can be accurately calculated further according to given pinch off add value, so as to provide suitable x sizes when device designs to meet
Real work demand.Fig. 4 is the Voff for the different length x that emulation obtains situation of change, and wherein ordinate is pinch-off voltage
Voff, unit are volts, and Vd is drain terminal voltage.It can be seen that when x length is smaller, more accurate, the stability of pinch-off voltage regulation and control
Also it is higher.
In the embodiment depicted in figure 2, JFET areas and VDMOS areas intersection are formed with first trap 202, as JFET areas
With the isolation in VDMOS areas.Isolated using the P- assisted depletion of the first trap 202, isolated by deeper P-well, can blocked completely
The circulation path of electric current, the electric leakage between JFET and VDMOS is prevented, and the N- extensions of lower section can be aided in when device is reverse-biased pressure-resistant
Layer (i.e. N-type region 214) participates in exhausting, and the breakdown voltage for lifting regional area acts on to solidify breakdown point.Meanwhile first trap
202 chip area for exhausting structure, can effectively shortening high pressure VDMOS as terminal in junction terminal extension technology.In addition by
Existing in the knot technique of knot terminal extension, P-well junction depth greatly exceed the junction depth of VDMOS P type substrate in conventional art,
So as to there is longer longitudinal current raceway groove.Compared to traditional structure, the pinch-off voltage stability of device can improve it is more, simultaneously
Pinch-off voltage can also significantly reduce.
In the embodiment depicted in figure 2, VDMOS areas include grid (grid include grid oxide layer 203 and polysilicon gate 204), the
The clamper area of two traps 205, the VDMOS source electrodes 206 of N+ in the second trap 205 and the p-type located at the bottom of the second trap 205
210.Wherein clamper area 210 uses the p-type ion implanting of high energy, to obtain enough injection depth.One embodiment wherein
Middle Implantation Energy is 480kev or so.Clamper area 210 can solidify breakdown point.
In the embodiment depicted in figure 2, connect in each second trap 205 formed with groove, VDMOS areas provided with VDMOS source metals
211 are touched, interior ohmic contact regions 209 of the bottom contact position formed with p-type with groove of each second trap 205, VDMOS source metals connect
Touch and 211 be filled in the groove in VDMOS areas, downward through VDMOS source electrodes 206 and extend to ohmic contact regions 209.JFET metals
Grid 213 is filled in the groove in JFET areas and extends downward into ohmic contact regions 209.The ion concentration of ohmic contact regions 209
More than the ion concentration of the second trap 205.
In the embodiment depicted in figure 2, in 205 interior, the VDMOS source electrodes 206 of the second trap in VDMOS areas and ohmic contact regions 209
Between, the non-clamper perception for being also formed with p-type switchs (Unclamped Inductive Switching, UIS) area 207.Non- pincers
The ion concentration of the perceptual switch region 207 in position is more than the ion concentration of the second trap 205.
Fig. 5 is the flow chart of the manufacture method for the device that junction field effect transistor is integrated with an embodiment, below with
Power device is VDMOS, and the first conduction type is N-type, and exemplified by the second conduction type is p-type, introduction is integrated with junction field
The manufacture method of the device of transistor：
S510, there is provided the substrate of the first conduction type, formed with the first conductivity regions on substrate.
In the present embodiment, it is that N-type region 214 is epitaxially formed on N+ substrates, substrate subsequent will be as the drain electrode of device
201。
S520, inject the ion of the second conduction type and push away trap, the first trap is formed in the first conductivity regions.
In the present embodiment, it is implanting p-type ion and to push away trap into N-type region 214, the first trap is formed in N-type region 214
202.Fig. 6 a are the cross-sectional views of device after the completion of step S520.
S530, field oxygen layer and grid oxide layer are grown, form polysilicon layer, injected the ion of the second conduction type and push away trap and formed
Multiple second traps.
Grow thick field oxygen layer and then grow grid oxide layer, and polysilicon layer 604 is formed on the surface of N-type region 214, then with field oxygen
Layer and polysilicon layer 604 be mask to the implanting p-type ion of N-type region 214, push away trap and form multiple second traps 205.Wherein JFET areas
Every one second trap 205 is formed in one first trap 202.The ion that the ion concentration of second trap 205 is more than the first trap 202 is dense
Degree.Fig. 6 b are the cross-sectional views of device after the completion of step S530.
S540, the ion of the first conduction type is injected into second trap in power device area, form power device source electrode.
N-type ion is injected to second trap 205 in VDMOS areas, forms VDMOS source electrodes 206.
Referring to Fig. 6 c, in the present embodiment, inject after the step of N-type ion forms VDMOS source electrode 206, in addition to
In second trap 205 in power device area the step of implanting p-type ion, with the lower section of the VDMOS source electrodes 206 in the second trap 205
Form non-clamper perception switch region 207.In order to prevent the p-type ion pair channel region injected into the second trap 205 from causing unfavorable shadow
Ring, in the present embodiment before the step of implanting p-type ion forms non-clamper perception switch region 207, in addition to form injection resistance
The step of barrier.It is by re-forming layer of oxide layer, due to implanting p-type ion shape to form implant blocking layer in the present embodiment
It is relatively thin into the oxide layer at the injection window of non-clamper perception switch region 207, therefore the p-type ion of high energy ion implantation can pass through oxygen
Change layer and form non-clamper perception switch region 207.And the oxide layer at other positions is formed at the knot such as an oxygen layer, polysilicon layer 604
On structure, therefore the thickness of whole implant blocking layer is thicker, and p-type ion is difficult to enter in N-type region 214 through implant blocking layer.
In Fig. 6 c illustrated embodiments, p-type ion can be equally injected into second trap 205 in JFET areas, it is possible to understand that, in other implementations
Can also be by that will not have p-type ion implanting in this step in second trap 205 in mask (mask) JFET areas in example.
The structure of deep trouth (groove 602) plus P+ injections (forming non-clamper perception switch region 207) is introduced in VDMOS parts,
The purpose is to lift the UIS characteristics of VDMOS device.In traditional high pressure VDMOS techniques, device is strengthened by UIS injections
UIS abilities, but be limited to inject depth and concentration and disperse, effect is not satisfactory.Deep etching VDMOS cell areas, are eliminated
Unnecessary N-type impurity, and concentrate and be filled with p-type ion, add electronics during UIS and release path, greatly reinforced device
UIS abilities.
S550, to the ion that the first conduction type is injected between two adjacent second traps in JFET areas, form JFET source electrodes.
In the present embodiment, it is medium and polysilicon layer 604 that the top of JFET source electrodes 208 is removed by photoetching and etching,
N-type impurity is then injected into, JFET source electrodes 208 are formed on the surface of N-type region 214.Unnecessary polysilicon layer 604 is formed after being removed
Polysilicon gate 204 shown in Fig. 6 d.Fig. 6 d are the cross-sectional views of device after the completion of step S550.
S560, photoetching simultaneously etch contact hole, deposited metal, inserted in contact hole, form the metal of JFET source electrodes respectively
The metal contact of electrode, JFET metal gates and power device source electrode.
Referring to Fig. 6 e, in the present embodiment, it is additionally included in before step S560 in each second trap 205 and etches groove 602
The step of, and at twice to the implanting p-type ion of the second trap 205, wherein being infused in for the first time in every one second trap 205 and groove
602 bottom contact position forms the ohmic contact regions 209 of p-type, and p-type is formed on the bottom for being infused in every one second trap 205 for the second time
Clamper area 210 the step of.The groove 602 that the metal level of deposit is inserted in second trap 205 in JFET areas, form JFET metal gates
Pole 213, the groove 602 inserted in second trap 205 in power device area, form VDMOS source metals contact 211.Deposit metal
Layer after device surface formed passivation layer, after the completion of device section it is as shown in Figure 2.
In one of the embodiments, the clamper area 210 that injection forms p-type is for the injection of high energy p-type, Implantation Energy
480kev or so.
In the present embodiment, the ion concentration of ohmic contact regions 209 is more than the non-ion concentration of clamper perception switch region 207,
And the non-clamper perception switch region 207 in second trap 205 in JFET areas is least partially overlapped with ohmic contact regions 209, in Fig. 6 e
Middle unification ohmic contact regions 209 represent.
The manufacture method of the above-mentioned device for being integrated with junction field effect transistor, the second trap 205 in device can be
The P type substrate in cell areas in VDMOS, but the concentration of P type substrate is limited to cell design parameters in VDMOS, thus needing accurately
It is the photoetching for also needing to add the second trap 205 of special regulation, this photoetching and DMOS process compatibles in the case of adjustment, so whole
The total number of plies of photoetching in technique is constant.
Summary advantage, the above-mentioned device for being integrated with junction field effect transistor improve on the basis of conventional art
The stability of pinch-off voltage, have cured breakdown point, strengthens UIS abilities, is matched completely in technique, and realize pinch-off voltage
The adjustability of size.
In one of the embodiments, step S520 is included in JFET areas and power device area intersection forms one first
Isolation of the trap 202 as JFET areas and power device area.
In one of the embodiments, the implantation concentration of step S520 the first trap 202 is 1.5E13cm-2~
2.2E13cm-2, the well depth of the first trap 202 of formation is 8.5 microns~13.5 microns.
Embodiment described above only expresses the several embodiments of the present invention, and its description is more specific and detailed, but simultaneously
Can not therefore it be construed as limiting the scope of the patent.It should be pointed out that come for one of ordinary skill in the art
Say, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to the protection of the present invention
Scope.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (13)
1. a kind of device for being integrated with junction field effect transistor, the device includes JFET areas and power device area, located at institute
The drain electrode of first conduction type at the device back side is stated, and it is conductive towards first on the positive face of the device located at the drain electrode
The drain electrode and the first conductivity regions are shared by class area, the JFET areas and power device area；Characterized in that, the JFET
Area also includes：
JFET source electrodes, it is the first conduction type；
The metal electrode of JFET source electrodes, it is formed on the JFET source electrodes and the JFET source contacts；
Compound well region structure, is the second conduction type and in first conductivity regions, including the first trap and positioned at institute
The second trap in the first trap is stated, the ion concentration of second trap is more than the ion concentration of first trap, the compound well region
Structure is in the both sides of the JFET source electrodes respectively formed with one, and the JFET source electrodes extend laterally into first trap and
In two traps；First conduction type and the second conduction type are opposite conduction type；
JFET metal gates, in the compound well region structure of the JFET source electrodes both sides.
2. the device according to claim 1 for being integrated with junction field effect transistor, it is characterised in that the JFET areas and
Power device area intersection is formed with first trap, the isolation as JFET areas and power device area.
3. the device according to claim 1 for being integrated with junction field effect transistor, it is characterised in that the device is vertical
Straight double-diffused metal oxide semiconductor field-effect transistor VDMOS.
4. the device according to claim 3 for being integrated with junction field effect transistor, it is characterised in that the power device
Area also includes grid, the second trap, the VDMOS source electrodes of the first conduction type and located at described second in second trap
The clamper area of second conduction type of trap bottom.
5. the device according to claim 4 for being integrated with junction field effect transistor, it is characterised in that each second trap
It is interior also to be contacted formed with groove, the power device area including VDMOS source metals, the interior bottom with the groove of each second trap
Ohmic contact regions of the contact position formed with the second conduction type, the VDMOS source metals contact are filled in the power device
In the groove in area, through the VDMOS source electrodes and the ohmic contact regions are extended to, the JFET metal gates are filled in described
In the groove in JFET areas and the ohmic contact regions are extended to, the ion concentration of the ohmic contact regions is more than second trap
Ion concentration.
6. the device according to claim 5 for being integrated with junction field effect transistor, it is characterised in that in the power device
In second trap in part area, the non-clamper of the second conduction type is also formed between the VDMOS source electrodes and the ohmic contact regions
Perceptual switch region, the ion concentration of the non-clamper perception switch region are more than the ion concentration of second trap.
7. the device for being integrated with junction field effect transistor according to any one in claim 1-6, it is characterised in that
First conduction type is N-type, and second conduction type is p-type, and first conductivity regions are N-type epitaxy layer.
8. a kind of manufacture method for the device for being integrated with junction field effect transistor, the device includes JFET areas and power device
Area, it is characterised in that methods described includes：
The substrate of the first conduction type is provided, formed with the first conductivity regions on the substrate；First conduction type and
Second conduction type is opposite conduction type；
The ion of the second conduction type is injected into the first conductivity regions and pushes away trap, is formed in first conductivity regions
First trap；
Successively growth field oxygen layer and grid oxide layer, polysilicon layer is formed on first conductivity regions surface, is led to described first
Electric class area, which injects the ion of the second conduction type and pushes away trap, forms multiple second traps, second trap positioned at the JFET areas
It is respectively formed in different first traps；
The ion of the first conduction type is injected into second trap in the power device area, forms power device source electrode；
To the ion that the first conduction type is injected between two adjacent second traps in the JFET areas, JFET source electrodes are formed；
Photoetching simultaneously etches contact hole, deposited metal, inserts in the contact hole, respectively formed JFET source electrodes metal electrode,
The metal of JFET metal gates and power device source electrode contacts.
9. according to the method for claim 8, it is characterised in that described to form the first trap in first conductivity regions
The step of, be included in the JFET areas and power device area intersection formed the first trap as JFET areas and power device area every
From.
10. according to the method for claim 8, it is characterised in that described to be led to first conductivity regions injection second
The ion of electric type is simultaneously pushed away in the step of trap forms multiple second traps, is to be noted using the field oxygen layer and polysilicon layer as mask
Enter.
11. according to the method for claim 10, it is characterised in that described the step of forming power device source electrode and the shape
Into between the step of JFET source electrodes, in addition to step：
The surface of formation implant blocking layer, the field oxygen layer and polysilicon layer is also superimposed with the implant blocking layer；
The ion of the second conduction type is injected into second trap in the power device area, with described in second trap
The non-clamper perception switch region formed below of power device source electrode, Implantation Energy are more than described to the second of the power device area
The Implantation Energy for the step of ion of the first conduction type is injected in trap, it is superimposed with the field oxygen layer and polycrystalline of the implant blocking layer
Silicon layer is by the ion barrier of the second conduction type of injection.
12. according to the method for claim 8, it is characterised in that the photoetching and the step of etch contact hole before, also wrap
The step of including the etching groove in each second trap, and inject the ion of the second conduction type, every to second trap
The step of forming the ohmic contact regions of the second conduction type with the bottom contact position of the groove in one second trap, insert described
The metal level of groove in second trap in JFET areas, the JFET metal gates are formed, insert the second of the power device area
The metal level of groove in trap, form the metal contact of the power device source electrode.
13. according to the method described in any one in claim 8-12, it is characterised in that first conduction type is N-type,
Second conduction type is p-type, and first conductivity regions are N-type epitaxy layer, and the power device is vertical double diffusion
Mos field effect transistor VDMOS.
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| PCT/CN2017/099402 WO2018041082A1 (en) | 2016-08-31 | 2017-08-29 | Device integrating junction field-effect transistor and manufacturing method therefor |
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| CN109671707A (en) * | 2018-12-25 | 2019-04-23 | 电子科技大学 | A kind of JCD integrated device of integrated VDMOS and preparation method thereof |
| CN111200014A (en) * | 2018-11-19 | 2020-05-26 | 上海晶丰明源半导体股份有限公司 | Junction field effect transistor and manufacturing method thereof |
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| CN113921592B (en) * | 2021-09-30 | 2023-06-30 | 上海华虹宏力半导体制造有限公司 | Junction field effect transistor device and forming method thereof |
| CN113937167B (en) * | 2021-10-20 | 2023-06-23 | 杭州芯迈半导体技术有限公司 | VDMOS device and manufacturing method thereof |
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| WO2018041082A1 (en) | 2018-03-08 |
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