CN107785365B - Device integrated with junction field effect transistor and manufacturing method thereof - Google Patents
Device integrated with junction field effect transistor and manufacturing method thereof Download PDFInfo
- Publication number
- CN107785365B CN107785365B CN201610793753.1A CN201610793753A CN107785365B CN 107785365 B CN107785365 B CN 107785365B CN 201610793753 A CN201610793753 A CN 201610793753A CN 107785365 B CN107785365 B CN 107785365B
- Authority
- CN
- China
- Prior art keywords
- region
- jfet
- well
- conductivity type
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000002353 field-effect transistor method Methods 0.000 title description 2
- 239000002184 metal Substances 0.000 claims abstract description 46
- 230000005669 field effect Effects 0.000 claims abstract description 28
- 239000002131 composite material Substances 0.000 claims abstract description 22
- 150000002500 ions Chemical class 0.000 claims description 58
- 238000000034 method Methods 0.000 claims description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 16
- 230000001939 inductive effect Effects 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 14
- 230000000903 blocking effect Effects 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- 238000002347 injection Methods 0.000 claims description 9
- 239000007924 injection Substances 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 229910044991 metal oxide Inorganic materials 0.000 claims description 4
- 150000004706 metal oxides Chemical class 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 3
- 238000002513 implantation Methods 0.000 description 14
- 238000000206 photolithography Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000007943 implant Substances 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000011295 pitch Substances 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
Abstract
The invention relates to a device integrated with a junction field effect transistor and a manufacturing method thereof, wherein a JFET area of the device comprises: a JFET source of a first conductivity type; the metal electrode of the JFET source electrode is formed on the JFET source electrode and is in contact with the JFET source electrode; the composite well region structure is of a second conductivity type, is arranged in the first conductivity type region, and comprises a first well and a second well positioned in the first well, wherein the ion concentration of the second well is greater than that of the first well, one composite well region structure is formed on each of two sides of the JFET source electrode, and the JFET source electrode transversely extends into the first well and the second well; and the JFET metal gate is arranged on the composite well region structure at two sides of the JFET source electrode. According to the invention, the composite channel is formed by using the composite well region formed by the first well and the second well, so that the channel depletion capability is enhanced, and the pinch-off voltage stability is enhanced. Meanwhile, the pinch-off voltage can be accurately adjusted by adjusting the distance of the composite channel, so that different circuit application occasions are met.
Description
Technical Field
The present invention relates to a semiconductor manufacturing technology, and more particularly, to a device integrated with a junction field effect transistor and a method for manufacturing the device integrated with the junction field effect transistor.
Background
The integration of a high-voltage Junction Field Effect Transistor (JFET) on a high-voltage process platform is an advanced development and conception in the Field of modern intelligent power integrated circuits, can greatly improve the on-state performance of a longitudinal power device, remarkably reduce the chip area, and meet the mainstream trend of the manufacture of the modern intelligent power device.
The high-voltage integrated JFET with the traditional structure can be realized by a simpler process, but the large-scale application of the JFET in the field of intelligent power integration is limited by the characteristics of unstable pinch-off voltage, poor regulation and control performance and the like.
Disclosure of Invention
In view of this, it is necessary to provide a device integrated with a JFET transistor to solve the problems of unstable pinch-off voltage and poor regulation of the conventional JFET.
A device integrated with a junction field effect transistor comprises a JFET area and a power device area, a drain electrode of a first conductivity type arranged on the back surface of the device, and a first conductivity type area arranged on the surface of the drain electrode facing to the front surface of the device, wherein the JFET area and the power device area share the drain electrode and the first conductivity type area; the JFET region further comprises: a JFET source of a first conductivity type; the metal electrode of the JFET source electrode is formed on the JFET source electrode and is in contact with the JFET source electrode; the composite well region structure is of a second conductivity type, is arranged in the first conductivity type region, and comprises a first trap and a second trap positioned in the first trap, wherein the ion concentration of the second trap is greater than that of the first trap, one composite well region structure is formed on each of two sides of the JFET source, and the JFET source transversely extends into the first trap and the second trap; the first conductivity type and the second conductivity type are opposite conductivity types; and the JFET metal gate is arranged on the composite well region structure on two sides of the JFET source electrode.
In one embodiment, the first well is formed at the junction of the JFET region and the power device region, and is used for isolating the JFET region from the power device region.
In one embodiment, the device is a vertical double diffused metal oxide semiconductor field effect transistor (VDMOS).
In one embodiment, the power device region further includes a gate, a second well, a VDMOS source of the first conductivity type disposed in the second well, and a clamp region of the second conductivity type disposed at the bottom of the second well.
In one embodiment, a trench is formed in each second well, the power device region further includes a VDMOS source metal contact, an ohmic contact region of the second conductivity type is formed in each second well at a contact position with the bottom of the trench, the VDMOS source metal contact is filled in the trench of the power device region, penetrates through the VDMOS source and extends to the ohmic contact region, the JFET metal gate is filled in the trench of the JFET region and extends to the ohmic contact region, and an ion concentration of the ohmic contact region is greater than that of the second well.
In one embodiment, a non-clamping inductive switching region of the second conductivity type is further formed in the second well of the power device region between the VDMOS source and the ohmic contact region, and the ion concentration of the non-clamping inductive switching region is greater than that of the second well.
In one embodiment, the first conductivity type is N-type, the second conductivity type is P-type, and the first conductivity type region is an N-type epitaxial layer.
There is also a need to provide a method of manufacturing a device integrated with a junction field effect transistor.
A method of manufacturing a device integrated with a junction field effect transistor, the device comprising a JFET region and a power device region, the method comprising: providing a substrate of a first conductive type, wherein a first conductive type area is formed on the substrate; the first conductivity type and the second conductivity type are opposite conductivity types; injecting ions of a second conductive type into the first conductive type region and pushing the ions to a trap, and forming a first trap in the first conductive type region; growing a field oxide layer and a gate oxide layer in sequence, forming a polycrystalline silicon layer on the surface of the first conduction type region, injecting ions of a second conduction type into the first conduction type region and pushing the ions into the wells to form a plurality of second wells, wherein the second wells positioned in the JFET region are formed in different first wells respectively; injecting ions of a first conduction type into the second trap of the power device area to form a source electrode of the power device; injecting ions of a first conductivity type between two adjacent second wells of the JFET region to form a JFET source electrode; and photoetching and etching the contact hole, depositing a metal layer, filling the metal layer into the contact hole, and respectively forming a metal electrode of the JFET source electrode, a metal grid electrode of the JFET and metal contacts of the power device source electrode.
In one embodiment, the step of forming the first well in the first conductivity type region includes forming the first well at an interface of the JFET region and the power device region as an isolation of the JFET region and the power device region.
In one embodiment, in the step of implanting ions of the second conductivity type into the first conductivity type region and driving the well to form the plurality of second wells, the implantation is performed using the field oxide layer and the polysilicon layer as masks.
In one embodiment, between the step of forming the source of the power device and the step of forming the source of the JFET, the method further comprises the steps of: forming an injection blocking layer, wherein the injection blocking layer is also superposed on the surfaces of the field oxide layer and the polycrystalline silicon layer; and injecting ions of a second conduction type into the second trap of the power device region to form a non-clamping inductive switching region below the source electrode of the power device in the second trap, wherein the injection energy is greater than that of the step of injecting the ions of the first conduction type into the second trap of the power device region, and the field oxide layer and the polycrystalline silicon layer which are overlapped with the injection blocking layer block the injected ions of the second conduction type.
In one embodiment, before the step of performing photolithography and etching the contact hole, the method further includes a step of etching a trench in each second well, and a step of injecting ions of the second conductivity type into each second well to form an ohmic contact region of the second conductivity type at a contact position with the bottom of the trench in each second well, wherein the metal layer of the trench in the second well of the JFET region is filled to form the JFET metal gate, and the metal layer of the trench in the second well of the power device region is filled to form the metal contact of the source of the power device.
In one embodiment, the first conductivity type is N-type, the second conductivity type is P-type, the first conductivity type region is an N-type epitaxial layer, and the power device is a vertical double-diffused metal oxide semiconductor field effect transistor VDMOS.
According to the device integrated with the junction field effect transistor and the manufacturing method thereof, the composite channel is formed by the composite well region formed by the first well and the second well, so that the channel depletion capability is enhanced, and the pinch-off voltage stability is enhanced. Meanwhile, the pinch-off voltage can be accurately adjusted by adjusting the distance of the composite channel, so that different circuit application occasions are met.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings of the embodiments can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic cross-sectional view of a conventional high voltage integrated JFET;
FIG. 2 is a schematic cross-sectional view of a device integrated with a junction field effect transistor in one embodiment;
figure 3 is a schematic diagram of the JFET region's recombination channel affecting the pinch-off voltage;
fig. 4 is a simulation result of the variation of Voff of the device at different pitches x of adjacent second wells;
FIG. 5 is a flow chart of a method of fabricating a device integrated with a junction field effect transistor in one embodiment;
fig. 6a to 6e are schematic sectional structures of devices manufactured by the method of manufacturing a device integrated with a junction field effect transistor in a manufacturing process.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and the like as used herein are for illustrative purposes only.
As used herein, the term semiconductor is used in the art to distinguish between P-type and N-type impurities, and for example, P + type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N + type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.
A conventional Vertical Double-diffused metal-oxide-semiconductor Field Effect Transistor (VDMOS) structure integrated with a high-voltage Junction Field-Effect Transistor (JFET) is shown in fig. 1. Including gate 101, source 102, high voltage P-well 103, body contact 104, N-type epitaxial layer 105, and N + contact 106.
When the VDMOS is in the on-phase, current flows from the bottom drain through the JFET and out source 2. When a gradually larger voltage Vg2 is applied to the source2 and the same voltage Vg1 is applied to the gate, and when Vg2 is larger than the pinch-off voltage Voff, the depletion layer of the JFET blocks the current, namely pinch-off occurs. At this time Vg1> Vth, the VDMOS is turned on, completing a turn-on process. The JFET absorbs the abrupt current of the DMOS on the Miller platform, so that the starting is more smooth, the current can be approximately linearly converted, and the JFET has a remarkable effect on improving the stability of the device in the starting process. It is advantageous for the power device to integrate a parasitic JFET on its process platform.
In practical JFET device applications, the pinch-off voltage needs to be stable and controllable, especially in high voltage applications. The conventional structure generally uses a self-aligned P-type implanted substrate as a P-type pinch-off substrate, and since the P-type substrate of a cell (cell) of the VDMOS has a shallow longitudinal junction depth, which is generally only 3-5 μm, the longitudinal channel of the JFET is short. Meanwhile, the concentration of a channel formed by high-temperature diffusion is not uniform, so that the pinch-off voltage is unstable. Simulation shows that when the drain voltage changes from 50V to 100V, the pinch-off voltage Voff increases from 11V to 20V; meanwhile, the JFET integrated by the traditional high-voltage process has the defect of poor controllability of pinch-off voltage due to the fact that the concentration of the high-voltage P well is relatively fixed. However, in practical circuit applications, the pinch-off voltage level required by different circuits will be different, and thus the actual requirements cannot be met.
Fig. 2 is a schematic cross-sectional structure diagram of a device integrated with a junction field effect transistor in an embodiment, in this embodiment, an N type is defined as a first conductivity type, a P type is defined as a second conductivity type, and a power device is a VDMOS. As shown in fig. 2, the device is structurally divided into a JFET region and a VDMOS region, which share an N-type drain 201 disposed on the back side of the device (i.e., the side facing downward in fig. 2), and an N-type region 214 disposed on the front side of the drain 201 (i.e., the side facing upward in fig. 2). In the present embodiment, the drain 201 is an N + drain, and the N-type region 214 is an N-epitaxial layer (in other embodiments, an N-type substrate can be directly used).
In this embodiment, the JFET region includes a JFET source 208, a JFET source metal electrode 212, a JFET metal gate 213, and a composite well region structure consisting of a first well 202 and a second well 205.
In the present embodiment, the composite well region structure is formed in an N-epitaxial layer, wherein the first well 202 is a P-well and the second well 205 is a high voltage P-well located in the first well 202. The ion concentration of the second trap 205 is greater than the ion concentration of the first trap 202. In one cell, a composite well region structure is formed on each side of the N + JFET source 208, and the JFET source 208 extends laterally into the first well 202 and the second well 205. The second well 205 serves as an N-type contact for the device, forming a conductive channel. A JFET source metal electrode 212 is formed on the JFET source 208 as a source contact to the JFET source 208. A JFET metal gate 213 is disposed over the composite well region structure as a gate contact for the JFET.
According to the device integrated with the junction field effect transistor, the composite channel formed by combining the first well 202 and the second well 205 is utilized, the channel depletion capability is enhanced, the pinch-off voltage stability is enhanced, and meanwhile, the pinch-off voltage can be accurately adjusted by adjusting the distance of the composite channel, so that different circuit application occasions are met. Referring to fig. 3, the pinch-off voltage of the whole JFET can be adjusted by adjusting the spacing of the composite well regions on both sides of the JFET source 208 during photolithography. The two traps are symmetrically subjected to distance adjustment, the concentration of a channel region can be effectively adjusted, the two traps are combined with channel region injection, the clamping voltage is accurately adjusted, and the purpose that the clamping voltage of the integrated JFET can be controlled and adjusted is achieved. Specifically, the method for adjusting the pinch-off voltage is to adjust the size of the distance x between the adjacent second wells 205 on both sides of the JFET source 208 in fig. 3, and the size of the distance L between the adjacent first wells 202 is fixed along with the P-junction depth, and then the value x can be accurately calculated according to the given pinch-off addition value, so that the proper size x is given during device design to meet the actual working requirements. Fig. 4 shows the variation of Voff with different lengths x obtained by simulation, where the ordinate is the pinch-off voltage Voff in volts and Vd is the drain voltage. It can be seen that the smaller the x length, the more precise the pinch-off voltage regulation and the higher the stability.
In the embodiment shown in fig. 2, a first well 202 is formed at the junction of the JFET region and the VDMOS region to isolate the JFET region from the VDMOS region. The first P-well 202 is used for assisting in depletion isolation, a current circulation path can be completely blocked through deeper P-well isolation, leakage between the JFET and the VDMOS is prevented, the N-epitaxial layer (namely the N-type region 214) below the JFET and the VDMOS can be assisted in depletion during reverse bias voltage resistance of the device, and breakdown voltage of a local region is improved to solidify a breakdown point effect. Meanwhile, the first well 202 is used as a depletion structure of a terminal in a junction terminal expansion technology, so that the chip area of the high-voltage VDMOS can be effectively shortened. In addition, due to the junction process of the junction terminal expansion, the junction depth of a P-well is greatly higher than that of a P-type substrate of a VDMOS in the prior art, so that a longer longitudinal current channel is formed. Compared with the traditional structure, the pinch-off voltage stability of the device is improved more, and the pinch-off voltage is also reduced obviously.
In the embodiment shown in fig. 2, the VDMOS region includes a gate (the gate includes a gate oxide layer 203 and a polysilicon gate 204), a second well 205, an N + VDMOS source 206 disposed in the second well 205, and a P-type clamp region 210 disposed at the bottom of the second well 205. Wherein the clamp region 210 is implanted with high-energy P-type ions to obtain a sufficient implantation depth. The implant energy is about 480kev in one embodiment. The clamping area 210 is capable of solidifying the breakdown point.
In the embodiment shown in fig. 2, a trench is formed in each second well 205, a VDMOS source metal contact 211 is formed in the VDMOS region, a P-type ohmic contact region 209 is formed in each second well 205 at a contact position with a bottom of the trench, and the VDMOS source metal contact 211 fills the trench of the VDMOS region, penetrates the VDMOS source 206 downward, and extends to the ohmic contact region 209. The JFET metal gate 213 fills the trench in the JFET region and extends down to the ohmic contact region 209. The ion concentration of the ohmic contact region 209 is greater than the ion concentration of the second trap 205.
In the embodiment shown in fig. 2, a P-type Unclamped Inductive Switching (UIS) region 207 is further formed in the second well 205 of the VDMOS region between the VDMOS source 206 and the ohmic contact region 209. The ion concentration of the non-clamping inductive switching region 207 is greater than the ion concentration of the second trap 205.
Fig. 5 is a flowchart of a method for manufacturing a device integrated with a junction field effect transistor in an embodiment, and a method for manufacturing a device integrated with a junction field effect transistor is described below by taking the example that a power device is a VDMOS, a first conductivity type is an N type, and a second conductivity type is a P type:
s510, providing a substrate of a first conduction type, wherein a first conduction type area is formed on the substrate.
In this embodiment, an N-type region 214 is epitaxially formed on an N + substrate, which will subsequently serve as the drain 201 of the device.
S520, injecting ions of the second conductive type and pushing the trap to form a first trap in the first conductive type area.
In the present embodiment, P-type ions are implanted into the N-type region 214 and pushed into the well, thereby forming the first well 202 in the N-type region 214. Fig. 6a is a schematic cross-sectional structure diagram of the device after step S520 is completed.
S530, growing a field oxide layer and a gate oxide layer to form a polysilicon layer, injecting ions of the second conduction type and pushing the wells to form a plurality of second wells.
Growing a thick field oxide layer, then growing a gate oxide layer, forming a polysilicon layer 604 on the surface of the N-type region 214, implanting P-type ions into the N-type region 214 by using the field oxide layer and the polysilicon layer 604 as masks, and forming a plurality of second wells 205 by using a push-well. Wherein each second well 205 of the JFET region is formed within a first well 202. The ion concentration of the second trap 205 is greater than the ion concentration of the first trap 202. Fig. 6b is a schematic cross-sectional structure diagram of the device after step S530 is completed.
And S540, injecting ions of the first conductivity type into the second trap of the power device region to form a source electrode of the power device.
N-type ions are implanted into the second well 205 of the VDMOS region to form a VDMOS source 206.
Referring to fig. 6c, in the present embodiment, after the step of implanting N-type ions to form the VDMOS source 206, a step of implanting P-type ions into the second well 205 of the power device region is further included to form a non-clamped inductive switch region 207 below the VDMOS source 206 in the second well 205. In order to prevent the P-type ions implanted into the second well 205 from adversely affecting the channel region, the present embodiment further includes a step of forming an implantation blocking layer before the step of implanting P-type ions to form the non-clamping inductive switch region 207. In this embodiment, the step of forming the implantation blocking layer is to form an oxide layer, and since the oxide layer at the implantation window where the P-type ions are implanted to form the non-clamped inductive switch region 207 is thinner, the high-energy implanted P-type ions can penetrate through the oxide layer to form the non-clamped inductive switch region 207. The oxide layers at other positions are formed on the field oxide layer, the polysilicon layer 604, etc., so that the thickness of the whole implantation blocking layer is relatively thick, and P-type ions are difficult to penetrate through the implantation blocking layer into the N-type region 214. In the embodiment shown in fig. 6c, P-type ions are also implanted into the second well 205 of the JFET region, and it is understood that in other embodiments, a mask (mask) may be used to prevent P-type ions from being implanted into the second well 205 of the JFET region in this step.
The structure of introducing a deep trench (trench 602) and P + implantation (forming the non-clamped inductive switch region 207) into the VDMOS part aims to improve the UIS characteristics of the VDMOS device. In the traditional high-voltage VDMOS process, the UIS capability of the device is enhanced by UIS implantation, but the device is limited by implantation depth and concentration dispersion, and the effect is not ideal. The deep groove etches the cell region of the VDMOS, redundant N-type impurities are removed, P-type ions are injected in a concentrated mode, an electron discharge path in the UIS process is increased, and the UIS capacity of the device is greatly enhanced.
And S550, injecting ions of the first conductivity type between two adjacent second wells of the JFET region to form a JFET source.
In this embodiment, the JFET source 208 is formed on the surface of the N-type region 214 by removing the dielectric and polysilicon layer 604 above the JFET source 208 by photolithography and etching, and then implanting N-type impurities. The excess polysilicon layer 604 is removed to form the polysilicon gate 204 shown in figure 6 d. Fig. 6d is a schematic cross-sectional structure diagram of the device after step S550 is completed.
And S560, photoetching and etching the contact hole, depositing a metal layer, filling the metal layer into the contact hole, and respectively forming a metal electrode of the JFET source electrode, a metal grid electrode of the JFET and metal contacts of the power device source electrode.
Referring to fig. 6e, in the present embodiment, the step S560 further includes a step of etching a trench 602 in each second well 205, and a step of implanting P-type ions into the second wells 205 in two times, where the first implantation forms a P-type ohmic contact region 209 at a position in each second well 205, where the first implantation contacts with the bottom of the trench 602, and the second implantation forms a P-type clamp region 210 at the bottom of each second well 205. The deposited metal layer fills the trench 602 in the second well 205 of the JFET region to form the JFET metal gate 213 and fills the trench 602 in the second well 205 of the power device region to form the VDMOS source metal contact 211. After depositing the metal layer, a passivation layer is formed on the surface of the device, and the cross section of the completed device is shown in fig. 2.
In one embodiment, the clamp region 210 implanted to form a P-type is a high energy P-type implant with an implant energy of about 480 kev.
In this embodiment, the ion concentration of the ohmic contact region 209 is greater than the ion concentration of the non-clamping inductive switch region 207, and the non-clamping inductive switch region 207 in the second well 205 of the JFET region at least partially overlaps the ohmic contact region 209, which is collectively represented by the ohmic contact region 209 in fig. 6 e.
In the manufacturing method of the device integrated with the junction field effect transistor, the second well 205 in the device can be a P-type substrate of a cell region in a VDMOS, but the concentration of the P-type substrate is limited by the cell design parameters in the VDMOS, so that the photolithography specially adjusting the second well 205 is required to be added under the condition of accurate adjustment, the photolithography is compatible with the DMOS process, and the total number of photolithography layers in the whole process is not changed.
By combining the advantages, the device integrated with the junction field effect transistor improves the stability of the pinch-off voltage on the basis of the traditional technology, solidifies the breakdown point, strengthens the UIS capability, is completely matched in process, and realizes the adjustability of the pinch-off voltage.
In one embodiment, step S520 includes forming a first well 202 at the junction of the JFET region and the power device region to isolate the JFET region from the power device region.
In one embodiment, the implantation concentration of the first well 202 of step S520 is 1.5E13cm-2～2.2E13cm-2The well depth of the first well 202 is 8.5 to 13.5 μm.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (13)
1. A device integrated with a junction field effect transistor comprises a JFET area and a power device area, a drain electrode of a first conductivity type arranged on the back surface of the device, and a first conductivity type area arranged on the surface of the drain electrode facing to the front surface of the device, wherein the JFET area and the power device area share the drain electrode and the first conductivity type area; wherein the JFET region further comprises:
a JFET source of a first conductivity type;
the metal electrode of the JFET source electrode is formed on the JFET source electrode and is in contact with the JFET source electrode;
the composite well region structure is of a second conductivity type, is arranged in the first conductivity type region, and comprises a first trap and a second trap positioned in the first trap, wherein the ion concentration of the second trap is greater than that of the first trap, one composite well region structure is formed on each of two sides of the JFET source, and the JFET source transversely extends into the first trap and the second trap; the first conductivity type and the second conductivity type are opposite conductivity types;
the JFET metal gate is arranged on the composite well region structure on two sides of the JFET source electrode;
wherein the second well forms a conductive channel.
2. The device of claim 1, wherein the junction of the JFET region and the power device region is formed with a first well that serves as an isolation between the JFET region and the power device region.
3. The device integrated with a junction field effect transistor according to claim 1, wherein the device is a vertical double-diffused metal oxide semiconductor field effect transistor (VDMOS).
4. The device integrated with a junction field effect transistor according to claim 3, wherein the power device region further comprises a gate, a second well, a VDMOS source of the first conductivity type disposed in the second well, and a clamp region of the second conductivity type disposed at the bottom of the second well.
5. The device of claim 4, wherein a trench is formed in each second well, the power device region further comprises a VDMOS source metal contact, an ohmic contact region of the second conductivity type is formed in each second well at a contact with a bottom of the trench, the VDMOS source metal contact is filled in the trench of the power device region, penetrates through the VDMOS source and extends to the ohmic contact region, the JFET metal gate is filled in the trench of the JFET region and extends to the ohmic contact region, and an ion concentration of the ohmic contact region is greater than an ion concentration of the second well.
6. The device integrated with the junction field effect transistor according to claim 5, wherein a non-clamping inductive switching region of the second conductivity type is further formed in the second well of the power device region between the VDMOS source and the ohmic contact region, and the ion concentration of the non-clamping inductive switching region is greater than that of the second well.
7. The device according to any of claims 1 to 6, wherein the first conductivity type is N-type, the second conductivity type is P-type, and the first conductivity type region is an N-type epitaxial layer.
8. A method of manufacturing a device integrated with a junction field effect transistor, the device comprising a JFET region and a power device region, the method comprising:
providing a substrate of a first conductive type, wherein a first conductive type area is formed on the substrate; the first conductivity type and the second conductivity type are opposite conductivity types;
injecting ions of a second conductive type into the first conductive type region and pushing the ions to a trap, and forming a first trap in the first conductive type region;
growing a field oxide layer and a gate oxide layer in sequence, forming a polycrystalline silicon layer on the surface of the first conduction type region, injecting ions of a second conduction type into the first conduction type region and pushing the ions into the wells to form a plurality of second wells, wherein the second wells positioned in the JFET region are formed in different first wells respectively;
injecting ions of a first conduction type into the second trap of the power device area to form a source electrode of the power device;
injecting ions of a first conductivity type between two adjacent second wells of the JFET region to form a JFET source electrode;
and photoetching and etching the contact hole, depositing a metal layer, filling the metal layer into the contact hole, and respectively forming a metal electrode of the JFET source electrode, a metal grid electrode of the JFET and metal contacts of the power device source electrode.
9. The method of claim 8, wherein the step of forming the first well within the first conductivity type region comprises forming the first well at an interface of the JFET region and the power device region as an isolation of the JFET region and the power device region.
10. The method of claim 8, wherein the step of implanting ions of the second conductivity type into the first conductivity type region and driving the well to form a plurality of second wells is performed by using the field oxide layer and the polysilicon layer as masks.
11. The method of claim 10, wherein between the step of forming the power device source and the step of forming the JFET source, further comprising the steps of:
forming an injection blocking layer, wherein the injection blocking layer is also superposed on the surfaces of the field oxide layer and the polycrystalline silicon layer;
and injecting ions of a second conduction type into the second trap of the power device region to form a non-clamping inductive switching region below the source electrode of the power device in the second trap, wherein the injection energy is greater than that of the step of injecting the ions of the first conduction type into the second trap of the power device region, and the field oxide layer and the polycrystalline silicon layer which are overlapped with the injection blocking layer block the injected ions of the second conduction type.
12. The method of claim 8, wherein the step of etching contact holes further comprises a step of etching trenches in each of the second wells, and a step of implanting ions of the second conductivity type into the second wells to form ohmic contact regions of the second conductivity type in each of the second wells at a contact point with the bottom of the trench, wherein the metal layer of the trench filled in the second well of the JFET region forms the JFET metal gate, and the metal layer of the trench filled in the second well of the power device region forms the metal contact of the power device source.
13. The method as claimed in any one of claims 8-12, wherein the first conductivity type is N-type, the second conductivity type is P-type, the first conductivity type region is an N-type epitaxial layer, and the power device is a vertical double-diffused metal oxide semiconductor field effect transistor (VDMOS).
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610793753.1A CN107785365B (en) | 2016-08-31 | 2016-08-31 | Device integrated with junction field effect transistor and manufacturing method thereof |
| PCT/CN2017/099402 WO2018041082A1 (en) | 2016-08-31 | 2017-08-29 | Device integrating junction field-effect transistor and manufacturing method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610793753.1A CN107785365B (en) | 2016-08-31 | 2016-08-31 | Device integrated with junction field effect transistor and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107785365A CN107785365A (en) | 2018-03-09 |
| CN107785365B true CN107785365B (en) | 2021-08-06 |
Family
ID=61300296
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610793753.1A Active CN107785365B (en) | 2016-08-31 | 2016-08-31 | Device integrated with junction field effect transistor and manufacturing method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN107785365B (en) |
| WO (1) | WO2018041082A1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109671707B (en) * | 2018-12-25 | 2023-03-28 | 电子科技大学 | JCD integrated device integrated with VDMOS and preparation method thereof |
| CN113921592B (en) * | 2021-09-30 | 2023-06-30 | 上海华虹宏力半导体制造有限公司 | Junction field effect transistor device and forming method thereof |
| CN113937167B (en) * | 2021-10-20 | 2023-06-23 | 杭州芯迈半导体技术有限公司 | VDMOS device and manufacturing method thereof |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4403395A (en) * | 1979-02-15 | 1983-09-13 | Texas Instruments Incorporated | Monolithic integration of logic, control and high voltage interface circuitry |
| CN1866542A (en) * | 2005-05-18 | 2006-11-22 | 崇贸科技股份有限公司 | MOS field effect transistor with isolating structure and making method thereof |
| US7211845B1 (en) * | 2004-04-19 | 2007-05-01 | Qspeed Semiconductor, Inc. | Multiple doped channel in a multiple doped gate junction field effect transistor |
| CN101026190A (en) * | 2007-03-30 | 2007-08-29 | 东南大学 | Trench high-pressure N-type metal oxide semiconductor tube and its preparing process |
| US7595244B1 (en) * | 2000-03-31 | 2009-09-29 | National Semiconductor Corporation | Fabrication of like-polarity insulated-gate field-effect transistors having multiple vertical body dopant concentration maxima and different halo pocket characteristics |
| CN102034820A (en) * | 2010-01-28 | 2011-04-27 | 崇贸科技股份有限公司 | Semiconductor device |
| CN102403352A (en) * | 2010-09-14 | 2012-04-04 | 无锡华润上华半导体有限公司 | MOS (metal oxide semiconductor) transistor |
| CN103022035A (en) * | 2012-01-20 | 2013-04-03 | 成都芯源系统有限公司 | Integrated circuit and method for manufacturing integrated circuit |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4229042B2 (en) * | 2004-10-14 | 2009-02-25 | 株式会社デンソー | Insulated gate bipolar transistor |
| US8710510B2 (en) * | 2006-08-17 | 2014-04-29 | Cree, Inc. | High power insulated gate bipolar transistors |
| US8674439B2 (en) * | 2010-08-02 | 2014-03-18 | Microsemi Corporation | Low loss SiC MOSFET |
| CN101950759A (en) * | 2010-08-27 | 2011-01-19 | 电子科技大学 | Super Junction VDMOS device |
| US9059329B2 (en) * | 2011-08-22 | 2015-06-16 | Monolithic Power Systems, Inc. | Power device with integrated Schottky diode and method for making the same |
| CN102299183B (en) * | 2011-09-22 | 2013-10-09 | 上海先进半导体制造股份有限公司 | Junction field effect transistor (JFET) and forming method thereof |
| US9460926B2 (en) * | 2014-06-30 | 2016-10-04 | Alpha And Omega Semiconductor Incorporated | Forming JFET and LDMOS transistor in monolithic power integrated circuit using deep diffusion regions |
-
2016
- 2016-08-31 CN CN201610793753.1A patent/CN107785365B/en active Active
-
2017
- 2017-08-29 WO PCT/CN2017/099402 patent/WO2018041082A1/en active Application Filing
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4403395A (en) * | 1979-02-15 | 1983-09-13 | Texas Instruments Incorporated | Monolithic integration of logic, control and high voltage interface circuitry |
| US7595244B1 (en) * | 2000-03-31 | 2009-09-29 | National Semiconductor Corporation | Fabrication of like-polarity insulated-gate field-effect transistors having multiple vertical body dopant concentration maxima and different halo pocket characteristics |
| US7211845B1 (en) * | 2004-04-19 | 2007-05-01 | Qspeed Semiconductor, Inc. | Multiple doped channel in a multiple doped gate junction field effect transistor |
| CN1866542A (en) * | 2005-05-18 | 2006-11-22 | 崇贸科技股份有限公司 | MOS field effect transistor with isolating structure and making method thereof |
| CN101026190A (en) * | 2007-03-30 | 2007-08-29 | 东南大学 | Trench high-pressure N-type metal oxide semiconductor tube and its preparing process |
| CN102034820A (en) * | 2010-01-28 | 2011-04-27 | 崇贸科技股份有限公司 | Semiconductor device |
| CN102403352A (en) * | 2010-09-14 | 2012-04-04 | 无锡华润上华半导体有限公司 | MOS (metal oxide semiconductor) transistor |
| CN103022035A (en) * | 2012-01-20 | 2013-04-03 | 成都芯源系统有限公司 | Integrated circuit and method for manufacturing integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2018041082A1 (en) | 2018-03-08 |
| CN107785365A (en) | 2018-03-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100904378B1 (en) | Power MOS Device | |
| KR102000886B1 (en) | Insulated gate type switching device and manufacturing method thereof | |
| CN107482061B (en) | Super junction device and manufacturing method thereof | |
| KR20100064263A (en) | A semiconductor device and method for manufacturing the same | |
| CN107785366B (en) | Device integrated with junction field effect transistor and manufacturing method thereof | |
| CN107785411B (en) | Device integrated with junction field effect transistor and manufacturing method thereof | |
| CN110718546A (en) | Power MOSFET with integrated pseudo-Schottky diode in source contact trench | |
| CN107785367B (en) | Device integrated with depletion type junction field effect transistor and manufacturing method thereof | |
| US20160149029A1 (en) | Semiconductor device and method for manufacturing semiconductor device | |
| CN105895533B (en) | The manufacturing method of super-junction structure | |
| CN107785365B (en) | Device integrated with junction field effect transistor and manufacturing method thereof | |
| CN108091695B (en) | Vertical double-diffused field effect transistor and manufacturing method thereof | |
| CN107785416B (en) | Junction field effect transistor and manufacturing method thereof | |
| CN111223931A (en) | Trench MOSFET and method of manufacturing the same | |
| US8421149B2 (en) | Trench power MOSFET structure with high switching speed and fabrication method thereof | |
| CN107039243B (en) | Super junction device and manufacturing method thereof | |
| CN104037206A (en) | Super-junction device and manufacturing method thereof | |
| CN105957897A (en) | Manufacturing method for groove grid super junction MOSFET | |
| TWI385802B (en) | High-voltage metal-oxide semiconductor device and fabrication method thereof | |
| CN107994077B (en) | Vertical double-diffused field effect transistor and manufacturing method thereof | |
| JP2019165166A (en) | Silicon carbide semiconductor device and method of manufacturing the same | |
| CN108766885B (en) | Manufacturing method of composite gate IGBT chip with three-dimensional channel | |
| CN105810723B (en) | It can realize the structures and methods of the MOSFET of reverse blocking | |
| CN110957351A (en) | Super-junction MOSFET device and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |