CN109671707B - JCD integrated device integrated with VDMOS and preparation method thereof - Google Patents
JCD integrated device integrated with VDMOS and preparation method thereof Download PDFInfo
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Abstract
A JCD integrated device of an integrated VDMOS and a preparation method thereof belong to the technical field of power semiconductor integration. The invention realizes the production of JFET, CMOS and VDMOS on the same chip for the first time, and can integrate passive elements such as poly capacitor, poly resistor, poly diode and the like with the JFET, CMOS and VDMOS to form a circuit. The invention not only combines the advantages of high switching speed, high voltage resistance of VDMOS, excellent analog characteristic and low noise characteristic of JFET device, strong temperature stability and radiation resistance, high integration degree of CMOS part and the like, but also brings great flexibility for power circuit design. The whole process of the invention uses fewer masks, has strong reusability of process levels and is beneficial to controlling the manufacturing cost; the chip manufactured by applying the JCD integration technology has better comprehensive performance and is beneficial to the development of the monolithic power system integration.
Description
Technical Field
The invention belongs to the technical field of power semiconductor integration, and particularly relates to a JCD integrated device integrating VDMOS and a preparation method thereof.
Background
For more than 40 years, semiconductor technology has continued to shrink in chip feature size along the lines of moore's law, however, semiconductor technology has now developed into a bottleneck: as the line width becomes smaller, the manufacturing cost rises exponentially; and as the line width approaches the nanometer scale, the quantum effect is more and more obvious, and the leakage current of the chip is also more and more large. Therefore, the development of semiconductor technology must consider the "post-molar age" problem. The International Technology Roadmap for Semiconductors (ITRS) proposed a concept that surpassed the more than Moore's law in 2005. The power semiconductor device and the power integration technology play an important role in more than Moore, are mainly used for power processing circuits of frequency conversion, voltage transformation, current transformation, power amplification, power management and the like in modern electronic systems, and are also one of the key technologies in the fields of current consumer electronics, industrial control, national defense equipment and the like.
A power integrated circuit (power integrated circuit) is an integrated circuit in which a high-voltage power device, a control circuit, a peripheral interface circuit, a protection circuit, and the like are integrated on the same chip, and is a bridge between a system signal processing section and an execution section. In the power integration technology, process compatibility between a high-voltage device and a low-voltage device is realized, particularly, a proper isolation technology is selected, and reusability of process layers must be considered in order to control manufacturing cost. Along with the development of the application requirements of an electronic system, more low-voltage logic circuits and more storage modules are required to be integrated to realize complex intelligent control; the power integrated circuit used as a strong and weak current bridge also has to realize low power consumption and high efficiency; the harsh application environment requires good performance and reliability. Therefore, power integration technology needs to achieve high-low voltage compatibility, high performance, high efficiency, and high reliability on a limited chip area. The BCD (Bipolar-CMOS-DMOS) integration technology is currently the mainstream power semiconductor integration technology, and integrates a high-precision Bipolar analog circuit, a high-integration CMOS logic circuit, and a high-power DMOS device on the same chip, and combines the advantages of the Bipolar circuit, such as low noise, high precision, high current density, low power consumption, high integration, simple logic control of the CMOS circuit, and high input impedance, high power capacity, fast switching speed, and good thermal stability of the DMOS device. The bipolar device is a device for controlling the operation of many photons and few photons by current, and large-scale integration is difficult to realize due to the complex manufacturing process of the bipolar device.
The rapid progress of the electronic industry puts higher and higher requirements on power integration, and the combination, modularization and power integration of power electronic devices gradually become mainstream requirements of the industry. The JFET as a voltage control multi-sub working device has good linear analog degree, and has the advantages of high input impedance, small 1/f noise, small temperature drift and the like because the channel of the JFET is positioned in a body, so the JFET is generally used as an input pair tube of an operational amplifier to effectively reduce the voltageImbalance is caused, and the conversion precision of the A/D and D/A converters and the smaller static output current of a low dropout regulator (LDO for short) are ensured. The CMOS is composed of N-channel and P-channel MOS field effect transistors and paired transistors, works in a push-pull mode to realize a logic function, and the CMOS logic device gradually becomes a mainstream device of an integrated circuit by virtue of high integration, strong anti-interference and ultralow power consumption. The power output stage DMOS tube is the core and key of the power integrated circuit. There are two main types of DMOS. A vertical double-diffused metal oxide semiconductor field effect transistor VDMOS and a lateral double-diffused metal oxide semiconductor field effect transistor LDMOS. The latter is widely adopted due to its easier compatibility with CMOS processes. LDMOS is a power device with a double-diffusion structure and has an on-resistance R ON R exists with device withstand voltage BV ON ∝BV 2.3～2.6 The relationship of (2) and (3) makes the withstand voltage and the on-resistance of the device have a contradiction relationship, and limits the high-voltage application of the LDMOS device. In order to overcome the problem, in 1979, a Resurf (Reduce Surface Field) technology is proposed by j.a.apples et al, and a Double Resurf technology is proposed by y.s.huang in 2001, which is widely applied to bulk silicon and SOI LDMOS devices. Semiconductor power circuits integrated on a single chip have been a research hotspot in the power electronics industry. In the prior art, a JFET device, a CMOS device and a DMOS device are usually used separately to form a power circuit, so that the number of elements, the number of interconnections and the number of welding points of a system are large, the system is poor in reliability, large in power consumption, high in cost, large in size and weight, and the development trend of light weight and integration in the electronic industry cannot be met. Therefore, the realization of the monolithic integration of JFET, CMOS and DMOS devices of active elements also becomes a technical problem to be solved by the technical personnel in the field, and the development of JFET-CMOS-DMOS integrated devices is significant. However, the integration technology of the JFET device has many problems such as poor compatibility, poor performance of the JFET device, and the like. Due to the JFET deviceDue to the particularity of the double-gate structure, technicians face to realize the monolithic integration of the low-voltage JFET, the high-voltage control part and the low-voltage logic part, the compatibility of the high-voltage DMOS and the low-voltage JFET and the compatibility of the JFET and the CMOS part still have integration obstacles, and due to the fact that the manufacturing process of the JFET device is complex, the saturation characteristic and the pinch-off characteristic of the JFET device cannot simultaneously meet application requirements, the performance of the JFET device and the development of related integrated operational amplifiers are limited.
Disclosure of Invention
In view of the above, the present invention provides a JCD (JFET-CMOS-DMOS) integrated device with integrated VDMOS, which integrates active components and passive components (or no passive components) including a low-voltage P-channel JFET (PJFET), a low-voltage CMOS and a high-voltage VDMOS on the same chip by using a single-chip integration technology, aiming at the defects existing in the power integrated circuit design adopting separate JFET, CMOS and DMOS devices.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a JCD integrated device of an integrated VDMOS is characterized by comprising a low-voltage PJFET device area, a low-voltage CMOS device area and a high-voltage VDMOS device area which are integrated on the same P-type substrate 1; a first N-type epitaxial layer 4 is arranged on the surface of the P-type substrate 1, and a second N-type epitaxial layer 8 is arranged on the surface of the first N-type epitaxial layer 4; the low-voltage PJFET device region, the low-voltage CMOS device region and the high-voltage VDMOS device region are arranged in the second N-type epitaxial layer 8 and are isolated from each other; a first N + buried layer 2 is arranged between the P-type substrate 1 and the first N-type epitaxial layer 4 below the high-voltage VDMOS device region; a second N + buried layer is arranged between the first N type epitaxial layer 4 and the second N type epitaxial layer 8 below the low-voltage CMOS device region; a second N + buried layer is arranged between the first N type epitaxial layer 4 and the second N type epitaxial layer 8 below the low-voltage CMOS device region; and a third N + buried layer is arranged between the first N-type epitaxial layer 4 and the second N-type epitaxial layer 8 below the low-voltage PJFET device region.
Further, the high-voltage VDMOS device region includes two mutually independent and isolated P wells 121 and 122 in the second N-type epitaxial layer 8, and each P well includes an N + source region and a P + contact region connected side by side; the N + source regions 161, 162 in the two P wells 121, 122 are relatively close and the P + contact regions 171, 172 are relatively far apart; the P + contact regions 171, 172 and portions of the N + source regions 161, 162 are connected by a source metal 20; the surfaces of the N + source regions 161 and 162, the P wells 121 and 122 positioned between the N + source regions 161 and 162 and the second N-type epitaxial layer 8 are provided with a gate oxide layer 14, and the upper surface of the gate oxide layer 14 is covered with a polysilicon gate region 151; the polysilicon gate region 151 and the periphery of the gate oxide layer 14 are isolated from the source metal 20 through the dielectric layer 18.
A first N-type through region 501 and a second N-type through region 901 which are mutually communicated and a first N-type through region 502 and a second N-type through region 902 which are mutually communicated are respectively arranged on two sides of a high-voltage VDMOS device region, the first N-type through region 501 and the first N-type through region 502 are arranged in a first N-type epitaxial layer 4, and the second N-type through region 901 and the second N-type through region 902 are arranged in a second N-type epitaxial layer 8; two first N-type punch-through regions 501 and 502 are respectively connected with two sides of the first N + buried layer 201; the surfaces of the two second N-type punch-through regions 901 and 902 respectively have a drain metal 19. A dielectric layer 18 is provided between the drain metal 19 and the source metal 20.
Furthermore, the surface of the second N-type epitaxial layer 8 outside the first N-type punch-through region 501 and the second N-type punch-through region 901 which are communicated with each other and the first N-type punch-through region 502 and the second N-type punch-through region 902 which are communicated with each other has a field oxide layer 11.
Further, the low-voltage CMOS device region comprises a low-voltage PMOS device region and a low-voltage NMOS device region; specifically, the NMOS device region includes a P well 123 in the second N type epitaxial layer 8, the P well 123 has therein a P + contact region 173 connected to the contact electrode metal 21, an N + source region 163 connected to the source metal 22, and an N + drain region 164 connected to the drain metal 23, respectively; the surface of the P well 123 between the N + source region 163 and the N + drain region 164 is provided with a gate oxide layer 14, and the upper surface of the gate oxide layer 14 is covered with a polysilicon gate region 152; dielectric layers 18 are arranged among the contact electrode metal 21, the source electrode metal 22 and the drain electrode metal 23 and on the surface of the polysilicon gate region 152; the PMOS device region includes a P + drain region 174 connected to the drain metal 24 and a P + source region 175 connected to the source metal 25 in the second N-type epitaxial layer 8, respectively; the surface of the second N-type epitaxial layer 8 between the P + drain region 174 and the P + source region 175 is provided with a gate oxide layer 14, and the upper surface of the gate oxide layer 14 is covered with a polysilicon gate region 153; a dielectric layer 18 is provided between the drain metal 24 and the source metal 25.
Further, in the second N-type epitaxial layer 8 near the P + source region 175 side of the low voltage NMOS device region, there is a second N-type punch-through region 903 connected to its contact electrode metal 26, the second N-type punch-through region 903 is punched through the second N-type epitaxial layer 8 and connected to the second N + buried layer 202. A dielectric layer 18 is provided between the contact electrode metal 26 and the source metal 25.
Further, the surface of the P-type epitaxial layer 3 between the low voltage PMOS and the low voltage NMOS has a field oxide layer 11.
Furthermore, two sides of the low-voltage CMOS device region are respectively provided with a P + buried layer, and the P + buried layers 301 and 302 are arranged between the P-type substrate 1 and the first N-type epitaxial layer 4; the two sides of the low-voltage CMOS device region further comprise a first P-type isolation region 601 and a second P-type isolation region 701 which are mutually communicated, and a first P-type isolation region 602 and a second P-type isolation region which are mutually communicated, wherein the first P- type isolation regions 601 and 602 are arranged in the first N-type epitaxial layer 4, and the second P-type isolation region is arranged in the second N-type epitaxial layer 8; the two first P- type isolation regions 601, 602 are connected to the corresponding P + buried layers 301, 302 below the two first P-type isolation regions, respectively, and the surfaces of the two second P-type isolation regions are provided with field oxide layers 11, respectively.
Further, the low-voltage PJFET device region includes a P-well 124 in the second N-type epitaxial layer 8, and the P-well 124 has a P + drain region 176 and a P + source region 177 connected to the drain metal 28 and the source metal 29, respectively; the top layer of P-well 124 between P + drain region 176 and P + source region 177 has an N-type gate region 13 connected to gate metal 27; a dielectric layer 18 is provided between the source metal 29, the drain metal 28 and the gate metal 27.
Further, the low-voltage PJFET device region further includes second N-type punch-through regions respectively disposed on two sides of the P-well 124, and the second N-type punch-through regions 904 and 905 on the two sides are respectively connected to two sides of the third N + buried layer 203; the surfaces of the two second N-type punch-through regions 904 and 905 are respectively provided with a gate metal 27. A dielectric layer 18 is provided between the gate metal 27 and other metals.
Furthermore, two sides of the low-voltage PJFET device region are respectively provided with a P + buried layer, and the P + buried layers 303 and 304 are arranged between the P-type substrate 1 and the first N-type epitaxial layer 4; the two sides of the low-voltage PJFET device region further comprise a first P-type isolation region 603 and a second P-type isolation region which are communicated with each other, and a first P-type isolation region 604 and a second P-type isolation region which are communicated with each other, wherein the first P- type isolation regions 603 and 604 are arranged in the first N-type epitaxial layer 4, and the second P-type isolation region is arranged in the second N-type epitaxial layer 8; the two first P- type isolation regions 603 and 604 are connected to the corresponding P + buried layers 303 and 304 below the two first P-type isolation regions, and the surfaces of the two second P-type isolation regions are provided with field oxide layers 11.
Further, the semiconductor device further comprises a well resistor region integrated in the same P-type substrate 1, wherein the well resistor region is arranged in the second N-type epitaxial layer 8. Specifically, the well resistor region includes a P well 125 in the first N-type epitaxial layer 4, the P well 125 has two independent and spaced P well contact regions 178, 179 therein, the upper portions of the two P well contact regions 178, 179 are respectively connected to the contact electrode metals 30, 31, and the dielectric layer 18 is disposed between the contact electrode metals 30, 31.
Furthermore, two sides of the well resistor region are respectively provided with a P + buried layer, and the P + buried layers 305 and 306 are arranged between the P-type substrate 1 and the first N-type epitaxial layer 4; the two sides of the well resistor region further comprise a first P-type isolation region 605 and a second P-type isolation region which are communicated with each other, and a first P-type isolation region 606 and a second P-type isolation region which are communicated with each other, wherein the first P-type isolation region 605 and the second P-type isolation region 606 are arranged in the first N-type epitaxial layer 4, and the second P-type isolation region is arranged in the second N-type epitaxial layer 8; the two first P- type isolation regions 605 and 606 are connected to the corresponding P + buried layers 305 and 306 below the two first P-type isolation regions, respectively, and the surfaces of the two second P-type isolation regions are provided with field oxide layers 11, respectively.
Further, the P-type substrate further comprises a poly capacitor region integrated on the same P-type substrate 1, and the poly capacitor region is arranged in the second N-type epitaxial layer 8. The poly capacitor comprises a P well 126 in a first N-type epitaxial layer 4, and two mutually independent and isolated P well contact regions 1710 and 1711 are arranged in the P well 126; the P- well contact regions 1710, 1711 are connected to the corresponding contact electrode metals 32, 34 above them; the surface of the P trap 126 between the two P trap contact regions 1710 and 1711 is provided with a gate oxide layer 14, and the upper surface of the gate oxide layer 14 is covered with polysilicon 154 connected with a contact electrode metal 33; a dielectric layer 18 is arranged among the contact electrode metals 32, 33 and 34; the surface of the second N-type epitaxial layer 8 on both sides of the P-well 126 is provided with a field oxide layer 11.
Further, still including the polyresistor district of integration in same P type substrate 1, polyresistor district sets up second N type epitaxial layer 8 top, have field oxide 11 between polyresistor district and the second N type epitaxial layer 8. Specifically, the poly resistance region includes a P-type doped region 155 and contact electrode metals 35, 36 disposed at both sides of the P-type doped region 155 and connected thereto; a dielectric layer 18 is provided between the contact electrode metals 35, 36.
Further, still including the polydiode area of integration in same P type substrate 1, polydiode area sets up second N type epitaxial layer 8, have field oxide 11 between polydiode area and second N type epitaxial layer 8. Specifically, the poly diode region includes an N-type doped cathode region 156 and a P-type doped anode region 157 which are arranged on the surface of the field oxide layer 11 and connected side by side, a cathode metal 37 connected with the N-type doped cathode region 156, and an anode metal 38 connected with the P-type doped anode region 157; a dielectric layer 18 is provided between the cathode metal 37 and the anode metal 38.
Furthermore, the CMOS device region, the low-voltage PJFET device region and the well resistor region form a pair-pass isolation with the corresponding P type isolation regions through the P + buried layers 301-306 to realize junction isolation.
On the other hand, the invention provides a preparation method of a JCD integrated device integrated with a VDMOS, which is characterized by comprising the following steps:
step 1: selecting a P-type semiconductor material as a P-type substrate;
and 2, step: implanting N-type impurities into the P-type substrate 1 for diffusion to form a first N + buried layer arranged below the high-voltage VDMOS device region;
and step 3: implanting ions into the P-type substrate 1 to form heavily doped P + buried layers 301-306 arranged below the low-voltage CMOS device region, the low-voltage PJFET device region and the well resistor region through diffusion;
and 4, step 4: epitaxially forming a first N-type epitaxial layer 4 on the P-type substrate 1;
and 5: implanting N-type impurities into the first N-type epitaxial layer 4, and diffusing to form first N-type punch-through regions 501 and 502 arranged on two sides of the high-voltage VDMOS device region, so that the two first N-type punch-through regions 501 and 502 are respectively connected with two sides of the first N + buried layer;
step 6: implanting ions into the first N-type epitaxial layer 4 to form P-type impurity diffusion to form first P-type isolation regions 601-606 arranged at two sides of the low-voltage CMOS device region, the low-voltage PJFET device region and the well resistor region; and the first P-type isolation regions 601-606 are connected with the corresponding P + buried layers 301-306 to form a pair of through isolation;
and 7: forming a field oxide layer 11 on the surface of the first N-type epitaxial layer 4 to realize the subsequent photoetching of a low-voltage CMOS device region and a low-voltage JFET device region, and performing ion implantation and N-type impurity diffusion in the first N-type epitaxial layer 4 to form a second N + buried layer and a third N + buried layer which are respectively arranged below the CMOS device region and the JFET device region;
and 8: epitaxially forming a second N-type epitaxial layer 8 on the first N-type epitaxial layer 4;
and step 9: implanting N-type impurities into the first N-type epitaxial layer 4, and diffusing to form second N-type through regions 901-905 which are arranged on two sides of the high-voltage VDMOS device region, the low-voltage JFET device region and one side of the low-voltage CMOS device region, so that the two second N-type through regions 901 and 902 arranged on two sides of the high-voltage VDMOS device region are respectively communicated with the first N-type through regions 501 and 502; the second N-type punch-through region 903 arranged on one side of the low-voltage CMOS device region is connected with one side of the second N + buried layer 20), and the second N-type punch-through regions 904 and 905 arranged on two sides of the low-voltage JFET device region are respectively connected with two sides of the third N + buried layer 203;
step 10: implanting ions into the first N-type epitaxial layer 4 to form P-type impurity diffusion to form second P-type isolation regions arranged at two sides of the low-voltage CMOS device region, the low-voltage PJFET device region and the well resistor region; and the second P-type isolation region is communicated with the corresponding first P-type isolation regions 601-606;
step 11: forming field oxide layers 11 on the surfaces of the device isolation region and the surfaces of the regions where the poly resistor and the poly diode are located so as to realize the subsequent photoetching of the active region;
step 12: implanting N-type impurities into the position of the VDMOS device region on the surface of the second N-type epitaxial layer 8 to form a JFET region;
step 13: forming P well regions 121-126 of a high-voltage VDMOS device region, a low-voltage CMOS device region, a well resistor region, a low-voltage PJFET device region and a poly capacitor region in the N-type epitaxial layer 4;
step 14: implanting N-type impurities into the JFET region to form an N-type gate region 13 of a low-voltage PJFET device region;
step 15: forming a gate oxide layer 14 of a high-voltage VDMOS device area, a low-voltage CMOS device area and a poly capacitor area;
step 16: forming a high-voltage VDMOS device area, a low-voltage CMOS device area, a poly capacitor area, a poly resistor and a polysilicon gate area of a poly diode;
step 17; implanting N-type impurities into the polycrystalline silicon gate region, and forming an N-type doped polycrystalline silicon gate region 151, an N + source region 161 and an N + drain region 162 of the high-voltage VDMOS device region, an N-type doped polycrystalline silicon gate region 152, an N + source region 163 and an N + drain region 164 of the low-voltage NMOS device region, an N-type doped polycrystalline silicon gate region 153 of the low-voltage PMOS device region, N-type doped polycrystalline silicon 154 of the poly capacitor region and an N-type doped cathode region 156 of the poly diode by diffusion;
step 19: depositing to form a dielectric layer (ILD) and refluxing to realize planarization, and etching ohmic holes in the region of the chip connecting lead;
step 20: activating impurity ions by adopting an annealing process;
step 21: the metallization forms drain metal 19 and source metal 20 for the high voltage VDMOS device region, contact electrode metal 21, source metal 22 and drain metal 23 for the low voltage NMOS device region, drain metal 24, source metal 25 and contact electrode metal 26 for the low voltage PMOS device region, gate metal 27, drain metal 28 and source metal 29 for the low voltage PJFET device region, contact electrode metal 30, 31 for the well resistor region, contact electrode metal 32, 33, 34 for the poly capacitor region, contact electrode metal 35, 36 for the poly resistor, and cathode metal 37 and anode metal 38 for the poly diode.
Further, the N-type impurity is phosphorus or arsenic.
Further, the process sequence of the step 2 and the step 3 is not in sequence, the process sequence of the step 5 and the step 6 is not in sequence, the process sequence of the step 9 and the step 10 is not in sequence, and the process sequence of the step 17 and the step 18 is not in sequence.
Further, the N-type punch-through region in step 9 is a drain terminal leading-out terminal of the VDMOS device, and is also a leading-out terminal of the N + buried layer of the low-voltage JFET device region.
Further, the step 11 adopts local oxidation to realize the isoplanar process, so that the step height of the chip surface is effectively reduced.
Further, the step 14 can meet the requirements of different pinch-off voltages, saturation currents, resistances and breakdown voltages by adjusting the implantation dose and the junction push-off time of the N-type gate region 13 of the low-voltage PJFET device region.
Further, the method also comprises the step of forming a high-voltage VDMOS device region on the surface of the second N-type epitaxial layer 8 to form an N-type electron accumulation layer as an N-type conduction channel; compared with a high-voltage enhancement type VDMOS device region manufactured by injection without an N-type accumulation layer, the high-voltage depletion type (normally-on type) VDMOS device region can be manufactured by adding the step.
Furthermore, the low-voltage CMOS device area is preferably provided with a plurality of sub guard rings and an N + buried layer, so that latch-up can be effectively prevented and the reliability of the device can be improved under the condition that the threshold voltage and the breakdown voltage of NMOS and PMOS are not influenced.
Compared with the prior art, the invention has the following beneficial effects:
(1) The invention integrates active elements of low voltage PJFET, low voltage CMOS, high voltage VDMOS and (or not) passive elements on the same chip, and the devices have good isolation effect and are compatible with each other, so that the devices can exert respective advantages.
(2) The invention can integrate JFET, CMOS and DMOS active elements and passive elements such as poly capacitor, poly resistor and poly diode to form a circuit, and a circuit designer can select required devices to obtain different circuits according to actual requirements, so that the abundant device types can bring great flexibility to circuit design. The invention is particularly suitable for the fields of power management ICs, circuit protection products and JFET integrated operational amplifiers.
(3) The invention provides a preparation method of a JCD integrated device, the whole process uses fewer masks, the manufacturing process is simple, the reusability of process levels is strong, and the control of the manufacturing cost is facilitated; meanwhile, a buried layer and punch-through injection are utilized to form a pair of punch-through isolation, all devices are manufactured in an isolation island, high-low voltage compatibility, high performance, high efficiency and high reliability are realized on a limited chip area, and a chip manufactured by applying the JCD integration technology has better comprehensive performance and is beneficial to the development of single-chip power system integration.
(4) The high-voltage VDMOS is integrated, the concentration of a drift region can be obviously improved while the breakdown voltage is not changed, and the on-resistance of a device is greatly reduced.
(5) The design of the integrated device is beneficial to reaching excellent compromise in performance, function and cost, and is convenient to realize product diversification, thereby rapidly meeting the continuously increased market demand.
(6) Compared with a circuit formed by discrete devices, the monolithic integration of the JFET, the CMOS and the DMOS device obviously reduces the number of elements, interconnection number and welding point number of the system, is favorable for reducing the volume and weight of the system, reduces electromagnetic interfaces and brings high reliability to the system.
Drawings
FIG. 1 is a schematic diagram of the main process flow of the present invention.
Fig. 2 is a schematic diagram of the overall structure of the JCD integrated device of the present invention.
Fig. 3 is a schematic structural diagram of a high-voltage depletion type VDMOS device region implemented by the present invention.
Fig. 4 is a schematic structural diagram of a CMOS device region implemented by the present invention.
Fig. 5 is a schematic diagram of the structure of a PJFET device region implemented by the present invention.
Fig. 6 is a schematic diagram of a well resistor region structure implemented by the present invention.
Fig. 7 is a schematic structural diagram of a Poly capacitor region implemented in the present invention.
Fig. 8 is a schematic structural diagram of a Poly resistance region implemented in the present invention.
Fig. 9 is a schematic structural diagram of a Poly diode region implemented in the present invention.
In the figure: 1 is a P-type substrate, 2 is an N + buried layer, 301-306 are P + buried layers, 4 is a first N-type epitaxial layer, 501-502 are first N + punch-through regions, 601-606 are first P + isolation regions, 8 is a second N-type epitaxial layer, 901-905 are second N + punch-through regions, 11 is a field oxide layer, 121-126 are P wells, 13 is an N-type gate region of a JFET device region, 14 is a gate oxide layer, 151 is a polysilicon gate of a VDMOS device region, 152 is a polysilicon gate of a low voltage NMOS device region, 153 is a polysilicon gate of a low voltage PMOS device region, 154 is a phosphorus doped polysilicon gate, 155 is a boron doped polysilicon resistor, 156 is an N-type doped cathode region of a poly diode region, 157 is a P-type doped anode region of a poly diode region, 161, 162 is an N + source region of a VDMOS device region, 164 is an N + source region and an N + source region of a low voltage NMOS device region, 171, 172 is a P + drain region, and 173 is a P + contact region of a low voltage NMOS device region, 174, 175 are the P + drain and P + source regions of the low voltage PMOS device region, 176, 177 are the P + drain and P + source regions of the low voltage JFET device region, 178, 179 are the P + drain and P + source regions of the well resistor region, 1710, 1711 are the P well contact region of the poly capacitor region, 18 are the dielectric layers, 19, 20 are the drain and source metals of the high voltage VDMOS device region, 21, 22, 23 are the contact electrode metal, source metal and drain metal of the low voltage NMOS device region, 24, 25, 26 are the drain, source and contact electrode metals of the low voltage PMOS device region, 27, 28, 29 are the gate, drain and source metals of the low voltage PJFET device region, 30, 31 are the contact electrode metal of the well resistor region, 32, 33, 34 are the contact electrode metal of the poly capacitor region, 35, 36 are the contact electrode metal of the poly resistor, 37. 38 are the cathode metal and anode metal of the poly diode, respectively.
Detailed Description
The structure of the integrated device of the present invention is described in detail below with reference to the drawings of the specification:
as shown in fig. 2, the present invention provides a JCD integrated device based on N-type epitaxy, which is characterized by comprising a high voltage VDMOS device region (see fig. 3), a low voltage CMOS device region (see fig. 4), a low voltage PJFET device region (see fig. 5), a well resistor region (see fig. 6), a poly capacitor region (see fig. 7), a poly resistor region (see fig. 8) and a poly diode region (see fig. 9) integrated on the same P-type substrate 1; the low-voltage CMOS device area comprises a low-voltage PMOS device area and a low-voltage NMOS device area; a first N-type epitaxial layer 4 is arranged on the surface of the P-type substrate 1, and a second N-type epitaxial layer 8 is arranged on the surface of the first N-type epitaxial layer 4; the high-voltage VDMOS device region, the low-voltage PMOS device region, the low-voltage NMOS device region, the well resistor region, the low-voltage PJFET device region and the poly capacitor region are arranged in the second N-type epitaxial layer 8, the poly resistor region and the poly diode region are arranged on the surface of a field oxide layer 11 on the second N-type epitaxial layer 8, and the device regions are isolated from each other by forming a pair-pass isolation;
as shown in fig. 3, a first N + buried layer is arranged between the P-type substrate 1 and the first N-type epitaxial layer 4 under the high-voltage VDMOS device region; the high-voltage VDMOS comprises two mutually independent and isolated P wells 121 and 122 in a second N-type epitaxial layer 8, wherein each P well comprises an N + source region and a P + contact region which are connected in parallel; the N + source regions 161, 162 in the two P-wells 121, 122 are relatively close and the P + contact regions 171, 172 are relatively far apart; the P + contact regions 171, 172 and portions of the N + source regions 161, 162 are connected by an electrode metal 20; the surfaces of the N + source regions 161 and 162, the P wells 121 and 122 positioned between the N + source regions 161 and 162 and the second N-type epitaxial layer 8 are provided with a gate oxide layer 14, and the upper surface of the gate oxide layer 14 is covered with a polysilicon gate region 151; the periphery of the polycrystalline silicon gate region 151 and the periphery of the gate oxide layer 14 are isolated from the source metal 20 through the dielectric layer 18; a first N-type punch-through region 501 and a second N-type punch-through region 901 which are mutually communicated and a first N-type punch-through region 502 and a second N-type punch-through region 902 which are mutually communicated are respectively arranged on two sides of a high-voltage VDMOS device region, the first N-type punch-through regions 501 and 502 are arranged in a first N-type epitaxial layer 4, and the second N-type punch-through regions 901 and 902 are arranged in a second N-type epitaxial layer 8; two first N-type punch-through regions 501 and 502 are respectively connected with two sides of the first N + buried layer 201; the surfaces of the two second N-type punch-through regions 901 and 902 are respectively provided with drain metal 19; a dielectric layer 18 is arranged between the drain metal 19 and the source metal 20; the surfaces of the first N-type through region 501 and the second N-type through region 901 which are mutually communicated and the surfaces of the second N-type epitaxial layer 8 outside the first N-type through region 502 and the second N-type through region 902 which are mutually communicated are provided with field oxide layers 11;
as shown in fig. 4, a second N + buried layer is arranged between the first N-type epitaxial layer 4 and the second N-type epitaxial layer 8 under the low-voltage CMOS device region; the NMOS device region includes a P well 123 in the second N-type epitaxial layer 8, and the P well 123 has a P + contact region 173 connected to the contact electrode metal 21, an N + source region 163 connected to the source metal 22, and an N + drain region 164 connected to the drain metal 23; the surface of the P well 123 between the N + source region 163 and the N + drain region 164 is provided with a gate oxide layer 14, and the upper surface of the gate oxide layer 14 is covered with a polysilicon gate region 152; dielectric layers 18 are arranged among the contact electrode metal 21, the source electrode metal 22 and the drain electrode metal 23 and on the surface of the polysilicon gate region 152; the PMOS device region includes a P + drain region 174 connected to the drain metal 24 and a P + source region 175 connected to the source metal 25 in the second N-type epitaxial layer 8, respectively; the surface of the second N-type epitaxial layer 8 between the P + drain region 174 and the P + source region 175 is provided with a gate oxide layer 14, and the upper surface of the gate oxide layer 14 is covered with a polysilicon gate region 153; a dielectric layer 18 is arranged between the drain metal 24 and the source metal 25; a second N-type punch-through region 903 is arranged in the second N-type epitaxial layer 8 close to one side of the low-voltage NMOS device region, and the second N-type punch-through region 903 penetrates through the second N-type epitaxial layer 8 and is connected with the second N + buried layer 202; the surface of the second N-type punch-through region 903 is provided with a contact electrode metal 26, two sides of the low-voltage CMOS device region are respectively provided with a P + buried layer, the P + buried layers 301 and 302 are arranged between the P-type substrate 1 and the first N-type epitaxial layer 4, two sides of the low-voltage CMOS device region further comprise a first P-type isolation region 601 and a second P-type isolation region which are communicated with each other, and a first P-type isolation region 602 and a second P-type isolation region which are communicated with each other, the first P-type isolation regions 601 and 602 are arranged in the first N-type epitaxial layer 4, the second P-type isolation region is arranged in the second N-type epitaxial layer 8, and the two first P-type isolation regions 601 and 602 are respectively connected with the corresponding P + buried layers 301 and 302 below the two first P-type isolation regions 601 and 602 to form a punch-through isolation;
as shown in fig. 5, a third N + buried layer is provided between the first N-type epitaxial layer 4 and the second N-type epitaxial layer 8 under the low-voltage PJFET device region; the low-voltage PJFET device region comprises a P-well 124 in the second N-type epitaxial layer 8, the P-well 124 having therein a P + drain region 176 and a P + source region 177 connected to the drain metal 28 and the source metal 29, respectively; the top layer of the P-well 124 between the P + drain region 176 and the P + source region 177 has an N-type gate region 13 connected to the gate metal 27; two sides of the P well 124 in the low-voltage PJFET device region are respectively provided with a second N-type punch-through region, and the second N-type punch-through regions 904 and 905 at the two sides are respectively connected with two sides of the third N + buried layer 203; and gate metal 27 is respectively arranged on the second N-type through regions 904 and 905 on the two sides, and a dielectric layer 18 is arranged among the source metal 29, the drain metal 28 and the gate metal 27. The two sides of the low-voltage PJFET device region are respectively provided with a P + buried layer, the P + buried layers 303 and 304 are arranged between the P-type substrate 1 and the first N-type epitaxial layer 4, the two sides of the low-voltage PJFET device region also comprise a first P-type isolation region 603 and a second P-type isolation region 703 which are communicated with each other, and a first P-type isolation region 604 and a second P-type isolation region which are communicated with each other, the first P- type isolation regions 603 and 604 are arranged in the first N-type epitaxial layer 4, the second P-type isolation region is arranged in the second N-type epitaxial layer 8, the surfaces of the two second P-type isolation regions are respectively provided with a field oxide layer 11, and the two first P- type isolation regions 603 and 604 are respectively connected with the corresponding P + buried layers 303 and 304 below the two first P-type isolation regions to form a pair-connection isolation;
as shown in fig. 6, the well resistor region includes a P well 125 in the N-type epitaxial layer 4, the P well 125 has two independent and spaced P well contact regions 178, 179 therein, the upper portions of the two P well contact regions 178, 179 are respectively connected to the contact electrode metals 30, 31, and the dielectric layer 18 is disposed between the contact electrode metals 30, 31; the two sides of the well resistor region are respectively provided with a P + buried layer, the P + buried layers 305 and 306 are arranged between the P-type substrate 1 and the first N-type epitaxial layer 4, the two sides of the well resistor region also comprise a first P-type isolation region 605 and a second P-type isolation region which are mutually communicated, and a first P-type isolation region 606 and a second P-type isolation region which are mutually communicated, the first P-type isolation regions 605 and 606 are arranged in the first N-type epitaxial layer 4, the second P-type isolation region is arranged in the second N-type epitaxial layer 8, the surfaces of the two second P-type isolation regions are respectively provided with a field oxide layer 11, and the two first P-type isolation regions 605 and 606 are respectively connected with the corresponding P + buried layers 305 and 306 below the two first P-type isolation regions to form a communicated isolation;
as shown in fig. 7. The poly capacitor comprises a P well 126 in an N-type epitaxial layer 4, and two mutually independent and isolated P well contact regions 1710 and 1711 are arranged in the P well 126; the P- well contact regions 1710, 1711 are connected to the corresponding contact electrode metals 32, 34 above them; the surface of the P trap 126 between the two P trap contact regions 1710 and 1711 is provided with a gate oxide layer 14, and the upper surface of the gate oxide layer 14 is covered with polysilicon 154 connected with a contact electrode metal 33; a dielectric layer 18 is arranged among the contact electrode metals 32, 33 and 34; the surface of the second N-type epitaxial layer 8 on both sides of the P-well 126 is provided with a field oxide layer 11.
As shown in fig. 8. Still including the polyresistor district of integration in same P type substrate 1, polyresistor district sets up second N type epitaxial layer 8 top, have field oxide 11 between polyresistor district and second N type epitaxial layer 8. Specifically, the poly resistance region includes a P-type doped region 155 and contact electrode metals 35, 36 disposed at both sides of the P-type doped region 155 and connected thereto; a dielectric layer 18 is provided between the contact electrode metals 35, 36.
As shown in fig. 9. Still including the polydiode area of integration in same P type substrate 1, the polydiode area sets up second N type epitaxial layer 8, have field oxide 11 between polydiode area and second N type epitaxial layer 8. Specifically, the poly diode region includes an N-type doped cathode region 156 and a P-type doped anode region 157 which are arranged on the surface of the field oxide layer 11 and connected side by side, a cathode metal 37 connected with the N-type doped cathode region 156, and an anode metal 38 connected with the P-type doped anode region 157; a dielectric layer 18 is provided between the cathode metal 37 and the anode metal 38.
The following describes the manufacturing process of the present invention in detail with reference to fig. 1 and specific examples. The teachings of the present invention are not limited to any particular embodiment nor represent the best embodiment, and general alternatives known to those skilled in the art are also intended to be encompassed within the scope of the present invention.
Example 1;
the embodiment provides a method for preparing a JCD integrated device based on N-type epitaxy, as shown in fig. 1, a schematic flow diagram of a preparation process of the integrated device of the present invention, which specifically includes the following main process steps:
step 1: preparing a substrate;
preparing a boron-doped silicon substrate with a <100> crystal orientation as a P-type substrate 1; in the embodiment, the resistivity of the P-type substrate 1 is 30-50 omega cm, and the thickness of the substrate is 550-750 um;
and 2, step: forming an N + buried layer;
etching the surface of the high-voltage VDMOS device region of the P-type silicon substrate 1 prepared in the step 1 by adopting an NBL1 (N-Buried Layer) plate, and performing ion implantation of phosphorus without high-temperature junction push to form an N + Buried Layer 201; in this example, the ion implantation energy was 60KeV, and the ion implantation dose was 1e15 to 5e15cm -2 ；
And step 3: forming a P + buried layer;
etching the surfaces of the CMOS device area, the JFET device area and the well resistor area of the P-type silicon substrate 1 prepared in the step (1) by adopting a PBL (PBURIED Layer) plate, injecting boron into ions, and forming P + buried layers 301-306 without high-temperature junction pushing; in this embodiment, the ion implantation energy is 60KeV, and the ion implantation dose is 1e 15-1e16 cm -2 ；
And 4, step 4: n-type epitaxy for the first time;
epitaxially growing an N-type semiconductor on the P-type substrate 1Forming a first N-type epitaxial layer 4; in this embodiment, the epitaxial growth temperature is 1100 deg.C, the epitaxial thickness is 15-30 um, and the epitaxial concentration is 1e 14-1 e15cm -3 ；
And 5: forming an N + punch-through;
etching two sides of the surface of a high-voltage VDMOS device region of the first N-type epitaxial layer 4 by using an N + PT plate, implanting phosphorus by ions, and then pushing the junction at high temperature for a long time to enable an N + through region to penetrate through the whole first N-type epitaxial layer 4 and be connected with an N + buried layer by using buried layer back expansion and high-temperature pushing junction to form first N-type through regions 501-502 arranged on two sides of the high-voltage VDMOS device region; in this example, the implantation energy is 120-200 KeV, and the implantation dose is 1e 15-3 e15cm -2 The temperature is 1150 ℃, and the knot pushing time is 100-300 min;
step 6: forming P + isolation;
etching one side of the surface of a CMOS device region in the first N-type epitaxial layer 4 and two sides of the surfaces of a JFET device region and a well resistor region by using a P + ISO version, implanting boron through ions, performing long-time high-temperature junction pushing, and enabling a P + isolation region to penetrate through the whole first N-type epitaxial layer 4 and to be communicated with a corresponding P + buried layer by using buried layer reverse expansion and high-temperature junction pushing to form first P + isolation regions 601-606 arranged on one side of the surface of the CMOS device region and two sides of the surfaces of the JFET device region and the well resistor region; in this example, the implantation energy is 120-200 KeV, and the implantation dose is 1e 15-3 e15cm -2 The temperature is 1150 ℃, and the knot pushing time is 200-400 min;
and 7: forming an N + buried layer;
etching the surfaces of the CMOS device region and the JFET device region of the first N-type epitaxial layer 4 by adopting an NBL2 plate, implanting phosphorus by ions, and forming a second N + buried layer 202 and a third N + buried layer 203 which are respectively arranged below the CMOS device region and the JFET device region without high-temperature junction pushing; in this example, the implantation energy was 60KeV, and the implantation dose was 1e 15-5 e15cm -2 ；
And 8: performing N-type epitaxy for the second time;
epitaxially growing an N-type semiconductor layer on the first N-type epitaxial layer 4 to form a second N-type epitaxial layer 8; in this embodiment, the epitaxial growth temperature is 1100 deg.C, the epitaxial thickness is 15-30 um, and the epitaxial concentration is1e14～1e15cm -3 ；
And step 9: forming an N + punch-through;
etching both sides of the surfaces of the high-voltage VDMOS device area and the JFET device area of the second N-type epitaxial layer 8 and one side of the surface of the CMOS device area by using an N + PT plate, injecting phosphorus, performing long-time high-temperature junction pushing, and enabling the N + through area to penetrate through the whole second N-type epitaxial layer 8 and be connected with the first N-type through area by using buried layer reverse expansion and high-temperature junction pushing to form second N-type through areas 901-905 arranged on both sides of the high-voltage VDMOS device area; in this example, the implantation energy is 120-200 KeV, and the implantation dose is 1e 15-3 e15cm -2 The temperature is 1150 ℃, and the knot pushing time is 100-300 min;
step 10: forming P + isolation;
etching the surface side of the CMOS device region of the second N-type epitaxial layer 8 and the surface sides of the JFET device region and the well resistor region by utilizing a P + ISO version, injecting boron ions, performing long-time high-temperature junction pushing, and performing reverse expansion and high-temperature junction pushing on a buried layer to enable a P + isolation region to penetrate through the whole second N-type epitaxial layer 8 and be communicated with the corresponding first P + isolation regions 601-606 so as to form second P + isolation regions arranged on the surface side of the CMOS device region and the surface sides of the JFET device region and the well resistor region; in this example, the implantation energy is 120-200 KeV, and the implantation dose is 1e 15-3 e15cm -2 The temperature is 1150 ℃, and the knot pushing time is 200-400 min;
step 11: forming a field oxide layer;
thermally growing an oxide layer and depositing Si 3 N 4 Carrying out photoetching on Active regions of the devices by adopting an Active photoetching plate, thermally growing thick oxide layers in an isolation region, a Poly resistor and a Poly diode region of each device, wherein the thickness of the oxide layers is about 2 mu m, and forming a field oxide layer 11 on the second N-type epitaxial layer 8; then removing Si in the active region 3 N 4 And a thin oxide layer. In the step, field oxide layers 11 are formed on the surfaces of the device isolation region and the surfaces of the regions where the poly resistor and the poly diode are located so as to realize the subsequent photoetching of the active region;
step 12: injecting a JFET region of the VDMOS;
second N-type epitaxy on VDMOS device regionThe upper surface of the layer adopts a JFET plate, phosphorus is implanted by ions, the implantation energy is 120kev, and the implantation dosage is 1e 12-4 e12cm -2 (ii) a Therefore, the resistance of the JFET part of the VDMOS can be reduced, and the aim of reducing the resistance of the whole VDMOS is fulfilled;
step 13: preparing a P well;
etching the surfaces of the high-voltage VDMOS device area, the CMOS device area, the well resistor area, the JFET device area and the Poly capacitor area of the second N-type epitaxial layer 8 by adopting a P-well plate, injecting boron and performing high-temperature junction pushing to form P wells 121-122 of the VDMOS device area, a P well 123 of the low-voltage NMOS device area, a P well 124 of the well resistor area, a P well 125 of the JFET device area and a P well 126 of the Poly capacitor area; in this example, the implantation energy was 120KeV and the implantation dose was 5e13 to 1e14cm -2 The temperature is 1150 ℃, and the knot pushing time is 100-200 min;
step 14: preparing an N-type grid electrode area of the JFET;
after etching the upper surface of the second N-type epitaxial layer 8 in the JFET device area by adopting an N1 plate, injecting phosphorus into low-energy ions and performing high-temperature junction pushing to form an N-type grid electrode area 13 in the low-voltage PJFET device area; in this example, the implantation energy was 60KeV, and the implantation dose was 1e 15-5 e15cm -2 The temperature is 1150 ℃, and the knot pushing time is 30-50 min;
step 15: n-type accumulation layer (Nacc) implant;
injecting phosphorus into the whole surface of the second N-type epitaxial layer 8 of the high-voltage VDMOS device region by adopting a Nacc plate without a high-temperature diffusion process, forming an electron accumulation layer on the surface, and forming an original N-type conducting channel; in this example, the implantation energy was 60KeV, and the implantation dose was 5e12 to 1e13 cm -2 ；
Step 16: preparing gate oxide and polysilicon;
growing a thin oxide layer and removing to obtain a pure surface; then growing gate oxide 14 on the whole area of the upper surface of the second N-type epitaxial layer 8, depositing polycrystalline silicon and oxidizing Poly, and etching by adopting a Poly plate to form a polycrystalline silicon gate area of a high-voltage VDMOS (vertical double-diffused metal oxide semiconductor) device area, a low-voltage CMOS (complementary metal oxide semiconductor) device area, a Poly capacitor area, a Poly resistor area and a Poly diode area;
and step 17: injecting N +;
exposing and developing polysilicon gate regions of a high-voltage VDMOS device region, a low-voltage CMOS device region, a Poly capacitor region, a Poly resistor region and a Poly diode region by adopting an N2 plate, and injecting phosphorus to form a polysilicon gate region 151, source regions 161-162 of the high-voltage VDMOS, a polysilicon gate region 152, a source region 163 and a drain region 164 of an N-type MOS device of the CMOS device region, a polysilicon gate region 153 of a p-type MOS device, a phosphorus-doped polysilicon gate 154 of the Poly capacitor region and an N-type doped cathode region 156 of the Poly diode region; in this example, the implantation energy was 60KeV and the implantation dose was 1e 15-5 e15cm -2 ；
exposing and developing the P well regions 121-126, injecting boron, and forming P + contact regions 171 and 172 of a high-voltage VDMOS device region, a P + source region 174 and a P + drain region 175 of a low-voltage PMOS device region, a P + contact region 173 of a low-voltage NMOS device region, a P + drain region 176 and a P + source region 177 of a low-voltage PJFET device region, P well contact regions 178 and 179 of a well resistance region, P well contact regions 1710 and 1711 of a poly capacitance region, a P type doped region 155 of a poly resistance and a P type doped anode region 157 of a poly diode through diffusion; in this example, the implantation energy was 60KeV and the implantation dose was 1e15 to 1e16cm -2 ；
Step 19: depositing BPSG13 to form a dielectric layer (ILD) and refluxing to realize planarization, and etching an ohmic hole in the region of the chip connecting lead;
step 20: activating impurity ions by adopting an annealing process, specifically annealing at 850 ℃ for 30min in the embodiment;
step 21: the metallization forms drain metal 19 and source metal 20 for the high voltage VDMOS device region, contact electrode metal 21, source metal 22 and drain metal 23 for the low voltage NMOS device region, drain metal 24, source metal 25 and contact electrode metal 26 for the low voltage PMOS device region, gate metal 27, drain metal 28 and source metal 29 for the low voltage PJFET device region, contact electrode metal 30, 31 for the well resistor region, contact electrode metal 32, 33, 34 for the poly capacitor region, contact electrode metal 35, 36 for the poly resistor, and cathode metal 37 and anode metal 38 for the poly diode.
The 13 main ion implantation processes related by the invention comprise: n + buried layer injection, P + buried layer injection, N + PT1 injection, P + ISO injection, N + buried layer injection, N + PT2 injection, P + ISO injection, JFET region injection of VDMOS, P well injection, grid N-type region injection of JFET, N-type accumulation layer (Nacc) injection, N + injection and P + injection.
Devices that can be made according to the present invention are shown in fig. 3-9. Step 1 forming a P-type substrate 1 of fig. 3 to 9; step 2, forming an N + buried layer 201 of FIG. 2; step 3, forming P + buried layers 301-306 of figures 4-6; step 4, forming a first N type epitaxial layer 4 shown in the figures 3-9; step 5, forming first N-type punch-through areas 501-502 in the figure 3; step 6 forms the first P-type isolation regions 601-606 of fig. 4-6; step 7 forms 202 of fig. 5 and 203 of fig. 6; step 8, forming a second N-type epitaxial layer 8 shown in the figures 3-9; step 9, forming second N-type punch-through regions 901-905 of figures 3-5; step 10 forming a second P-type isolation region of fig. 4-6; step 11 forming a field oxide layer 11 of fig. 3-9; the portion formed in step 12 is not directly shown in the figure, and is located in the portion between the two P wells 121 and 122 in fig. 3; step 13 forms the P-wells 121-126 of fig. 3-7; step 14 forms the N-type gate region 13 of fig. 5; the part formed in step 15 is not directly shown in the figure, and is located at the interface between the second N-type epitaxial layer 8, the second N-type punch-through regions 901 and 902, the P wells 121 and 122, the N + source region 161, the N + drain region 162, and the P + contact regions 171 and 172, and the gate oxide layer 14, the dielectric layer 18, the drain metal 19, and the source metal 20 in fig. 2; step 16 forms gate oxide 14 of fig. 3, 4, 5, N-doped polysilicon gate region 151 of fig. 3, N-doped polysilicon gate regions 152-153 of fig. 4, N-doped polysilicon 154 of fig. 7, and N-doped cathode region 156 of fig. 9; step 17 forms N + source regions 161, 163 of fig. 3 and N + drain regions 162, 164 of fig. 4; step 18 forms the P + contact regions 171, 172 of fig. 3, the P + contact regions 173, 174, and 175 of fig. 4, the P + drain regions 176 and 177 of fig. 5, the P-well contact regions 178, 179 of fig. 6, and the P-well contact regions 1710, 1711 of fig. 7; step 21 forms electrode metals 19 to 38 of fig. 3 to 9.
While the present invention has been particularly shown and described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (9)
1. A JCD integrated device of an integrated VDMOS is characterized by comprising a low-voltage PJFET device area, a low-voltage CMOS device area and a high-voltage VDMOS device area which are integrated on the same P-type substrate; a first N-type epitaxial layer is arranged on the surface of the P-type substrate, and a second N-type epitaxial layer is arranged on the surface of the first N-type epitaxial layer; the high-voltage VDMOS device region is arranged in a first N-type epitaxial layer and a second N-type epitaxial layer, the low-voltage PJFET device region and the low-voltage CMOS device region are arranged in the second N-type epitaxial layer, and the device regions are isolated from each other; a first N + buried layer is arranged between the P-type substrate below the high-voltage VDMOS device region and the first N-type epitaxial layer; a second N + buried layer is arranged between the first N type epitaxial layer and the second N type epitaxial layer below the low-voltage CMOS device region; a third N + buried layer is arranged between the first N-type epitaxial layer and the second N-type epitaxial layer below the low-voltage PJFET device region;
the high-voltage VDMOS device region comprises two mutually independent and isolated P wells in a second N-type epitaxial layer, and each P well comprises an N + source region and a P + contact region which are connected in parallel; the N + source regions in the two P wells are relatively close to each other, and the P + contact regions are relatively far away from each other; the P + contact region is connected with part of the N + source region through source metal; the surfaces of the N + source region, the P well positioned between the N + source regions and the second N-type epitaxial layer are provided with gate oxide layers, and the upper surfaces of the gate oxide layers are covered with polysilicon gate regions; the periphery of the polycrystalline silicon gate region and the periphery of the gate oxide layer are isolated from the source metal through a dielectric layer; a first N-type through region and a second N-type through region which are communicated with each other are respectively arranged on two sides of the high-voltage VDMOS device region, the first N-type through region is arranged in the first N-type epitaxial layer, and the second N-type through region is arranged in the second N-type epitaxial layer; the two first N-type punch-through regions are respectively connected with two sides of the first N + buried layer; the surfaces of the two second N-type through regions are respectively provided with drain metal; a dielectric layer is arranged between the drain electrode metal and the source electrode metal;
the low-voltage CMOS device area comprises a low-voltage PMOS device area and a low-voltage NMOS device area; specifically, the NMOS device region includes a P-well in the second N-type epitaxial layer, and the P-well has a P + contact region connected to the contact electrode metal, an N + source region connected to the source metal, and an N + drain region connected to the drain metal, respectively; a gate oxide layer is arranged on the surface of the P trap between the N + source electrode region and the N + drain electrode region, and a polycrystalline silicon gate region covers the upper surface of the gate oxide layer; dielectric layers are arranged among the contact electrode metal, the source electrode metal and the drain electrode metal and on the surface of the polycrystalline silicon gate region; the PMOS device region comprises a P + drain region and a P + source region, wherein the P + drain region is connected with drain metal and the P + source region is connected with source metal in the second N-type epitaxial layer; a gate oxide layer is arranged on the surface of the second N-type epitaxial layer between the P + drain region and the P + source region, and a polycrystalline silicon gate region covers the upper surface of the gate oxide layer; a dielectric layer is arranged between the drain metal and the source metal; a second N-type through region connected with the contact electrode metal is arranged in the second N-type epitaxial layer close to one side of the P + source region of the low-voltage NMOS device region, and the second N-type through region penetrates through the second N-type epitaxial layer and is connected with the second N + buried layer; a dielectric layer is arranged between the contact electrode metal and the source electrode metal;
the low-voltage PJFET device region comprises a P well in the second N-type epitaxial layer, and the P well is internally provided with a P + drain region connected with drain electrode metal and a P + source region connected with source electrode metal; the top layer of the P trap between the P + drain region and the P + source region is provided with an N-type grid electrode region connected with grid electrode metal; a dielectric layer is arranged among the source metal, the drain metal and the grid metal; the low-voltage PJFET device region further comprises second N-type through regions respectively arranged on two sides of the P well, and the second N-type through regions on the two sides are respectively connected with two sides of the third N + buried layer; grid metal is respectively arranged on the surfaces of the two second N-type through regions; and a dielectric layer is arranged between the grid metal and other metals.
2. The JCD integrated device of integrated VDMOS of claim 1, further comprising any one or more of a well resistor region, a poly capacitor region, a poly resistor region and a poly diode region integrated in the same P-type substrate;
the trap resistance region is arranged in the second N-type epitaxial layer; the trap resistance region comprises a P trap in the second N-type epitaxial layer, two independent and separated P trap contact regions are arranged in the P trap, the upper parts of the two P trap contact regions are respectively connected with contact electrode metals, and a dielectric layer is arranged between the contact electrode metals;
the poly capacitor region is arranged in the second N-type epitaxial layer; the poly capacitor comprises a P trap in the second N-type epitaxial layer, and two mutually independent and isolated P trap contact regions are arranged in the P trap; the P trap contact area is connected with the corresponding contact electrode metal above the P trap contact area; a gate oxide layer is arranged on the surface of the P well between the two P well contact areas, and polycrystalline silicon connected with contact electrode metal covers the upper surface of the gate oxide layer; a dielectric layer is arranged between the contact electrode metals; the surface of the second N-type epitaxial layer on two sides of the P well is provided with a field oxide layer;
the poly resistor region is arranged above the second N-type epitaxial layer, and a field oxide layer is arranged between the poly resistor region and the second N-type epitaxial layer; the poly resistance region comprises a P-type doped region and contact electrode metal which is arranged on two sides of the P-type doped region and connected with the P-type doped region; a dielectric layer is arranged between the contact electrode metals;
the diode area is arranged above the second N-type epitaxial layer, and a field oxide layer is arranged between the diode area and the second N-type epitaxial layer; the poly diode area comprises an N-type doped cathode area and a P-type doped anode area which are arranged on the surface of the field oxide layer and are connected side by side, cathode metal connected with the N-type doped cathode area and anode metal connected with the P-type doped anode area; a dielectric layer is arranged between the cathode metal and the anode metal.
3. The JCD integrated device of integrated VDMOS of claim 1,
the two sides of the low-voltage CMOS device region are respectively provided with a P + buried layer, and the P + buried layers are arranged between the P-type substrate and the first N-type epitaxial layer; the two sides of the low-voltage CMOS device region further comprise a first P-type isolation region and a second P-type isolation region which are communicated with each other, the first P-type isolation region is arranged in the first N-type epitaxial layer, and the second P-type isolation region is arranged in the second N-type epitaxial layer; the two first P-type isolation regions are respectively connected with the corresponding P + buried layers below the two first P-type isolation regions, and the surfaces of the two second P-type isolation regions are respectively provided with field oxide layers;
the two sides of the low-voltage PJFET device region are respectively provided with a P + buried layer, and the P + buried layers are arranged between the P-type substrate and the first N-type epitaxial layer; the two sides of the low-voltage PJFET device region further comprise a first P-type isolation region and a second P-type isolation region which are mutually communicated, the first P-type isolation region is arranged in the first N-type epitaxial layer, and the second P-type isolation region is arranged in the second N-type epitaxial layer; the two first P-type isolation regions are respectively connected with the corresponding P + buried layers below the two first P-type isolation regions, and the surfaces of the two second P-type isolation regions are respectively provided with field oxide layers;
the two sides of the trap resistance region are respectively provided with a P + buried layer, and the P + buried layers are arranged between the P-type substrate and the first N-type epitaxial layer; the two sides of the trap resistance region also comprise a first P-type isolation region and a second P-type isolation region which are mutually communicated, the first P-type isolation region is arranged in the first N-type epitaxial layer, and the second P-type isolation region is arranged in the second N-type epitaxial layer; the two first P-type isolation regions are respectively connected with the corresponding P + buried layers below the two first P-type isolation regions, and the surfaces of the two second P-type isolation regions are respectively provided with field oxide layers.
4. A preparation method of a JCD integrated device integrated with a VDMOS is characterized by comprising the following steps:
step 1: selecting a P-type semiconductor material as a P-type substrate;
and 2, step: implanting N-type impurities into the P-type substrate by ion implantation and diffusing to form a first N + buried layer arranged below the high-voltage VDMOS device region;
and 3, step 3: implanting ions into the P-type substrate to form a heavily doped P + buried layer below the low-voltage CMOS device region, the low-voltage PJFET device region and the well resistor region;
and 4, step 4: epitaxially forming a first N-type epitaxial layer on a P-type substrate;
and 5: implanting N-type impurities into the first N-type epitaxial layer for diffusion to form first N-type through regions arranged on two sides of the high-voltage VDMOS device region, and respectively connecting the two first N-type through regions with two sides of the first N + buried layer;
step 6: implanting ions into the first N-type epitaxial layer to form a P-type impurity diffusion layer, and forming first P-type isolation regions arranged at two sides of the low-voltage CMOS device region, the low-voltage PJFET device region and the well resistor region; and the first P-type isolation region is connected with the corresponding P + buried layer to form a pair of through isolations;
and 7: forming a field oxide layer on the surface of the first N-type epitaxial layer to realize the subsequent photoetching of the low-voltage CMOS device region and the low-voltage JFET device region, and performing ion implantation and N-type impurity diffusion in the first N-type epitaxial layer to form a second N + buried layer and a third N + buried layer which are respectively arranged below the CMOS device region and the JFET device region;
and 8: epitaxially forming a second N-type epitaxial layer on the first N-type epitaxial layer;
and step 9: implanting ions into the second N-type epitaxial layer to form second N-type through regions arranged on two sides of the high-voltage VDMOS device region, the low-voltage JFET device region and one side of the low-voltage CMOS device region by means of diffusion of N-type impurities, and enabling the two second N-type through regions arranged on two sides of the high-voltage VDMOS device region to be respectively communicated with the first N-type through region; the second N-type punch-through region arranged on one side of the low-voltage CMOS device region is connected with one side of the second N + buried layer, and the second N-type punch-through regions arranged on two sides of the low-voltage JFET device region are respectively connected with two sides of the third N + buried layer;
step 10: implanting ions into the second N-type epitaxial layer to form P-type impurity diffusion to form second P-type isolation regions arranged on two sides of the low-voltage CMOS device region, the low-voltage PJFET device region and the well resistor region; and the second P-type isolation region is communicated with the corresponding first P-type isolation region;
step 11: forming field oxide layers on the surfaces of the device isolation region and the surfaces of the regions where the poly resistor and the poly diode are located so as to realize the subsequent photoetching of the active region;
step 12: implanting N-type impurities into the position of the VDMOS device region on the surface of the second N-type epitaxial layer to form a JFET region;
step 13: forming a high-voltage VDMOS device area, a low-voltage CMOS device area, a well resistor area, a low-voltage PJFET device area and a P well area of a poly capacitor area in the second N type epitaxial layer;
step 14: injecting N-type impurities into the JFET region to form an N-type grid region of a low-voltage PJFET device region;
step 15: forming gate oxide layers of a high-voltage VDMOS device area, a low-voltage CMOS device area and a poly capacitor area;
step 16: forming a high-voltage VDMOS device area, a low-voltage CMOS device area, a poly capacitor area, a poly resistor and a polysilicon gate area of a poly diode;
step 17; implanting N-type impurities into the polycrystalline silicon gate region, and forming an N-type doped polycrystalline silicon gate region, an N + source region and an N + drain region of the high-voltage VDMOS device region through diffusion, an N-type doped polycrystalline silicon gate region, an N + source region and an N + drain region of the low-voltage NMOS device region, an N-type doped polycrystalline silicon gate region of the low-voltage PMOS device region, N-type doped polycrystalline silicon of the poly capacitor region and an N-type doped cathode region of the poly diode;
step 18; implanting P-type impurities into the P well region, and forming a P + contact region of a high-voltage VDMOS device region, a P + source region and a P + drain region of a low-voltage PMOS device region, a P + contact region of a low-voltage NMOS device region, a P + drain region and a P + source region of a low-voltage PJFET device region, a P well contact region of a well resistor region, a P well contact region of a poly capacitor region, a P-type doped region of a poly resistor and a P-type doped anode region of a poly diode through diffusion;
step 19: depositing to form a dielectric layer, refluxing to realize planarization, and etching ohmic holes in the lead wire connection area of the chip;
step 20: activating impurity ions by adopting an annealing process;
step 21: the metallization forms drain metal and source metal of the high-voltage VDMOS device area, contact electrode metal, source metal and drain metal of the low-voltage NMOS device area, drain metal, source metal and contact electrode metal of the low-voltage PMOS device area, gate metal, drain metal and source metal of the low-voltage PJFET device area, contact electrode metal of the well resistor area, contact electrode metal of the poly capacitor area, contact electrode metal of the poly resistor area, and cathode metal and anode metal of the poly diode.
5. The method for preparing a JCD integrated device with integrated VDMOS of claim 4, wherein the process sequence of step 2 and step 3 is not in sequence, the process sequence of step 5 and step 6 is not in sequence, the process sequence of step 9 and step 10 is not in sequence, and the process sequence of step 17 and step 18 is not in sequence.
6. The method for preparing a JCD integrated device of an integrated VDMOS as claimed in claim 4, wherein the N-type punch-through region in step 9 is a drain terminal of the VDMOS device and is also a terminal of the N + buried layer of the low voltage JFET device region.
7. The method for preparing a JCD integrated device with integrated VDMOS of claim 4, wherein the step 11 uses local oxidation to realize a plasma process, thereby effectively reducing the step height on the surface of the chip.
8. The method for preparing a JCD integrated device with integrated VDMOS of claim 4, further comprising a step of forming a high voltage VDMOS device region on the surface of the second N-type epitaxial layer (8) to form an N-type electron accumulation layer as an N-type conduction channel, thereby realizing the manufacture of a high voltage depletion type VDMOS device region.
9. The method as claimed in claim 4, wherein the low voltage CMOS device region is provided with multiple sub guard rings and N + buried layer.
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