CN104037231B - A kind of flash horizontal dual pervasion field effect transistor - Google Patents
A kind of flash horizontal dual pervasion field effect transistor Download PDFInfo
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- CN104037231B CN104037231B CN201410271875.5A CN201410271875A CN104037231B CN 104037231 B CN104037231 B CN 104037231B CN 201410271875 A CN201410271875 A CN 201410271875A CN 104037231 B CN104037231 B CN 104037231B
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- 230000005669 field effect Effects 0.000 title claims abstract description 13
- 230000009977 dual effect Effects 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 238000002955 isolation Methods 0.000 claims abstract description 25
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 18
- 239000001301 oxygen Substances 0.000 claims abstract description 18
- 230000007935 neutral effect Effects 0.000 claims description 5
- 230000015556 catabolic process Effects 0.000 abstract description 10
- 230000006872 improvement Effects 0.000 abstract description 6
- 230000005684 electric field Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000005611 electricity Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 230000002146 bilateral effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001727 in vivo Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a kind of flash horizontal dual pervasion field effect transistor, including: P type substrate, N epitaxial layer, P+ buried regions, P+ is to logical isolation, field oxygen, P top layer, P body district, P body district contact P+, N+ source electrode, grid oxide layer, polygate electrodes, N+ drain electrode.The above of described P type substrate is N epitaxial layer.The side of described N epitaxial layer is provided with P+ buried regions and P+ to logical isolation, in order to isolate different types of device.Further, P body district and P+, to being provided with another P body district between logical isolation, are provided with body district contact P+ in P body district.P top floor it is provided with between P body district and P body district.Avalanche breakdown voltage between source electrode of the present invention and substrate is greatly improved, i.e. isolation performance has had the biggest improvement, meets the application in relatively high working voltage field.
Description
Technical field
The present invention relates to field of semiconductor, particularly relate to a kind of flash horizontal dual pervasion field effect transistor
(LDMOS).
Background technology
Power integrated circuit PIC(Power Integrated Circuit) it is by power device, control circuit, signal
The special integrated circuit that reason circuit etc. is integrated in same chip.PIC, as a branch in integrated circuit, plays always
Vital effect.Compared with discrete device, PIC not only has the biggest advantage in terms of circuit performance, stability and power consumption,
And also have huge potential reducing the aspect such as cost, reduction volume and weight.Just because of these advantages, PIC is by extensively
General apply to computer, communication and many applications such as network, consumer electronics, Industry Control and automotive electronics.And it is horizontal
Bilateral diffusion field-effect tranisistor LDMOS(Lateral double-diffused metal-oxide semiconductor) by
High in having running voltage, technique is simple, it is easy to and low voltage CMOS circuit advantage such as compatible in technique, it is widely used in merit
Rate integrated circuit drives output stage.
In half-bridge driven is applied, it is contemplated that the problem such as chip area and production cost, the flash of output switch circuit
(electron mobility is 2 ~ 3 times of hole mobility, to reach identical generally individually to use N-type channel device with low limit LDMOS
Current driving ability, p-type LDMOS device area needs 2 ~ 3 times for N-type LDMOS device area).At output switch circuit
In duty, and during flash LDMOS conducting, its source voltage is close to supply voltage.Therefore, compare and low limit LDMOS, flash
There is another challenge in LDMOS on structure designs, i.e. needs to isolate the high voltage between source electrode and substrate, to prevent
Puncture and then result in the integrity problem such as noise, breech lock.
Tradition flash LDMOS structure is as it is shown in figure 1, wherein: 101 is P type substrate, and 102 is N-epitaxial layer, and 103 is that P+ buries
Layer, 104 be P+ to logical isolation, 105 is an oxygen, and 106 is P-top layer, 107 ShiP-Ti districts, 108 ShiP-Ti districts contact P+, 109 are
LDMOS N+ source electrode, 110 is grid oxide layer, and 111 is polygate electrodes, and 112 is LDMOS N+ drain electrode.As flash LDMOS
During conducting, P-body district 107 and N+ source electrode 109, close to supply voltage, is in high pressure conditions.P+ is to logical isolation 104 and P-body district
Drift region between 107 is in order to undertake the voltage between source electrode and substrate, it is to avoid source electrode and substrate are in normal working voltage
Lower puncture.But, this structure is applicable to middle low-work voltage.For relatively high working voltage (supply voltage is more than 500V),
Avalanche breakdown can occur between source electrode and substrate in advance.Therefore, for the application of relatively high working voltage, need to improve tradition high
Limit LDMOS structure.
Summary of the invention
Technical problem solved by the invention is to provide a kind of flash horizontal dual pervasion field effect transistor (LDMOS),
Double Resurf(Double RESURF is used between source electrode and substrate) technology, substantially increase source electrode and lining
Isolating power at the end, meets the device application in relatively high working voltage field.
The present invention solves the technology that shown technical problem used puts case and is:
A kind of flash horizontal dual pervasion field effect transistor, including P type substrate, N-epitaxial layer, P+ buried regions, P+ to logical every
From, field oxygen, P-top layer, P-body district, P-body district contact P+, N+ source electrode, grid oxide layer, polygate electrodes, N+ drain electrode.Institute
Stating the above of P type substrate is N-epitaxial layer.The side of described N-epitaxial layer is provided with P+ buried regions and P+ to logical isolation, in order to isolate not
Device with type.The opposite side of described N-epitaxial layer is provided with N+ drain electrode and N+ source electrode, and N+ source electrode is positioned at N+ electric leakage
Between pole and P+ are to logical isolation.Within N+ source electrode is arranged at P-body district, in P-body district, it is additionally provided with body district contact P+.N+ drain electrode
And between N+ source electrode, it is provided with P-top layer.P-top layer is arranged over an oxygen.Overlying regions between P-body district and above-mentioned P-top floor
It is provided with grid oxide layer.Grid oxide layer is arranged over polygate electrodes.P-body district and P+ are to being additionally provided with another P-body between logical isolation
District, is provided with body district contact P+ in P-body district.Being provided with another P-top floor between Liang GeP-Ti district, P-top layer is arranged over an oxygen,
Field oxygen is arranged over polygate electrodes.P-body district and P+ are provided with an oxygen to overlying regions between logical isolation；Further, P-body district
With P+ is to being provided with another P-body district between logical isolation, in P-body district, it is provided with body district contact P+.Set between P-body district and P-body district
There is P-top layer.
Another described P-body district contacts P+ with body district, and it is consistent with substrate that it connects current potential, i.e. connecting to neutral current potential.
In the present invention: when flash LDMOS turns on, device drain-source voltage fall is the least, and source electrode voltage is close to supply voltage.
Owing to substrate, P+ are to logical isolation and P-body district equal connecting to neutral current potential, the vertical PN junctions between N-epitaxial layer and P type substrate is in reverse-biased
State.Meanwhile, the transverse p/n junction between N-epitaxial layer and P-body district is also at reverse-biased.Along with the increasing of source electrode voltage,
The barrier region of two PN junctions constantly extends and interacts, and the result of its effect makes barrier region prolong along surface to edge, P-body district
Stretching, finally make whole drift region exhaust, surface field reduces.Vertical PN junctions reaches critical electric field prior to surface field and manages
That thinks internal punctures.Owing to have employed Double Resurf technology between source electrode and substrate, so between source electrode and substrate
Avalanche breakdown voltage be greatly improved, i.e. isolation performance has had the biggest improvement, meets the application in relatively high working voltage field.
Accompanying drawing explanation
Fig. 1 is tradition flash LDMOS structure schematic diagram.
Fig. 2 is flash horizontal dual pervasion field effect transistor structural representation of the present invention.
Surface electric field distribution when Fig. 3 is the source lining generation avalanche breakdown of flash horizontal dual pervasion field effect transistor of the present invention
Analogous diagram.
Source lining current curve when Fig. 4 is the source lining generation avalanche breakdown of flash horizontal dual pervasion field effect transistor of the present invention
Analogous diagram.
Detailed description of the invention
In order to make the technical problem to be solved, technical scheme and improvement effect clearer, below tie
Close accompanying drawing, the present invention is described in further detail.
Flash horizontal dual pervasion field effect transistor structure of the present invention, as in figure 2 it is shown, include: P type substrate 201, N-extension
Layer 202, P+ buried regions 203, P+ is to logical isolation 204, field oxygen 205, P-top layer 206, P-body district 207 and a 2nd P-body district
213, a P-body district contact P+208 and the 2nd P-body district contact P+214, N+ source electrode 209, grid oxide layer 210, polysilicon gate electricity
Pole 211, N+ drain electrode 212.
The above of described P type substrate 201 is N-epitaxial layer 202.The side of described N-epitaxial layer 202 is provided with P+ buried regions 203
With P+ to logical isolation 204, in order to isolate different types of device.The opposite side of described N-epitaxial layer 202 is provided with N+ drain electrode 212
With N+ source electrode 209, and N+ source electrode 209 is between N+ drain electrode 212 and P+ is to logical isolation 204.N+ source electrode 209 is arranged
Within a P-body district 207, in a P-body district 207, it is additionally provided with a P-body district contact P+208.N+ drain electrode 212 and N+
A P-top layer 206 it is provided with between source electrode 209.Oneth P-top layer 206 is arranged over an oxygen 205.Oneth P-body district 207 He
Between an above-mentioned P-top layer 206, overlying regions is provided with grid oxide layer 210.Grid oxide layer 210 is arranged over polygate electrodes 211.
Oneth P-body district 207 and P+, to being additionally provided with the 2nd P-body district 213 between logical isolation 204, is provided with the 2nd P-in the 2nd P-body district 213
Body district contact P+214.It is provided with the 2nd P-top floor 206, the 2nd P-top layer between 2nd P-body district 213 and a P-body district 207
206 are arranged over an oxygen 205, and field oxygen 205 is arranged over polygate electrodes 211.2nd P-body district 213 and P+ is to logical isolation
Between 204, overlying regions is provided with an oxygen 205.
The 2nd described P-body district 213 contacts P+214 with the 2nd P-body district, and it is consistent with substrate that it connects current potential, i.e. connecting to neutral
Current potential.
The present invention, by arranging the 2nd P-body district 213 and the 2nd P-top floor 206 between source electrode and substrate, defines
Double Resurf structure.When flash LDMOS turns on, source electrode voltage is close to supply voltage.Owing to substrate 201, P+ are to logical
Isolation 204 and the 2nd equal connecting to neutral current potential in P-body district 213, the vertical PN junctions between N-epitaxial layer 202 and P type substrate 201 is in instead
State partially.Meanwhile, the transverse p/n junction between N-epitaxial layer 202 and the 2nd P-body district 213 is also at reverse-biased.Along with source electrode
The increasing of voltage, the barrier region of two PN junctions constantly extends and interacts, and result of its effect makes barrier region along surface to the
One edge, P-body district 207 extends, and finally makes whole drift region exhaust, and surface field reduces.Vertical PN junctions reaches prior to surface field
The most internal puncturing is there is to critical electric field.So, the avalanche breakdown voltage between source electrode and substrate is greatly improved, i.e.
Isolation performance has had the biggest improvement, meets the application in relatively high working voltage field.
In order to the improvement effect of the present invention is expanded on further, by process simulation software Tsuprem4 and device simulation software
Medici carries out source lining OFF state avalanche breakdown voltage characteristic Simulation to an embodiment of novel flash LDMOS structure.Fig. 3 show
Surface electric field distribution figure during generation avalanche breakdown between device source lining, it can be seen that between N-epitaxial layer 202 and P type substrate 201
Peak electric field strength between peak electric field strength a little higher than N-epitaxial layer 202 and the 2nd P-body district 213, illustrates between device source lining
Puncture generation in vivo (i.e. vertical PN junctions between N-epitaxial layer 202 and P type substrate 201).Electricity when Fig. 4 show device breakdown
Current voltage curve, taking source voltage when source current density reaches 1e-9A/um is that source serves as a contrast avalanche breakdown voltage value, reaches
600V.Simulation result, between novel flash LDMOS structure source electrode and substrate, isolating power is good, can meet relatively high workload field
Application.
The foregoing is only presently preferred embodiments of the present invention, that is made within every the spirit and principles in the present invention appoints
What amendment, equivalent and improvement etc., should be included within the scope of the present invention.
Claims (2)
1. a flash horizontal dual pervasion field effect transistor, it is characterised in that it includes: P type substrate (201), N-epitaxial layer
(202), P+ buried regions (203), P+ is to logical isolation (204), field oxygen (205), P-top layer (206), a P-body district (207) and
Two P-body districts (213), a P-body district contact P+(208) contact P+(214 with the 2nd P-body district), N+ source electrode (209), grid oxygen
Layer (210), polygate electrodes (211), N+ drain electrode (212)；The above of described P type substrate (201) is N-epitaxial layer
(202), the side of described N-epitaxial layer (202) is provided with P+ buried regions (203) and P+ to logical isolation (204), in order to isolate inhomogeneity
The device of type, the opposite side of described N-epitaxial layer (202) is provided with N+ drain electrode (212) and N+ source electrode (209), and N+ source electrode
(209) be positioned at N+ drain electrode (212) and P+ to logical isolation (204) between, N+ source electrode (209) is arranged at a P-body district
(207), within, body district contact the oneth P-body district contact P+(208 in a P-body district (207), it is additionally provided with), N+ drain electrode (212)
And between N+ source electrode (209), it being provided with a P-top layer (206), a P-top layer (206) is arranged over an oxygen (205), the
Between one P-body district (207) and an above-mentioned P-top floor (206), overlying regions is provided with grid oxide layer (210), on grid oxide layer (210)
Side is provided with polygate electrodes (211), a P-body district (207) and P+ to being additionally provided with the 2nd P-body district between logical isolation (204)
(213), the 2nd P-body district contact P+(214 in the 2nd P-body district (213), it is provided with), the 2nd P-body district (213) and a P-body district
(207) being provided with the 2nd P-top layer (206) between, the 2nd P-top layer (206) is arranged over an oxygen (205), field oxygen (205) top
It is provided with polygate electrodes (211), the 2nd P-body district (213) and P+ and overlying regions between logical isolation (204) is provided with an oxygen
(205).
Flash horizontal dual pervasion field effect transistor the most according to claim 1, it is characterised in that the 2nd described P-body
District (213) contacts P+(214 with the 2nd P-body district), it is consistent with substrate that it connects current potential, i.e. connecting to neutral current potential.
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| CN201410271875.5A CN104037231B (en) | 2014-06-18 | 2014-06-18 | A kind of flash horizontal dual pervasion field effect transistor |
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| CN201410271875.5A CN104037231B (en) | 2014-06-18 | 2014-06-18 | A kind of flash horizontal dual pervasion field effect transistor |
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| CN104037231A CN104037231A (en) | 2014-09-10 |
| CN104037231B true CN104037231B (en) | 2016-08-31 |
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| CN105405887A (en) * | 2014-09-11 | 2016-03-16 | 北大方正集团有限公司 | Semiconductor device |
| US10998439B2 (en) | 2018-12-13 | 2021-05-04 | Ningbo Semiconductor International Corporation | Gate driver integrated circuit |
| CN111326579B (en) * | 2018-12-13 | 2021-06-25 | 中芯集成电路（宁波）有限公司 | Gate drive integrated circuit |
| CN109671707B (en) * | 2018-12-25 | 2023-03-28 | 电子科技大学 | JCD integrated device integrated with VDMOS and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101728392A (en) * | 2008-10-22 | 2010-06-09 | 台湾积体电路制造股份有限公司 | High voltage device having reduced on-state resistance |
| CN103441145A (en) * | 2013-08-02 | 2013-12-11 | 无锡华润上华半导体有限公司 | Semiconductor device and forming method, starting circuit and switching power source of semiconductor device |
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| US8389366B2 (en) * | 2008-05-30 | 2013-03-05 | Freescale Semiconductor, Inc. | Resurf semiconductor device charge balancing |
| US9484454B2 (en) * | 2008-10-29 | 2016-11-01 | Tower Semiconductor Ltd. | Double-resurf LDMOS with drift and PSURF implants self-aligned to a stacked gate “bump” structure |
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| CN101728392A (en) * | 2008-10-22 | 2010-06-09 | 台湾积体电路制造股份有限公司 | High voltage device having reduced on-state resistance |
| CN103441145A (en) * | 2013-08-02 | 2013-12-11 | 无锡华润上华半导体有限公司 | Semiconductor device and forming method, starting circuit and switching power source of semiconductor device |
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