CN102386227B - Both-way surface field subdued drain electrode isolation double diffused drain metal-oxide -semiconductor field effect transistor (DDDMOS) transistor and method - Google Patents
Both-way surface field subdued drain electrode isolation double diffused drain metal-oxide -semiconductor field effect transistor (DDDMOS) transistor and method Download PDFInfo
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- CN102386227B CN102386227B CN201010270128.1A CN201010270128A CN102386227B CN 102386227 B CN102386227 B CN 102386227B CN 201010270128 A CN201010270128 A CN 201010270128A CN 102386227 B CN102386227 B CN 102386227B
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Abstract
The invention discloses a both-way surface field subdued drain electrode isolation double diffused drain metal-oxide -semiconductor field effect transistor (DDDMOS) transistor and a method. The both-way surface field subdued drain electrode isolation DDDMOS transistor comprises a drain region and body injection regions located at two sides of the drain region. The drain region is provided with a pinch injection layer which is connected with body injection regions on two sides of the drain region. An injection structure connected with the body injection region is added in a drain region of the double diffusion drain electrode metallic oxide field effect transistor. A drain electrode of the drain region can be effectively exhausted when high voltage is applied to the drain region, so that a surface electric field is effectively reduced. Therefore an on-resistance is provided when high voltage is borne. Due to the fact that parasitic capacitance in the drain region is reduced, operating frequency of devices is effectively improved.
Description
Technical field
The present invention relates to a kind of integrated circuit (IC)-components and method, be specifically related to a kind of high pressure and power integration circuit device and method.
Background technology
In power and high voltage integrated circuit manufacture, double-diffused drain electrode power metal-oxide field-effect transistor DDDMOS array (as shown in Figure 1) usually can be adopted to provide large output current.Power DDDMOS structure conventional is at present in the horizontal direction (as shown in Figure 2) due to the expansion of depletion region, drain region cannot be exhausted completely the puncture voltage improving device when drain doping concentration is higher.So high-tensionly cannot provide low conducting resistance bearing simultaneously.Simultaneously because the field intensity on surface is the most concentrated, often occur in device surface so puncture.
Summary of the invention
Technical problem to be solved by this invention is to provide the drain electrode isolation DDDMOS transistor that a kind of Bidirectional surface electric field weakens, and it high-tensionly can provide low conducting resistance bearing simultaneously, effectively improves the operating frequency of device.
In order to solve above technical problem, the invention provides the drain electrode isolation DDDMOS transistor that a kind of Bidirectional surface electric field weakens; Comprise: drain region and the body injection region being positioned at both sides, drain region, have one deck pinch off implanted layer and be connected with the body injection region of both sides, drain region in drain region.
Beneficial effect of the present invention is: add the injecting structure be connected with body injection region in the drain region of double-diffused drain electrode MOS (metal-oxide-semiconductor) memory.When drain region high voltage, the electric field of drain region longitudinal direction effectively by drain depletion, thus can effectively reduce surface field (Reduced SurfaceField).High-tensionly can provide low conducting resistance bearing so simultaneously.Simultaneously because drain region parasitic capacitance reduces, the operating frequency of device is improved.
Present invention also offers the manufacture method of the drain electrode isolation DDDMOS transistor that a kind of Bidirectional surface electric field weakens, comprise the following steps:
Step one, on substrate, form deep trap;
Step 2, active area are formed;
Step 3, pinch off region inject and drain-drift region is injected;
Step 4, body injection region are formed;
Step 5, gate oxide are formed;
Step 6, grid are formed;
Step 7, side wall are formed;
Step 8, source-drain area inject.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
Fig. 1 is traditional DDDMOS section of structure (a) and plane graph (b);
Fig. 2 is depletion region and the Potential Distributing schematic diagram of traditional DDDMOS;
Fig. 3 is DDDMOS section of structure (a) and the plane graph (b) described in the embodiment of the present invention with pinch off Rotating fields;
Fig. 4 is in method described in the embodiment of the present invention, the schematic diagram of deep trap implantation step;
Fig. 5 is in method described in the embodiment of the present invention, the schematic diagram of active area forming step;
Fig. 6 is in method described in the embodiment of the present invention, the schematic diagram of the injection of pinch off layer and high pressure drift region implantation step;
Fig. 7 is in method described in the embodiment of the present invention, and the injection of pinch off layer and injection region, high pressure drift region push away the schematic diagram of trap step;
Fig. 8 is in method described in the embodiment of the present invention, the schematic diagram of body injection region forming step;
Fig. 9 is in method described in the embodiment of the present invention, the schematic diagram of polysilicon gate forming step;
Figure 10 is in method described in the embodiment of the present invention, the schematic diagram of side wall forming step;
Figure 11 is in method described in the embodiment of the present invention, the schematic diagram of source-drain area implantation step;
Figure 12 is the flow chart of method described in the embodiment of the present invention.
Embodiment
The present invention adds the injecting structure be connected with body injection region in the drain region of double-diffused drain electrode MOS (metal-oxide-semiconductor) memory.When drain region high voltage, the electric field of drain region longitudinal direction effectively by drain depletion, thus can effectively reduce surface field (Reduced Surface Field).High-tensionly can provide low conducting resistance bearing so simultaneously.Simultaneously because drain region parasitic capacitance reduces, the operating frequency of device is improved.
As shown in Figure 3, have one deck pinch off implanted layer be connected with the body injection region of both sides, drain region in drain region, the depletion region when draining reverse bias high voltage bottom drain region is fully expanded, and is exhausted by the conductive region in whole drain region.Thus substantially reduce the electric field on surface.Improve the puncture voltage of device.
As shown in figure 12, the technological process realizing this structure is specific as follows:
(1), as shown in Figure 4, substrate forms deep trap.
(2), as shown in Figure 5, active area is formed (can adopt localized oxidation of silicon isolation or trench isolations etc.).
(3), as shown in Figure 6, pinch off region injects and drain-drift region injection.
(4), as shown in Figure 7, pinch off region and drift region push away trap (also can omit if the Impurity Distribution injected has met device needs).
(5), as shown in Figure 8, body injection region is formed.
(6), gate oxide is formed.
(7), as shown in Figure 9, grid is formed.
(8), as shown in Figure 10, side wall is formed.
(9), as shown in figure 11, source-drain area injects.
The present invention utilizes a PN junction bottom drain region, and drain region exhausts by depletion region completely that produce a vertical direction when device is back-biased.The puncture voltage of device can be increased like this while increasing drain region doping content.Device realizes the puncture voltage higher than traditional structure and conducting resistance.
The present invention is not limited to execution mode discussed above.Above the description of embodiment is intended to describe and the technical scheme that the present invention relates to being described.Based on the present invention enlightenment apparent conversion or substitute also should be considered to fall into protection scope of the present invention.Above embodiment is used for disclosing best implementation method of the present invention, can apply numerous embodiments of the present invention and multiple alternative to reach object of the present invention to make those of ordinary skill in the art.
Claims (4)
1. the drain electrode isolation DDDMOS transistor that weakens of a Bidirectional surface electric field, drain electrode isolation DDDMOS transistor to be formed in deep trap injection region and to be surrounded by described deep trap injection region, comprise: drain region and the body injection region being positioned at both sides, drain region, described drain region comprises high pressure drift injection region and is formed at the source and drain injection region on described high pressure drift surface, injection region, described body injection region and described high pressure drift injection region lateral contact, the source and drain injection region as source region is formed in described body injection region, and draw injection region for the body of drawing described body injection region, gate dielectric layer and polysilicon gate is formed successively on surface, described body injection region, described gate dielectric layer and described polysilicon gate also extend a segment distance to described high pressure drift injection region, the surface of described body injection region that covers by described polysilicon gate for the formation of raceway groove, a segment distance of being separated by is isolated between the source and drain injection region in described drain region and described polysilicon gate, described drain region isolates DDDMOS transistor by two adjacent described drain electrodes and shares, two described drain electrode isolation DDDMOS transistors are formed at same by adopting field to be oxidized in the active area isolating and formed, it is characterized in that, there is in drain region one deck pinch off implanted layer be connected with the body injection region of both sides, drain region, described pinch off implanted layer is positioned at the bottom of described high pressure drift injection region, when described drain region connects reverse bias voltage, described pinch off implanted layer is used for carrying out longitudinal direction from bottom to described high pressure drift injection region and exhausts, having lateral depletion is carried out to described high pressure drift injection region from the side in described body injection region, the Bidirectional surface electric field realizing described drain region weakens.
2. the manufacture method of DDDMOS transistor is isolated in the drain electrode that Bidirectional surface electric field as claimed in claim 1 weakens, and it is characterized in that, comprises the following steps:
Step one, on substrate, form deep trap;
Step 2, active area are formed;
Step 3, pinch off region inject and drain-drift region is injected;
Step 4, body injection region are formed;
Step 5, gate oxide are formed;
Step 6, grid are formed;
Step 7, side wall are formed;
Step 8, source-drain area inject.
3. the manufacture method of DDDMOS transistor is isolated in the drain electrode that Bidirectional surface electric field as claimed in claim 2 weakens, and it is characterized in that, in described step 2, adopts localized oxidation of silicon isolation or trench isolations to be formed with source region.
4. the manufacture method of drain electrode isolation DDDMOS transistor that weakens of Bidirectional surface electric field as claimed in claim 3, is characterized in that, increases the step that pinch off region and drift region push away trap between step 3 and step 4.
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| CN201010270128.1A CN102386227B (en) | 2010-08-31 | 2010-08-31 | Both-way surface field subdued drain electrode isolation double diffused drain metal-oxide -semiconductor field effect transistor (DDDMOS) transistor and method |
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| CN201010270128.1A CN102386227B (en) | 2010-08-31 | 2010-08-31 | Both-way surface field subdued drain electrode isolation double diffused drain metal-oxide -semiconductor field effect transistor (DDDMOS) transistor and method |
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| CN102386227A CN102386227A (en) | 2012-03-21 |
| CN102386227B true CN102386227B (en) | 2015-04-08 |
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| US9799766B2 (en) * | 2013-02-20 | 2017-10-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | High voltage transistor structure and method |
| CN104538446B (en) * | 2014-12-23 | 2017-09-22 | 电子科技大学 | A kind of bi-directional MOS type device and its manufacture method |
| CN105993076B (en) * | 2014-12-23 | 2019-03-01 | 电子科技大学 | A kind of bi-directional MOS type device and its manufacturing method |
| CN114613849B (en) * | 2022-05-10 | 2022-08-12 | 深圳市威兆半导体股份有限公司 | Silicon carbide MOS device for improving short circuit characteristic |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5382535A (en) * | 1991-10-15 | 1995-01-17 | Texas Instruments Incorporated | Method of fabricating performance lateral double-diffused MOS transistor |
| CN101740385A (en) * | 2008-11-24 | 2010-06-16 | 上海华虹Nec电子有限公司 | Method for forming channel in LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6989567B2 (en) * | 2003-10-03 | 2006-01-24 | Infineon Technologies North America Corp. | LDMOS transistor |
| KR100628250B1 (en) * | 2005-09-28 | 2006-09-27 | 동부일렉트로닉스 주식회사 | Semiconductor device for using power and method for fabricating the same |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5382535A (en) * | 1991-10-15 | 1995-01-17 | Texas Instruments Incorporated | Method of fabricating performance lateral double-diffused MOS transistor |
| CN101740385A (en) * | 2008-11-24 | 2010-06-16 | 上海华虹Nec电子有限公司 | Method for forming channel in LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor |
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