CN101740385A

CN101740385A - Method for forming channel in LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor

Info

Publication number: CN101740385A
Application number: CN200810043984A
Authority: CN
Inventors: 陈华伦; 罗啸; 熊涛; 陈瑜; 陈雄斌
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2008-11-24
Filing date: 2008-11-24
Publication date: 2010-06-16

Abstract

The invention relates to a method for forming a channel in an LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor. After deep well injection is conducted on a silicon substrate, the method comprises the following steps of: (1) growing a thick oxidation layer used as a blocking layer on a silicon surface; (2) defining an active area by using a photoetching process, etching the oxidation layer to the silicon surface by taking a photoresist pattern formed by photoetching as a mask, and then removing photoresist; and (3) oxidizing to cover the exposed silicon surface with a thin layer of silicon oxide, and then defining a base region by using the phototeching process, conducting ion injection to form the base region by taking the formed photoresist pattern as a mask, wherein the base region is the channel of the LDMOS transistor.

Description

Raceway groove formation method in the ldmos transistor

Technical field

The present invention relates to a kind of preparation method of ldmos transistor, particularly the formation method of raceway groove in the ldmos transistor.

Background technology

Lateral double diffusion metal oxide semiconductor field-effect transistor (lateraldouble-diffused MOSFET is called for short LDMOS) is a kind of of MOS transistor.The method of raceway groove generally has two kinds in present 0.35um technology and the above prepared ldmos transistor.A kind of is earlier the ion injection of channel region to be carried out before doing polysilicon gate, and as shown in Figures 1 to 4, with the transistorized example that is prepared as of LDNMOS, idiographic flow is as follows: form in the dark N trap on the P substrate earlier; Locos district that preparation then is used to isolate and the growth of the silicon face between isolated area oxide layer; Then utilize photoetching process to define the position that the base injects, carry out the P foreign ion and inject formation P base (this P base is the channel region of ldmos transistor); Then deposit utilizes the grid oxygen under photoetching process and etching technics formation grid and the grid as the silicon dioxide of grid oxygen and the polysilicon that is used as grid successively; Then carry out follow-up common process, see among Fig. 4, the side wall of grid oxygen, polysilicon gate and gate side, N+ district in the left side is that source region, P+ district are the tagma, and N+ district in the right is the drain region, forms complete LDNMOS transistor.Another kind of (seeing Fig. 5 to Fig. 8) is after polysilicon gate forms, and the ion of making raceway groove of wide-angle injects, and then with certain heat-treat condition, allows the injection region ions diffusion to channel region.These two kinds of methods all have corresponding shortcoming, and first kind channel region is by the crossover region decision of two layer patterns, and the stability on whole silicon wafer can be relatively poor relatively; Second kind of preparation method then can introduce new heat-treat condition, and the length of channel region is limited to.

Summary of the invention

The technical problem to be solved in the present invention provides the raceway groove formation method in a kind of ldmos transistor, and the size of channel region is only determined by polysilicon layer in this method.

For solving the problems of the technologies described above, the raceway groove formation method in the ldmos transistor of the present invention is characterized in that: carry out comprising the steps: after the deep trap injection on silicon substrate

1) grows an oxide layer as injecting the barrier layer at silicon face;

2) utilize photoetching process to define active area, and be mask with the photoresist pattern that photoetching forms, etching not by oxide layer that photoresist covered to silicon face, photoresist is removed in the back;

3) oxidation makes exposed silicon face growth one deck silica as injecting protective layer; then utilizing photoetching process to define the base, is mask with formed photoresist pattern, carries out ion and injects; form the base, described base is the raceway groove of described ldmos transistor.

Raceway groove formation method in the ldmos transistor of the present invention, utilize the thick silicon oxide in the active layer to do self aligned channel region ion injection as the barrier layer, prepare grid polycrystalline silicon then, the size of channel region is just only decided by polysilicon layer like this, overcome existing preparation method's shortcoming, and because of locos isolation structure of no use, so the beak effect that does not exist this locos isolation structure to bring, can reduction of device size.

Description of drawings

The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:

Fig. 1 to Fig. 4 is a raceway groove formation method in existing a kind of ldmos transistor;

Fig. 5 to Fig. 8 is a raceway groove formation method in the existing another kind of ldmos transistor;

Fig. 9 is that raceway groove forms method flow diagram in the ldmos transistor of the present invention;

Figure 10 to Figure 14 is the structural representation of one embodiment of the invention;

Figure 15 is a barrier layer structure schematic diagram in the another embodiment of the present invention;

Figure 16 to Figure 17 is the structural representation of side wall preparation in oxide layer barrier layer in the another embodiment of the present invention.

Embodiment

Raceway groove formation method in the ldmos transistor of the present invention is an example with preparation LDNMOS on the P substrate, and idiographic flow is a (see figure 9):

1) on the P silicon substrate, carries out after the dark N trap injection, make to inject the barrier layer (see figure 10) in surface of silicon growth or deposit one oxide layer, wherein the thickness on this oxide layer barrier layer is determined by the base injection degree of depth, in general, it is dark more that the base injects the degree of depth, require barrier layer thickness big more, can be usually between the 4000-10000 dust;

2) utilize photoetching process (comprise the photoresist spin coating, carry out photoetching and development) to define active area with photoetching grinding version, and the photoresist pattern that forms with photoetching is a mask, the oxide layer that etching is not covered by photoresist is to silicon face, make the silicon face of active area expose out (seeing Figure 11), photoresist is removed in the back;

3) oxidation makes exposed silicon face growth silicon monoxide as injecting protective layer; utilize photoetching process to define the position that the base injects once more; be mask then with formed photoresist pattern; carry out the p type impurity ion and inject formation P base, this P base is the channel region (seeing Figure 12) of ldmos transistor.Carry out follow-up common process afterwards, as removing photoresist and injecting protective layer, grid oxygen and grid form (seeing Figure 13), the formation in source region, drain region and tagma (seeing Figure 14) etc.

In the raceway groove formation method of the present invention, should be noted that some:

1) in above-mentioned steps one, oxide layer wherein might not be to want thermal oxidation or all thermal oxidations, might not be the growth oxide layer in other words, can use deposited oxide layer or other dielectric layers.

2) if the injection degree of depth of the P base of actual needs is very dark in the device preparation, thus need the oxide layer barrier layer very thick, and at this time single thick oxide layer can cause the back processing procedure that the evenness of non-constant is arranged because too high thickness is arranged.So can constitute this barrier layer with sandwich structure, for example the bottom is lower floor's oxide layer of suitable thickness, and the centre is a nitride, is upper strata oxide layer (seeing Figure 15) above.If adopt sandwich structure to do the barrier layer, after the ion of finishing the P base injects, upper strata oxide layer and middle nitride can be removed so.

3) in the photoetching of P base, can see that drain terminal may have the problem that photoresist is filled.In fact, in this technology, because the problem of locos beak is arranged, so the size of the active area of drain terminal is about 1um, therefore, even need barrier layer thickness more than 2um, photoresist can not filled yet.Even,, can after the P base layer is finished, add a new photoetching etch layer again and make for very undersized structure for extreme case.

4) cause the relative locos technology in oxide layer corner more steep for active area etching meeting, and cause the edge distribution and the relatively more difficult problem of etching of polysilicon.The problems referred to above can solve by the following method: the one, can select appropriate oxidated layer thickness according to voltage, and avoid very thick oxide layer; The 2nd, can regulate the etching condition of active area, make the etching figure of oxide layer that the bigger elevation angle be arranged; The 3rd, after finishing the injection of P base, can handle oxide layer with wet etching, since the isotropism of wet etching, the comparison slyness that the drift angle of oxide layer can be handled; The 4th, after finishing the injection of P base, deposit one deck dielectric on silicon chip, another silica (seeing Figure 16) as the 500-2000 dust, then another layer silica on the whole silicon wafer carried out dry etching, consequently produce the side wall (seeing Figure 17) of a 0.2-1um, can effectively strengthen slick and sly effect like this at the edge on thick silicon oxide barrier layer; The 5th, increase the thickness of polysilicon layer, when polysilicon is etched, increase many mistakes then and be etched with and thoroughly go out polysilicon remnants.

5) guarantee that for need between P base and injection barrier layer, needing certain distance sometimes certain safe distance comes to eliminate the influence of relatively dense P base to the diffusion region of relatively light dark N trap, can after finishing thick barrier layer, do the side wall of a thick grid oxygen so before the injection of P base, as use nitride, finish and again this side wall is removed after the P base injects.

Claims

1. the raceway groove formation method in the ldmos transistor is characterized in that: carry out comprising the steps: after deep trap injects on silicon substrate

1) grows an oxide layer as injecting the barrier layer at silicon face;

2) utilize photoetching process to define active area, and be mask with the photoresist pattern that photoetching forms, the oxide layer that etching is not covered by photoresist is to silicon face, and photoresist is removed in the back;

3) oxidation makes exposed silicon face growth silicon monoxide as injecting protective layer, then utilizes photoetching process to define the base, is mask with formed photoresist pattern, carries out ion and injects the formation base, and described base is the raceway groove of described ldmos transistor.

2. according to the described raceway groove of claim 1 formation method, it is characterized in that: the oxidated layer thickness in the described step 1 is between the 4000-10000 dust.

3. according to the described raceway groove of claim 1 formation method, it is characterized in that: the oxide layer in the described step 1 adopts the method for thermal oxidation or deposit to be prepared from.

4. according to each described raceway groove formation method among the claim 1-3, it is characterized in that: also comprise the step that makes its drift angle slynessization with the described oxide layer of wet treatment after the described step 3.

5. according to each described raceway groove formation method among the claim 1-3, it is characterized in that: also be included in after the described step 3 and follow another oxide layer of deposit on the silicon substrate, described another oxide layer of etching makes the step place that forms after the step 2 etching form the step of side wall afterwards.

6. according to the described raceway groove of claim 1 formation method, it is characterized in that: the sandwich structure that the oxide layer in the described step 1 is made up of lower floor's oxide layer, middle nitride and upper strata oxide layer substitutes, and also comprises the step with nitride in the middle of described and the removal of described upper strata oxide layer after the described step 3.