CN107622939A - A kind of manufacture method of semiconductor devices - Google Patents
A kind of manufacture method of semiconductor devices Download PDFInfo
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- CN107622939A CN107622939A CN201610559436.3A CN201610559436A CN107622939A CN 107622939 A CN107622939 A CN 107622939A CN 201610559436 A CN201610559436 A CN 201610559436A CN 107622939 A CN107622939 A CN 107622939A
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- 238000000034 method Methods 0.000 title claims abstract description 67
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000009792 diffusion process Methods 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000002019 doping agent Substances 0.000 claims abstract description 17
- 210000000746 body region Anatomy 0.000 claims abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 23
- 238000001259 photo etching Methods 0.000 claims description 21
- 238000000407 epitaxy Methods 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 238000007689 inspection Methods 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 description 9
- 239000000463 material Substances 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000002347 injection Methods 0.000 description 7
- 239000007924 injection Substances 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000003153 chemical reaction reagent Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000026267 regulation of growth Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
Abstract
The invention discloses a kind of manufacture method of semiconductor devices.With it, extension number of layers can be reduced, so as to simplification of flowsheet, cost, raising craft precision are reduced.This method includes：First epitaxial layer of the first conduction type is provided on substrate；Mask layer is formed on first epitaxial layer, to limit the region where the cylindricality diffusion region of the second conduction type；Using the second conductivity type dopant ion of million electro-volt superfine energy, ion implanting is carried out to the first epitaxial layer, to form the second conductivity type dopant body zone；Remove the mask layer；Carry out high temperature and push away trap, be diffused the second conduction type dopant in the second conduction type body region, obtain the cylindricality diffusion region of the second conduction type.
Description
Technical field
The present invention relates to field of semiconductor manufacture, the more particularly, to semiconductor devices with super-junction structure
Manufacture method.
Background technology
For the power device of conventional single conduction type, higher breakdown voltage is obtained, it is just necessary
Thicker epitaxial layer drift region and relatively low doping concentration are formed, thus conducting resistance can be with breakdown voltage
Increase and increased dramatically.However, conducting resistance is general higher and can not further reduce.
Super-junction structure is increasingly paid attention to as a kind of advanced drift region structure by industrial quarters.Super-junction structure
Drift region use alternate PN junction structure, be the advantages of this structure, in identical resistance to pressure, superjunction
The doping concentration of structure drift region can improve an order of magnitude, therefore conducting resistance can reduce 5-10 times.
Fig. 1 shows the schematic diagram of the semiconductor devices with super-junction structure according to prior art.Such as Fig. 1
Shown, super-junction structure includes alternate P posts diffusion region 110 and N-type epitaxial region 120.
Super-junction structure is mainly realized by two kinds of processes at present：1) multiple extension and multiple ion implanting work
Skill；2) deep trouth epitaxy technique, the difficult point of deep trouth epitaxy technique manufacture are：Form the P with high-aspect-ratio
Post area and N posts area.
For the superjunction devices formed by multiple extension and multiple ion implantation technology, prior art is used
Epitaxy layer thickness typically in the micro- scopes of 6-8, in order to enable the device to reach 600V to 900V and more than
Voltage endurance, prior art will generally form plurality of layers (6 layers even more than 6 layers) epitaxial layer, and this is
Because the ion energy of used ion implantation technology is in a kiloelectron-volt superfine during superjunction devices manufactures
In the range of, therefore its ion implanting depth is limited, which has limited the thickness of each layer of epitaxial layer.It is pre- to obtain
The P posts diffusion region height of phase, it has to carry out multiple epitaxial growth.
Although prior art can realize superjunction function, due to the requirement of high withstand voltage, using common more
Secondary extension and multiple ion implanting, the extension number of plies is more, complex technical process, and cost is higher, it is easier to by
To the influence of photoetching alignment precision repeatedly.
Therefore, it is necessary to which a kind of manufacture method for being used for the semiconductor devices with super-junction structure, can solve the problem that existing
There is subproblem existing for technology.
The content of the invention
It is an object of the invention to provide a kind of manufacture method of semiconductor devices, with it, can reduce outer
Prolong number of layers, so as to simplification of flowsheet, reduce cost, raising precision of manufacturing process.
According to an aspect of the present invention, there is provided a kind of manufacture method of semiconductor devices, including：A) exist
First epitaxial layer of the first conduction type is provided on substrate；B) mask layer is formed on first epitaxial layer,
To limit the region where the cylindricality diffusion region of the second conduction type；C) using million electro-volt superfine energy
Second conductivity type dopant ion, ion implanting is carried out to the first epitaxial layer, to form the second conduction type
Dopant body zone；D) mask layer is removed；E) carry out high temperature and push away trap, adulterate the second conduction type
The second conduction type dopant is diffused in body zone, obtains the cylindricality diffusion region of the second conduction type.
According to an aspect of the present invention, in preceding method, by photoetching process on first epitaxial layer
Form the photoresist layer with specific pattern includes as the mask layer, the photoetching process：Described
The photoresist layer is formed on one epitaxial layer, the thickness of the photoresist layer is 5 microns to 6 microns；Pass through
Specific part in alignment, exposure, developing process removal photoresist layer is with the epitaxial layer of expose portion first.
According to an aspect of the present invention, in preceding method, the thickness that first outer layer prolongs is more than or equal to
10 microns
According to an aspect of the present invention, preceding method, which is additionally included in, before high temperature pushes away trap, be repeated several times
Step a) to step d), to reach predetermined total epitaxy layer thickness.
According to an aspect of the present invention, preceding method is additionally included in before repeat step a), removes upper one
The surface oxide layer of layer epitaxial layer.
According to an aspect of the present invention, in preceding method, the high temperature pushes away trap and causes shape in each epitaxial layer
Into the cylindricality diffusion region of the second conduction type form connection in vertical direction.
According to an aspect of the present invention, in preceding method, first conduction type is N-type, described
Second conduction type is p-type.
According to an aspect of the present invention, in preceding method, the second conductivity type dopant ion is boron
Ion.
According to an aspect of the present invention, in preceding method, after the mask layer is removed, surface is carried out
Check, to ensure that it is clean that mask layer removes.
According to another aspect of the present invention, there is provided a kind of semiconductor devices, including pass through claim 1
To the structure of the method manufacture described in any one of 9..
Compared with prior art, make for 600V to 900V and the above different pressure voltages, every layer of extension
With more than 10 microns thickness, it is possible to reduce the growth course of 1-2 layer extensions and corresponding photoetching injection system
Step is made, so as to reduce the 1-2 technique error chance from photoetching to ion implanting, improves technique
Controllability, improve device reliability.Simultaneously as reduce the manufacturing steps such as 1-2 layer epitaxially growns,
Corresponding manufacturing cost can reduce 8-12%, and lift production capacity.
Brief description of the drawings
For the above and other advantages and features of each embodiment that the present invention is furture elucidated, by refer to the attached drawing
The more specifically description of various embodiments of the present invention is presented.It is appreciated that these accompanying drawings only describe the present invention
Exemplary embodiments, therefore be not to be regarded as being restriction on its scope.In the accompanying drawings, in order to cheer and bright,
It is exaggerated layer and the thickness in region.Identical or corresponding part will be represented with same or similar mark.
Fig. 1 shows the schematic diagram 100 of the semiconductor devices with super-junction structure according to prior art.
The section that Fig. 2A to Fig. 2 G shows to form the process of super-junction structure according to an embodiment of the invention shows
It is intended to.
Fig. 3 shows to form the schematic diagram of the semiconductor devices with super-junction structure according to an embodiment of the invention
300。
Fig. 4 shows the flow chart of formation super-junction structure according to an embodiment of the invention.
Embodiment
In the following description, with reference to each embodiment, present invention is described.However, the technology of this area
Personnel will be recognized that can in the case of neither one or multiple specific details or with it is other replacement and/or it is attached
Adding method, material or component implement each embodiment together.In other situations, it is not shown or is not described in detail
Known structure, material or operation are in order to avoid make the aspects of various embodiments of the present invention obscure.Similarly, it is
The purpose explained, elaborates specific quantity, material and configuration, to provide to embodiments of the invention
Comprehensive understanding.However, the present invention can be implemented in the case of no specific detail.Further, it should be understood that accompanying drawing
In each embodiment for showing be illustrative expression and be not drawn necessarily to scale.
In the technology of super-junction structure is manufactured by multiple extension and multiple ion implantation technology, by first
The cylindricality diffusion region of the second deep conduction type is formed in conductive type epitaxial layer, and obtains suitable diffusion
Concentration is to reach the key that superjunction devices is capable of stable operation.
The invention discloses in multiple extension and multiple ion implantation technology, injected and realized using energetic ion
Less epitaxial layer, obtain the manufacture method of high withstand voltage structure.
Forming the technological process of super-junction structure includes：The repeated multiple times growth regulation one in the first conductivity type substrate
Conductive type epitaxial layer, the second conduction type is customized out in Yanzhong outside each conduction type of layer first by photoetching
Cylindricality diffusion region, and ion implanting is carried out to the cylindricality diffusion region of the second conduction type, then using high temperature
The cylindricality diffusion region that trap connects the second conduction type is pushed away, to reach suitable diffusion concentration.
The present invention employs the superfine note of high energy million electro-volt when forming the cylindricality diffusion region of the second conduction type
The technique entered, every layer of epitaxial thickness, can thereby using the epitaxial structure of the less number of plies more than 10 microns
To reach the resistance to pressure request of 600 to 900V and the above, it can reach and be easy to produce, reduce the purpose of cost.
The section that Fig. 2A to Fig. 2 F shows to form the process of super-junction structure according to an embodiment of the invention shows
It is intended to.
First, as shown in Figure 2 A, the first epitaxial layer 202 of the first conduction type is provided on the substrate 201.
Substrate 201 can be any material that can be used for producing the semiconductor devices.In certain embodiments, substrate 201
Can be single crystal silicon material, doped single crystal silicon material, on polycrystalline or sandwich construction substrate or insulator
Semiconductor substrate.In certain embodiments, substrate 201 can not include silicon, alternatively include such as Ge,
Backing materials different GaAs or InP etc..Substrate 201 can include one or more materials, device or
Layer, or can be the single material without multilayer.
In an exemplary embodiment of the present invention, substrate 201 can be N-type silicon substrate, and first leads
First epitaxial layer 202 of electric type is the predetermined thickness formed by epitaxial growth in N-type silicon substrate 201
Prolong with the N-type outer layer of concentration.For example, the thickness that the N-type outer layer formed in N-type silicon substrate 201 prolongs
10 microns can be more than or equal to.
As shown in Figure 2 B, before subsequent treatment is carried out to the first epitaxial layer 202, due to by the first extension
Layer 202 is externally exposed air, and may be in the surface oxide layer 203 of the surface of the first epitaxial layer 202 formation.
As shown in Figure 2 C, mask layer 204 is formed on the first epitaxial layer 202, to limit the second conductive-type
Region where the cylindricality diffusion region of type.
In an exemplary embodiment of the present invention, it can be formed by photoetching process on the first epitaxial layer 202
Photoresist layer with specific pattern is as mask layer 204.The photoetching process specifically includes：First,
Photoresist layer is formed on one epitaxial layer 202 and surface oxide layer 203, it is micro- that the thickness of the photoresist layer reaches 5
Rice is to 6 microns, to ensure the precision of the cylindricality diffusion region size of the second conduction type that follow-up photoetching defines；
By be aligned exposure, development etc. processing remove photoresist layer in specific part with formed open area 205,
206, so as to expose the specific part of the first epitaxial layer 202.
However, it will be appreciated by those skilled in the art that：Mask layer 204 is not limited to photoresist layer, as long as
The material that part is not implanted that is blocked can be protected to can be used as mask layer in subsequent ion injection process
204.For example, mask layer 204 can be the metal hard mask layer formed by metal material.
As shown in Figure 2 D, by the second conductivity type dopant ion implanting to the first epitaxial layer 202, with
Form the second conductivity type dopant body zone 207,208.In an embodiment of the present invention, using million electronics
Volt level energy accelerates to injection ion, so that the second conduction type body zone can reach predetermined dense
Degree and desired depth.
In an exemplary embodiment of the invention, the first conduction type is N-type, and the second conduction type is p-type,
The injection of the second conductivity type dopant, used work are carried out using the boron ion of million electro-volt superfine energy
Skill gas can be BF3And/or B2H6.Because in ion implantation process, the energy of boron ion is in million electricity
Sub- volt level, which increase the penetration depth of ion so that the thickness of individual layer epitaxial layer is increased.At this
In the embodiment of invention, the thickness of individual layer epitaxial layer can be more than or equal to 10 microns.
As shown in Figure 2 E, mask layer is removed, and carries out surface inspection, to ensure that mask layer is removed clean.
In the embodiment that mask layer is photoresist layer, chemical reagent wet method can be used to remove photoresist, Huo Zheye
Can be with using plasma dry technique stripping photoresist.This dry technique can not only peel off a large amount of photoetching
Glue, and some remaining organic matters can also be removed.
As shown in Figure 2 F, surface oxide layer 203 is removed, to ensure that surface is adapted to the normal of next layer of extension
Growth.Surface oxide layer can be removed by chemical reagent wet method, or can also be gone using dry etching technology
Except surface oxide layer.
Then, the process shown in Fig. 2A to Fig. 2 F can be repeated several times, until epitaxial thickness needed for formation.
In an embodiment of the present invention, using a million electro-volt ion implanting for superfine energy, subsequent high temperature is facilitated to push away trap
The abundant connection of the cylindricality diffusion region of second conduction type, superjunction function is formed, so as to allow every layer of epitaxial layer
Thickness more than 10 microns.Compared with prior art, the cylindricality of the second conduction type of same size is obtained
The extension number of plies needed for diffusion region at least reduces 1-2 layers, reduces photoetching alignment number, reduces technique and go out
Wrong probability.
As shown in Figure 2 G, it is outer comprising the second conduction type body region 207,208 by what is formed
Prolong layer progress high temperature and push away trap, expanded the second conduction type dopant in the second conduction type body region
Dissipate, so that the cylindricality diffusion region of the conduction type of each layer second forms connection in vertical direction, obtain the
The cylindricality diffusion region of two conduction types.
Fig. 3 shows to form the schematic diagram of the semiconductor devices with super-junction structure according to an embodiment of the invention
300.From figure 3, it can be seen that obtain outer needed for the cylindricality diffusion region of the second conduction type of same size
Prolong the number of plies to substantially reduce.
Fig. 4 shows the flow chart of the method for formation super-junction structure according to an embodiment of the invention.
In step 401, the first epitaxial layer of the first conduction type is provided on substrate.At one of the present invention
In example embodiment, substrate can be N-type silicon substrate, and the first epitaxial layer of the first conduction type is to pass through
The predetermined thickness and the N-type outer layer of concentration that epitaxial growth is formed in N-type silicon substrate prolong.For example, in N
The thickness that the N-type outer layer formed on type silicon substrate 201 prolongs can be more than or equal to 10 microns.
In step 402, mask layer is formed on the first epitaxial layer, is expanded with limiting the cylindricality of the second conduction type
Dissipate the region where area., can be by photoetching process in the first extension in an exemplary embodiment of the present invention
The photoresist layer with specific pattern is formed on layer as mask layer.The photoetching process specifically includes：First,
Photoresist layer is formed on the first epitaxial layer, and the thickness of the photoresist layer reaches 5 microns to 6 microns, to protect
Demonstrate,prove the precision of the cylindricality diffusion region size for the second conduction type that follow-up photoetching defines；Exposed by alignment,
The processing such as development remove the specific part in photoresist layer to form open area 205,206, so as to exposure the
The specific part of one epitaxial layer.
In step 403, by the second conductivity type dopant ion implanting to the first epitaxial layer, to form
Two conduction type body regions.In an embodiment of the present invention, using million electro-volt superfine energy to injection
Ion is accelerated, so that the second conduction type body zone can reach predetermined concentration and desired depth.
In step 404, mask layer is removed, and carries out surface inspection, to ensure that mask layer is removed clean.
In the embodiment that mask layer is photoresist layer, chemical reagent wet method can be used to remove photoresist, Huo Zheye
Can be with using plasma dry technique stripping photoresist.This dry technique can not only peel off a large amount of photoetching
Glue, and some remaining organic matters can also be removed.
In step 405, surface oxide layer is removed, to ensure that surface is adapted to the normal growth of next layer of extension.
In step 406, judge whether the gross thickness of epitaxial layer reaches predetermined value, if the gross thickness of epitaxial layer
Less than predetermined value, then return to step 401；If the gross thickness of epitaxial layer reaches predetermined value, into step
407。
In step 407, high temperature is carried out to each epitaxial layer and pushes away trap, make in the second conduction type body region the
Two conduction type dopants are diffused, so that the cylindricality diffusion region of the conduction type of each layer second is vertical
Side is upwardly formed connection, obtains the cylindricality diffusion region of the second conduction type.
In above process, noted for the cylindricality diffusion region of the second conduction type using high energy million electro-volt is superfine
Enter, to realize the abundant connection of the cylindricality diffusion region of the second conduction type, form superjunction function, every layer of extension
Using more than 10 microns of thickness so that the extension number of plies reduces 1-2 layers, reduce photoetching alignment number,
Reduce technique error probability.The pressure-resistant requirement higher than 600V to 900V of device can equally be reached.
In summary, compared with prior art, for 600V to 900V and the above different pressure voltages,
Every layer of extension uses more than 10 microns of thickness, it is possible to reduce the growth course of 1-2 layer extensions and accordingly
Photoetching injection process, so as to reduce the 1-2 technique error chance from photoetching to ion implanting, improve
The controllability of technique.Further, since reduce growth course and the corresponding photoetching injection of 1-2 layer extensions
Process, corresponding overall cost cost can reduce 8-12%.
The foregoing description of embodiments of the invention is had been presented for for the purpose of illustration and description.It is not intended to poor
Lift or limit the invention to disclosed precise forms.This specification and appended claims include it is such as left,
The right side, top, bottom ... on ... under, top, bottom, the term such as first, second, this
The purposes of description are only used for a bit and should not be construed as limiting.For example, indicate that the term of relative upright position refers to
Be that the device-side (or active surface) of substrate or integrated circuit is the situation in substrate " top " face；Substrate
Any direction can be practically at so that " top " side of substrate can be less than " bottom " side in the referential of standard land
And still fall in the implication on term " top ".As used in this term " ... on " (it is included in right
In it is required that) do not indicate that first layer on the second layer directly contacts on the second layer and directly with the second layer,
It is such unless expressly stated；Can there are third layer or other knots between the second layer on first layer and first layer
Structure.It can be manufactured in multiple position and direction, use or the embodiment of transport device as described herein or product.
It is possible that those skilled in the relevant art can understand many modification and variation according to teaching above.Ability
The technical staff in domain will be recognized that various equivalent combinations and the replacement of each component shown in accompanying drawing.Therefore this hair
Bright scope is not to be limited by the detail specifications but be defined by the following claims.
The foregoing describe some embodiments of the present invention.However, the present invention can be embodied as other concrete forms
Without departing from its spirit or essential characteristics.Described embodiment should all be to be considered merely as illustrating in all respects
Property and it is nonrestrictive.Therefore, the scope of the present invention by appended claims rather than described above limits.
All changes fallen into the implication and scope of the equivalents of claims are by the scope of claims
Covered.
Claims (10)
1. a kind of manufacture method of semiconductor devices, including：
A) first epitaxial layer of the first conduction type is provided on substrate；
B) mask layer is formed on first epitaxial layer, to limit the region where the cylindricality diffusion region of the second conduction type；
C) using the second conductivity type dopant ion of million electro-volt superfine energy, ion implanting is carried out to the first epitaxial layer, to form the second conductivity type dopant body zone；
D) mask layer is removed；
E) carry out high temperature and push away trap, be diffused the second conduction type dopant in the second conduction type body region, obtain the cylindricality diffusion region of the second conduction type.
2. the method as described in claim 1, it is characterised in that the photoresist layer with specific pattern is formed on first epitaxial layer by photoetching process and is used as the mask layer, the photoetching process includes：
The photoresist layer is formed on first epitaxial layer, the thickness of the photoresist layer is 5 microns to 6 microns；
By being aligned, exposing, developing process remove specific part in photoresist layer with the epitaxial layer of expose portion first.
3. the method as described in claim 1, it is characterised in that the thickness that first outer layer prolongs is more than or equal to 10 microns.
4. the method as described in claim 1, it is characterised in that be additionally included in and carry out before high temperature pushes away trap, step a) to step d) being repeated several times, to reach predetermined total epitaxy layer thickness.
5. method as claimed in claim 4, being additionally included in before repeat step a), the surface oxide layer of last layer epitaxial layer is removed.
6. method as claimed in claim 4, it is characterised in that the high temperature pushes away trap so that the cylindricality diffusion region of the second conduction type formed in each epitaxial layer forms connection in vertical direction.
7. the method as described in claim 1, it is characterised in that first conduction type is N-type, and second conduction type is p-type.
8. method as claimed in claim 7, it is characterised in that the second conductivity type dopant ion is boron ion.
9. the method as described in claim 1, it is characterised in that after the mask layer is removed, surface inspection is carried out, to ensure that it is clean that mask layer removes.
10. a kind of semiconductor devices, including the structure manufactured by the method described in any one of claim 1 to 9.
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| CN201610559436.3A CN107622939A (en) | 2016-07-15 | 2016-07-15 | A kind of manufacture method of semiconductor devices |
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| CN201610559436.3A CN107622939A (en) | 2016-07-15 | 2016-07-15 | A kind of manufacture method of semiconductor devices |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112038391A (en) * | 2019-06-03 | 2020-12-04 | 上海先进半导体制造股份有限公司 | Method for manufacturing super junction field effect transistor |
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