CN105405887A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- CN105405887A CN105405887A CN201410461146.6A CN201410461146A CN105405887A CN 105405887 A CN105405887 A CN 105405887A CN 201410461146 A CN201410461146 A CN 201410461146A CN 105405887 A CN105405887 A CN 105405887A
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Abstract
The invention provides a semiconductor device, which comprises a substrate, an epitaxial layer located on the surface of the substrate, a device region located in the epitaxial layer and a sinking layer located on the surface of the epitaxial layer. A buried layer is disposed in the substrate and at the region being in contact with the epitaxial layer and facing the sinking layer. The impurity concentration of the buried layer is higher than that in the substrate. A first diffusion region and a second diffusion region are disposed in the epitaxial layer and respectively surrounding the peripheries of the sinking layer and the buried layer. The first diffusion region is in contact with the second diffusion region and a source region of the device region. The sinking layer, the buried layer, the first diffusion layer and the second diffusion layer are of the same impurity conductivity type. An embodiment of the invention effectively solves the technical problems that to manufacture a radio frequency-lateral double diffused metal oxide semiconductor field-effect transistor for instance in the prior art, as the impurity in a densely doped substrate diffuses upward when a sinking layer drives in at a high temperature, the effective thickness of an epitaxial layer is reduced, and thus the device breakdown voltage is decreased.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of semiconductor device.
Background technology
At present, at radio frequency-cross bimoment (RadioFrequency-LateralDouble-DiffusedMetal-Oxide-Semicon ductorField-EffectTransistor, RF-LDMOS) characteristic feature adopted in structure is back of the body source technology, and namely source electrode is drawn from the device back side.Conventional method corresponding to this technology is the mode injected (being generally P type ion boron) by sinking layer and driven in, and utilizes sinking layer that source electrode is guided to the back side.This method needs long high temperature to drive in could be driven into the injection ion in sinking layer P type high concentration substrate, allows sinking layer and substrate couple together, thus draws source electrode using substrate as the back side.
Fig. 1 is the substrate and epitaxial layer portion structure that utilize back of the body source technology to be formed in existing RF-LDMOS, comprising: the Xia Kuo district 4 of dense doped substrate 1, epitaxial loayer 2, sinking floor 3, sinking floor 3, the Shang Kuo district 5 of dense doped substrate 1.Wherein, dense doped substrate 1 is identical with the doping type in sinking layer 3; The Xia Kuo district 4 of sinking floor 3 and the Shang Kuo district 5 of dense doped substrate 1 be respectively device carry out carrying on the back the high temperature of source technology drive in after Doped ions in corresponding sinking floor 3 and dense doped substrate 1 be diffused into the structure formed in epitaxial loayer 2.
For N-shaped RF-LDMOS, substrate and epitaxial loayer are all the P type boron ions of doping, and sinking layer injects the boron ion that ion is also P type.The dense substrate of P type is that (boron ion source protonatomic mass is little for boron due to doping, diffusion is easy in the semiconductors under high temperature), so in high-temperature hot process, inevitably upwards spread fast, tie up the space of P type epitaxial loayer, epitaxy layer thickness is significantly reduced.
For RF-LDMOS, its puncture voltage determines primarily of the thickness of epitaxial loayer, and epitaxy layer thickness is less, and puncture voltage is less.Therefore, in concrete preparation process, according to the needs of puncture voltage, if epitaxial thickness is expected to be T, so during actual production, epitaxy layer thickness can be set to 2T, reason is exactly need the upper expansion of dense doped substrate from taking into account.But blocked up epitaxial thickness, can increase again the difficulty that sinking layer is connected with substrate, also can increase conducting resistance, this is disadvantageous to device performance simultaneously.
Summary of the invention
The invention provides a kind of semiconductor device, in order to solve the RF-LDMOS that prior art manufactures, it when carrying out sinking floor height temperature and driving in, dense doped substrate expands the effective epitaxy layer thickness caused and reduces, the technical problem that device electric breakdown strength declines.
The embodiment of the present invention provides a kind of semiconductor device, comprising: substrate, be arranged in described substrate surface epitaxial loayer, be positioned at the device region of described epitaxial loayer and be positioned at the sinking layer of described epi-layer surface, wherein:
Contact with described epitaxial loayer in described substrate and the region being right against described sinking layer is provided with buried regions, the impurity concentration of described buried regions is higher than the impurity concentration in described substrate;
Be arranged in described epitaxial loayer, be respectively arranged with the first diffusion region and the second diffusion region around described sinking layer and described buried regions periphery; Described first diffusion region contacts with each other with the source region of described second diffusion region and described device region respectively;
Wherein, described sinking layer, described buried regions, described first diffusion region is identical with the impurity conduction type in described second diffusion region.
Semiconductor device provided by the invention, by contact with epitaxial loayer in the substrate and the region being right against sinking layer arranges buried regions, the impurity concentration of this buried regions is higher than the impurity concentration in substrate; Make sinking layer drive in process at high temperature, the impurity in buried regions is diffused in epitaxial loayer simultaneously and forms the second diffusion region; Reach the object that sinking layer contacts with substrate being contacted with the first diffusion region expanding formation under sinking floor height temperature by the second diffusion region, the heat shortening sinking layer drives in the time, thus the impurity in minimizing substrate carries out time of spreading to the drift region in semiconductor device, reduce the thick end that substrate expands, thus improve the puncture voltage of whole device.
Accompanying drawing explanation
Fig. 1 is the substrate and epitaxial loayer generalized section that utilize back of the body source technology to be formed in existing RF-LDMOS;
The generalized section of the semiconductor device that Fig. 2 provides for the embodiment of the present invention;
The method schematic diagram of the formation of photoetching on the substrate buried regions figure that Fig. 3 a provides for the embodiment of the present invention;
The method schematic diagram of the boron ion implantation formation buried regions that Fig. 3 b provides for the embodiment of the present invention;
The structural representation forming buried regions on substrate that Fig. 3 c provides for the embodiment of the present invention;
The structural representation after deposited on substrates oxide layer that Fig. 4 a provides for the embodiment of the present invention;
The method schematic diagram of the formation of photoetching in the oxide layer buried regions figure that Fig. 4 b provides for the embodiment of the present invention;
The method schematic diagram of the etching oxidation layer that Fig. 4 c provides for the embodiment of the present invention;
Another boron ion implantation method schematic diagram that Fig. 4 d provides for the embodiment of the present invention.
Embodiment
For making the object of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described.For convenience of description, zoomed in or out the size of different layers and region, so size shown in figure and ratio might not represent actual size, also do not reflect the proportionate relationship of size.
The generalized section of the semiconductor device that Fig. 2 provides for the embodiment of the present invention.As shown in Figure 2, this device architecture specifically comprises: substrate 201, be arranged in substrate 201 surface epitaxial loayer 202, be positioned at the device region of epitaxial loayer 202 and be positioned at the sinking layer 203 of epi-layer surface, wherein:
Contact with epitaxial loayer 202 in substrate 201 and the region being right against sinking layer 203 is provided with buried regions 204, the impurity concentration of this buried regions 204 is higher than the impurity concentration in substrate;
Be arranged in epitaxial loayer 202, be respectively arranged with the first diffusion region 205 and the second diffusion region 206 around sinking layer 203 and buried regions 204 periphery; Wherein, the first diffusion region 205 contacts with each other with the source region of the second diffusion region 206 and device region respectively;
Wherein, above-mentioned sinking layer 203, buried regions 204, first diffusion region 205 are identical with the impurity conduction type in the second diffusion region 206.
Above-mentioned substrate 201 is specifically as follows the semi-conducting material with dense doping, and as materials such as silicon, germanium, gallium nitride, GaAs, mixing impurity can be the impurity of P type for conduction type, as boron; The impurity of N-type that also can be conduction type be, as phosphorus, arsenic, antimony.
During due to the RF-LDMOS of existing technique preparation as N-type substrate, the impurity of N-type is as larger relative to its atomic weight of P type ion in phosphorus, plasma, even if carry out high-temperature process to device in device fabrication process, its heat also can not make N-type ion in substrate layer be diffused in a large number in epitaxial loayer, affects the effective epitaxy layer thickness in epitaxial loayer below position, drift region.The structure type of the semiconductor device therefore shown in the present embodiment is more suitable for substrate and is dense doping and mixes the structure type that impurity is the RF-LDMOS device of p type impurity.
In the present embodiment, epitaxial loayer 202 for mixing impurity as boron, phosphorus, arsenic, the material such as silicon, germanium, gallium nitride, GaAs of antimony etc.
In the present embodiment, the device region being arranged in epitaxial loayer 202 is specially the device area of prepared semiconductor device corresponding to epitaxial loayer 202.It will be appreciated by those skilled in the art that as this device area is for realizing the essential device architecture part of certain semiconductor device function, as comprised the structural regions such as source region, drain region, grid, well region and raceway groove.What pay close attention in the above embodiment of the present invention is the sinking layer 203 of source region and prepared semiconductor device in this device region, the position relationship between buried regions 204, first diffusion region 205 and the second diffusion region 206, and is not limited for the particular type of the semiconductor device in this device region and structure.In other words, the semiconductor device shown in the present embodiment can be the existing semiconductor device of any kind.
In the present embodiment, to contact and the region being right against sinking layer 203 is provided with buried regions 204 in substrate 201 with epitaxial loayer 202, the impurity concentration of this buried regions 204 is higher than the impurity concentration in substrate 201.
Concrete, a kind of specific implementation forming buried regions 204 on substrate 201 surface is:
Attached lid photoresistance on the substrate 201, adopts the mask plate identical with preparation sinking layer 203 by the photoetching process of sinking layer light shield, come out in the substrate region just right with sinking layer 203, and other regions still covers photoresistance.This photoetching process as shown in Figure 3 a.
In the subregion of the substrate 201 exposed, inject boron ion form buried regions 204, boron ion implantation energy, for being more than or equal to 50KEV, is less than or equal to 120KEV simultaneously; Implantation dosage is for being more than or equal to 5E15/cm
2, be less than or equal to 1E16/cm simultaneously
2, this photoetching process as shown in Figure 3 b.
Finally, remove the photoresistance on substrate 201 surface, form structural representation as shown in Figure 3 c.
Concrete, the another kind of specific implementation forming buried regions 204 on substrate 201 surface is:
Deposit layer of oxide layer on the substrate 201, this oxide layer can be tetraethoxysilance, and deposit thickness is
deposition process can adopt Low Pressure Chemical Vapor Deposition, also can adopt thermal oxidation technology.The structural representation after deposited on substrates oxide layer that Fig. 4 a provides for the embodiment of the present invention.
Attached lid photoresistance in oxide layer, adopts the mask plate identical with preparation sinking layer 203 by the photoetching process of sinking layer light shield, come out in the oxide layer region just right with sinking layer 203, and other regions still covers photoresistance.This photoetching process as shown in Figure 4 b.
By etching technics, the oxide layer region etch exposed is fallen, and expose the substrate below this region, etching technics specifically can adopt wet-etching technology or dry etch process, does not limit herein.Then remove light ancestral, form structure as illustrated in fig. 4 c.
In the subregion of the substrate 201 exposed, inject boron ion by coating doping process (Doping) and form buried regions 204, in this doping process, ambient temperature is 800 ~ 1000 DEG C, control wafer square resistance 1 ~ 20 ohms/square, and Fig. 4 d is boron ion implantation method schematic diagram.
Wet etching is adopted to remove oxide layer, mixed solution (the Bufferoxideetch of hydrofluoric acid solution or hydrofluoric acid and ammonium fluoride is adopted in the present embodiment, BOE) wet etching process is realized, the formation schematic diagram of final formation buried regions as shown in Figure 3 b.
In the present embodiment, be arranged in epitaxial loayer 202, be respectively arranged with the first diffusion region 205 and the second diffusion region 206 around sinking layer 203 and buried regions 204 periphery; This first diffusion region 205 contacts with each other with the source region of the second diffusion region 206 and device region respectively; And then realize source region and draw from substrate side.
Wherein, sink in the present embodiment layer 203, buried regions 204, first diffusion region 205 is identical with the impurity conduction type in the second diffusion region 206.
Further, above-mentioned first diffusion region 205 is the structural region that in sinking layer 203, impurity is formed after being at high temperature diffused into epitaxial loayer 202.
Further, above-mentioned second diffusion region 206 is the structural region that in buried regions 204, impurity is formed after being at high temperature diffused into epitaxial loayer 202.
The substrate forming buried regions 204 forms epitaxial loayer 202 successively by predetermined process flow process, sinking layer 203 and device region.Wherein after formation epitaxial loayer 202, high temperature need be carried out to whole device and drive in, be connected with substrate 201 with above-mentioned first diffusion region 205 making Impurity Diffusion in sinking layer 203 enter into epitaxial loayer 202 formation.In the present embodiment, due in substrate 201 and the position being right against sinking layer 203 has been pre-formed buried regions 204, make to carry out while high temperature drives in process at above-mentioned sinking layer 203, impurity in buried regions 204 also epitaxial layers 202 diffuses to form the second diffusion region 206, contacts by making the first diffusion region 205 object reaching the first diffusion region 205 and be connected with substrate 201 with the second diffusion region 206.Obviously, time needed for mode that sinking layer 203 contacts with substrate 201 substantially reduces relative to the simple mode adopting sinking layer 203 to drive in adopt method that sinking layer 203 and buried regions 204 spread simultaneously to realize.
Further, also comprise in the above-described embodiments: the 3rd diffusion region 207.In practical devices preparation process, in the process that above-mentioned high temperature drives in, foreign ion in substrate 201 also can diffusion and form the 3rd diffusion region 207 in epitaxial layers 202, and the mode adopting method that sinking layer 203 and buried regions 204 spread simultaneously to realize sinking layer 203 to contact with substrate 201, make heating drive in the time greatly to shorten, thus reduce the time of diffusion in the impurity epitaxial layers 202 in substrate 201, it also reduce the thickness of the 3rd diffusion region 207.In actual process, the thickness of the 3rd diffusion region 207 is at least less than the half of epitaxial loayer 202 thickness, the decline of the whole device electric breakdown strength brought to avoid the upper expansion of substrate 201.The thickness of buried regions of the thickness being directed to the 3rd diffusion region 207 by being formed, doping content and high temperature drive in the time and regulate.
In the above-described embodiments, the conduction type of the impurity in substrate 201 is for being specially P type.
In the above-described embodiments, the thickness of buried regions 204 is 0.1 ~ 0.4 micron.
Semiconductor device provided by the invention, by contact with epitaxial loayer in the substrate and the region being right against sinking layer arranges buried regions, the impurity concentration of this buried regions is higher than the impurity concentration in substrate; Make sinking layer drive in process at high temperature, the impurity in buried regions is diffused in epitaxial loayer simultaneously and forms the second diffusion region; The first diffusion region formed after being driven in sinking floor height temperature by the second diffusion region is contacted and reaches the object that sinking layer contacts with substrate, the high temperature shortening sinking layer drives in the time, thus also just shorten foreign ion in substrate and diffuse into the time of epitaxial loayer, reduce the thick end that substrate expands, thus improve the anti-breakdown voltage capabilities of whole device.
Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (9)
1. a semiconductor device, is characterized in that, comprising: substrate, be arranged in described substrate surface epitaxial loayer, be positioned at the device region of described epitaxial loayer and be positioned at the sinking layer of described epi-layer surface, wherein:
Contact with described epitaxial loayer in described substrate and the region being right against described sinking layer is provided with buried regions, the impurity concentration of described buried regions is higher than the impurity concentration in described substrate;
Be arranged in described epitaxial loayer, be respectively arranged with the first diffusion region and the second diffusion region around described sinking layer and described buried regions periphery; Described first diffusion region contacts with each other with the source region of described second diffusion region and described device region respectively;
Wherein, described sinking layer, described buried regions, described first diffusion region is identical with the impurity conduction type in described second diffusion region.
2. semiconductor device according to claim 1, is characterized in that, also comprises:
Be arranged in described epitaxial loayer, described substrate surface is provided with the 3rd diffusion region; The impurity conduction type of described 3rd diffusion region is identical with the conduction type of the impurity in described substrate.
3. semiconductor device according to claim 1 and 2, is characterized in that, described first diffusion region is formed after in described sinking layer, impurity is at high temperature diffused into described epitaxial loayer.
4. semiconductor device according to claim 1 and 2, is characterized in that, described second diffusion region is that in described buried regions, impurity is formed after being at high temperature diffused into described epitaxial loayer.
5. semiconductor device according to claim 1 and 2, is characterized in that, the conduction type of the impurity in described substrate is P type.
6. semiconductor device according to claim 2, is characterized in that, the thickness of described 3rd diffusion region is less than the half of described epitaxy layer thickness.
7. semiconductor device according to claim 1 and 2, is characterized in that, the thickness of described buried regions is 0.1 ~ 0.4 micron.
8. semiconductor device according to claim 1, is characterized in that, described substrate is any one material in silicon, germanium, gallium nitride.
9. semiconductor device according to claim 5, is characterized in that, the impurity in described substrate is boron ion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410461146.6A CN105405887A (en) | 2014-09-11 | 2014-09-11 | Semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410461146.6A CN105405887A (en) | 2014-09-11 | 2014-09-11 | Semiconductor device |
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| CN105405887A true CN105405887A (en) | 2016-03-16 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997023901A1 (en) * | 1995-12-21 | 1997-07-03 | Philips Electronics N.V. | Method of manufacturing a resurf semiconductor device, and a semiconductor device manufactured by such a method |
| CN101599462A (en) * | 2009-06-13 | 2009-12-09 | 无锡中微爱芯电子有限公司 | Production method of high and low voltage devices based on thin epitaxy |
| CN104037231A (en) * | 2014-06-18 | 2014-09-10 | 浙江大学 | High-sided transverse double diffused field effect transistor |
-
2014
- 2014-09-11 CN CN201410461146.6A patent/CN105405887A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997023901A1 (en) * | 1995-12-21 | 1997-07-03 | Philips Electronics N.V. | Method of manufacturing a resurf semiconductor device, and a semiconductor device manufactured by such a method |
| CN101599462A (en) * | 2009-06-13 | 2009-12-09 | 无锡中微爱芯电子有限公司 | Production method of high and low voltage devices based on thin epitaxy |
| CN104037231A (en) * | 2014-06-18 | 2014-09-10 | 浙江大学 | High-sided transverse double diffused field effect transistor |
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