CN104518023A - High-voltage LDMOS (laterally-diffused metal oxide semiconductor) device - Google Patents

High-voltage LDMOS (laterally-diffused metal oxide semiconductor) device Download PDF

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CN104518023A
CN104518023A CN201310460839.9A CN201310460839A CN104518023A CN 104518023 A CN104518023 A CN 104518023A CN 201310460839 A CN201310460839 A CN 201310460839A CN 104518023 A CN104518023 A CN 104518023A
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type
layer
voltage
withstand voltage
ldmos device
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CN104518023B (en
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祁树坤
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CSMC Technologies Corp
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Wuxi CSMC Semiconductor Co Ltd
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A high-voltage LDMOS (laterally-diffused metal oxide semiconductor) device comprises a P-channel region, an N-drift region, a voltage-withstanding layer and a p-type substrate positioned at the bottom, wherein the voltage-withstanding layer is positioned between the p-type substrate and the N-drift region. The high-voltage LDMOS device has the advantages that the voltage-withstanding layer is introduced into the high-voltage LDMOS device, so that drive-in time is shortened technologically, current channel sectional area is increased and on-resistance is improved; meanwhile, longitudinal and lateral voltage withstanding is improved.

Description

High-voltage LDMOS device
Technical field
The present invention relates to integrated circuit fields, particularly relate to a kind of high-voltage LDMOS device.
Background technology
Due to BCD(bipolar-CMOS-DMOS) high pressure of technology, low-power consumption, advantage that integrated level is high, the HVIC be made up of BCD technology (high voltage integrated circuit), SPIC(smart-power IC) etc. integrated circuit be more and more applied to that motor drives, the IPM(Intelligent Power Module of high-power LED illumination and white domestic appliances) in frequency-variable module.The core devices UHV-NLDMOS(superhigh pressure-N-type lateral double diffusion metal oxide semiconductor of BCD technology) more occupy first of development difficulty with withstand voltage high and low conducting resistance, each major company competitively releases the device architecture differed from one another.Form dark knot, N-type (electron type) drift region that concentration is high to obtain low on-resistance, but low withstand voltage can only be obtained; Falling field layer by being formed on N-type drift region surface along the P type (cavity type) of channel direction zonal distribution, forming certain junction depth through pushing away trap, exhaust to strengthen drift region to reach the charge balance in deeply tying with N-type, improve withstand voltage; And after superheating process, N-type drift region impurity concentration is subject to P type and falls the impact of field layer impurity and reduce, effective current cross-sectional passage reduces, and weakens the path that electric current flows through, improves conducting resistance on the contrary.Therefore for obtaining high withstand voltage, low on-resistance, P type must be reduced by other approach and falling field layer impurity to the negative effect of N-type drift region impurity concentration, extremely efficient current channel, reduce conducting resistance and obtain high withstand voltage.
Because prior art cannot take into account the forward demand of high withstand voltage and low on-resistance simultaneously, due to N-type drift region, to push away the trap time long simultaneously, and bring the negative effect of cost and energy consumption, the device needing proposition new is to carry out optimization, the improvement of technique and device two aspect.
Summary of the invention
The technical problem to be solved in the present invention is to provide one can be increased withstand voltage and reduce conducting resistance high-voltage LDMOS device.
Technical scheme of the present invention is a kind of high-voltage LDMOS device, and comprise P type channel region, N-type drift region, Withstand voltage layer and be positioned at the P type substrate of bottom, described Withstand voltage layer is between P type substrate and N-type drift region.
High-voltage LDMOS device as above, described Withstand voltage layer comprises staggered p type buried layer and n type buried layer.
High-voltage LDMOS device as above, described Withstand voltage layer extends to the horizontal both end sides of LDMOS device.
High-voltage LDMOS device as above, described Withstand voltage layer perpendicular abutment N-type drift region.
High-voltage LDMOS device as above, described P type channel region and N-type drift region are in horizontal, and P type channel region and N-type drift region are all positioned at directly over Withstand voltage layer.
High-voltage LDMOS device as above, described P type substrate is positioned at below Withstand voltage layer, and does not extend to the two ends of Withstand voltage layer.
High-voltage LDMOS device as above, described p type buried layer and n type buried layer are all perpendicular to N-type drift region.
High-voltage LDMOS device as above, described Withstand voltage layer is shaping before formation extension.
High-voltage LDMOS device as above, it is shaping that described Withstand voltage layer injects knot by mask plate photoetching.
High-voltage LDMOS device as above: described Withstand voltage layer comprises at least two n type buried layers and the some p type buried layers between n type buried layer.
High-voltage LDMOS device of the present invention passes through to introduce Withstand voltage layer, makes technique reduces to push away the trap time, improves current channel area of section, reduces conducting resistance, simultaneously laterally withstand voltage by improving longitudinal withstand voltage lifting.
Accompanying drawing explanation
Accompanying drawing 1 is the structural representation of invention first embodiment mesohigh LDMOS device;
Accompanying drawing 2 is the partial schematic diagram of invention first embodiment mesohigh LDMOS device.
Embodiment
Below in conjunction with each execution mode shown in the drawings, the present invention is described in detail; but should be noted that; these execution modes are not limitation of the present invention; those of ordinary skill in the art are according to these execution mode institute work energy, method or structural equivalent transformations or substitute, and all belong within protection scope of the present invention.
Fig. 1 is the schematic diagram of first embodiment of the invention mesohigh LDMOS device 100, and it comprises P type substrate 10, be positioned at Withstand voltage layer 20 above P type substrate, be positioned at P type channel region 30, the N-type drift region 40 above Withstand voltage layer 20 and be positioned at N-type drift region overlying p-type and fall field layer 50.
Described P type substrate 10 is as the substrate of high-voltage LDMOS device 100, and P type substrate is arranged at the below of Withstand voltage layer 20, and does not extend to Withstand voltage layer 20 both sides and top.P type channel region 30 and N-type drift region 40 are in horizontal, and both are all positioned at directly over Withstand voltage layer 20.Described Withstand voltage layer 20, before formation extension, adopts mask plate photoetching to inject knot shaping, through extension and follow-up thermal process, slows down concentration gradient, can be connected, make Potential Distributing more even longitudinally with high pressure drift region.
Described Withstand voltage layer comprises p type buried layer 21 and n type buried layer 22, and p type buried layer 21 is staggered in level with n type buried layer 22, and described p type buried layer 21 and n type buried layer 22 are all perpendicular to N-type drift region 40.Withstand voltage layer 20 extends horizontally to the both end sides of high-voltage LDMOS device, and it aligns at least partly with the N-type drift region in the vertical direction of the side of being located thereon, and the n type buried layer 22 in Withstand voltage layer can realize effect that current path is larger, conducting resistance is less.In the preferred embodiment, Withstand voltage layer 20 perpendicular abutment N-type drift region.
When drain terminal plus high-pressure thus introduce high potential time, p type buried layer 21 and n type buried layer 22 can weaken the transverse direction of electric field and longitudinal vector, and push a part of depletion layer to P type substrate 10 depths, thus reduce the electric field on N-type drift region 40 and surface, P type channel region 30, improve overall device withstand voltage level.Meanwhile, n type buried layer 22 also can realize increasing current channel and reducing conducting resistance object; The setting of p type buried layer 21, then reduce the impurity implantation dosage that field layer 50 falls in P type, maximized longitudinal direction can be obtained withstand voltage, making it be greater than to fall the transverse direction of field layer and N-type drift region by P type can withstand voltage, realize transverse variable P type and fall field layer size, final reduction conducting resistance improves withstand voltage simultaneously, reduces gate leakage capacitance, improves its switching characteristic.In addition, first avalanche breakdown occur in n type buried layer instead of P type substrate surface, enhances the reliability of high-voltage LDMOS device 100.
Fig. 2 is the second embodiment of the present invention, and Fig. 2 is the partial schematic diagram (omit element and refer to Fig. 1) of high-voltage LDMOS device 500, and in the present embodiment except the structure of Withstand voltage layer, other structures are identical with the first embodiment, do not repeat them here.Withstand voltage layer 50 in this enforcement comprises n type buried layer 51 and the multiple p type buried layers 52 between n type buried layer are formed, and can realize equally reducing conducting resistance and improving withstand voltage effect (concrete principle please refer to the first embodiment) by n type buried layer 51 and p type buried layer 52.
In sum, the present invention introduces Withstand voltage layer by high-voltage LDMOS device, makes technique reduces to push away the trap time, improves current channel area of section, improves conducting resistance, simultaneously by improve longitudinally withstand voltage use promote laterally withstand voltage.

Claims (10)

1. a high-voltage LDMOS device, is characterized in that: comprise P type channel region, N-type drift region, Withstand voltage layer and be positioned at the P type substrate of bottom, described Withstand voltage layer is between P type substrate and N-type drift region.
2. high-voltage LDMOS device as claimed in claim 1, is characterized in that: described Withstand voltage layer comprises staggered p type buried layer and n type buried layer.
3. high-voltage LDMOS device as claimed in claim 2, is characterized in that: described Withstand voltage layer extends to the horizontal both end sides of high-voltage LDMOS device.
4. high-voltage LDMOS structure as claimed in claim 2, is characterized in that: described Withstand voltage layer perpendicular abutment N-type drift region.
5. high-voltage LDMOS device as claimed in claim 3, is characterized in that: described P type channel region and N-type drift region are in horizontal, and P type channel region and N-type drift region are all positioned at directly over Withstand voltage layer.
6. high-voltage LDMOS device as claimed in claim 2, is characterized in that: described P type substrate is positioned at below Withstand voltage layer, and does not extend to the two ends of Withstand voltage layer.
7. the high-voltage LDMOS device as described in claim the 2, is characterized in that: described p type buried layer and n type buried layer are all perpendicular to N-type drift region.
8. the high-voltage LDMOS device according to any one of claim 2 to 7, is characterized in that: described Withstand voltage layer is shaping before formation extension.
9. high-voltage LDMOS device as claimed in claim 8, is characterized in that: it is shaping that described Withstand voltage layer injects knot by mask plate photoetching.
10. high-voltage LDMOS device as claimed in claim 1, is characterized in that: described Withstand voltage layer comprises at least two n type buried layers and the some p type buried layers between n type buried layer.
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Cited By (8)

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Publication number Priority date Publication date Assignee Title
CN105679831A (en) * 2016-03-16 2016-06-15 上海华虹宏力半导体制造有限公司 Lateral diffusion field effect transistor and manufacturing method thereof
CN106231213A (en) * 2016-09-29 2016-12-14 北方电子研究院安徽有限公司 A kind of band shutter CCD pixel structure eliminating SMEAR effect
CN107180856A (en) * 2017-05-26 2017-09-19 电子科技大学 A kind of PMOS device structure
CN108346696A (en) * 2017-01-22 2018-07-31 中芯国际集成电路制造(上海)有限公司 LDMOS device and its manufacturing method
TWI695434B (en) * 2018-05-25 2020-06-01 大陸商矽力杰半導體技術（杭州）有限公司 Lateral diffusion metal oxide semiconductor structure and its forming method
CN112599599A (en) * 2020-12-03 2021-04-02 杰华特微电子（杭州）有限公司 Lateral double-diffused transistor and manufacturing method thereof
CN113410299A (en) * 2020-03-16 2021-09-17 电子科技大学 High-voltage-resistance n-channel LDMOS device and preparation method thereof
CN113594254A (en) * 2021-07-29 2021-11-02 上海华虹宏力半导体制造有限公司 LDMOS device structure for improving transconductance

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CN102130164A (en) * 2010-01-18 2011-07-20 上海华虹Nec电子有限公司 Buried layer of LDMOS (laterally diffused metal-oxide semiconductor)

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CN101969074B (en) * 2010-10-28 2012-07-04 电子科技大学 High voltage lateral double diffused MOSFET element
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US5883413A (en) * 1995-07-19 1999-03-16 U.S. Philips Corporation Lateral high-voltage DMOS transistor with drain zone charge draining
CN102034876A (en) * 2009-09-30 2011-04-27 株式会社电装 Semiconductor device having SOI substrate and method for manufacturing the same
CN102130164A (en) * 2010-01-18 2011-07-20 上海华虹Nec电子有限公司 Buried layer of LDMOS (laterally diffused metal-oxide semiconductor)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105679831A (en) * 2016-03-16 2016-06-15 上海华虹宏力半导体制造有限公司 Lateral diffusion field effect transistor and manufacturing method thereof
CN106231213A (en) * 2016-09-29 2016-12-14 北方电子研究院安徽有限公司 A kind of band shutter CCD pixel structure eliminating SMEAR effect
CN106231213B (en) * 2016-09-29 2023-08-22 北方电子研究院安徽有限公司 CCD pixel structure with shutter capable of eliminating SMEAR effect
CN108346696A (en) * 2017-01-22 2018-07-31 中芯国际集成电路制造(上海)有限公司 LDMOS device and its manufacturing method
CN107180856A (en) * 2017-05-26 2017-09-19 电子科技大学 A kind of PMOS device structure
CN107180856B (en) * 2017-05-26 2020-01-17 电子科技大学 PMOS device structure
TWI695434B (en) * 2018-05-25 2020-06-01 大陸商矽力杰半導體技術（杭州）有限公司 Lateral diffusion metal oxide semiconductor structure and its forming method
CN113410299A (en) * 2020-03-16 2021-09-17 电子科技大学 High-voltage-resistance n-channel LDMOS device and preparation method thereof
CN112599599A (en) * 2020-12-03 2021-04-02 杰华特微电子（杭州）有限公司 Lateral double-diffused transistor and manufacturing method thereof
CN113594254A (en) * 2021-07-29 2021-11-02 上海华虹宏力半导体制造有限公司 LDMOS device structure for improving transconductance
CN113594254B (en) * 2021-07-29 2024-01-23 上海华虹宏力半导体制造有限公司 LDMOS device structure for improving transconductance

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